- Line deflection output UNIT + SMPS Pulse Command/POWER drive + Supply Trafo + EHT
- Synch + Frame deflection + Drive UNIT
- Signal Processing / Video Luminance + Chrominance + RGB Amplifier
- IF Video + Sound
- Sound amplifier Unit
LINE/HORIZONTAL DEFLECTION UNIT (HORIZONTAL- MODUL Best.Nr. 7807021000)
SMPS - BU208A (TELEFUNKEN)
LINE DEFLECTION OUTPUT- BU208A (TELEFUNKEN)
NOTE THAT THE EHT TRAFO HAS FUNCTION EVEN AS LINE SYNCHRONIZED SUPPLY SMPS TRAFO.
npn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C
SABA ULTRACOLOR T56Q75 QUARTZ COMPUTER CHASSIS Q110 CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:
Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.
It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.
V o = V i . δ
Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V 0 . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.
In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.
In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 i
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transstors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.
This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.
The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.
In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.
Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.
Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondar
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
SABA ULTRACOLOR T56Q75 QUARTZ COMPUTER CHASSIS Q110 Regulated deflection circuit:
1. A deflection circuit comprising:
a deflection winding;
a deflection generator coupled to said deflection winding for generating scanning current in said deflection winding during a deflection cycle, said deflection generator including a retrace capacitance coupled to said deflection winding for forming a retrace resonant circuit therewith to produce a retrace pulse voltage during a retrace interval of said deflection cycle;
a second capacitance coupled to said inductance for forming a second resonant circuit therewith, said second resonant circuit being coupled to said deflection generator;
a source of energy; and
switching means coupled to said source and to said second resonant circuit in a self-oscillating configuration, said switching means being responsive to a deflection rate switching signal for storing a controllable amount of energy from said source in said second resonant circuit, said retrace pulse voltage being applied to said second resonant circuit to provide for the transfer of energy between said second and retrace resonant circuits,
said switching means in the absence of said deflection rate switching signal undergoing free-running oscillation.
2. A deflection circuit according to claim 1 wherein said switching means is coupled to said source and to said second resonant circuit in a blocking oscillator configuration. 3. A deflection circuit according to claim 2 wherein the frequency of said free-running oscillation is lower than the frequency of said deflection cycle. 4. A deflection circuit according to claims 1 or 2 wherein said switching means includes first and second switching devices coupled to said inductance in a push-pull relationship. 5. A deflection circuit according to claim 4 wherein the frequency of free-running oscillation is such that during said free-running oscillation, each of said first and second switching devices conducts for a duration that is longer than the duration of said trace interval. 6. A deflection circuit according to claim 5 wherein the amount of energy stored in said second resonant circuit at the end of said trace interval remains substantially unchanged as said controllable instant varies. 7. A deflection circuit according to claim 1 wherein said switching arrangement includes a first controllable switching device coupled to said source and to said second resonant circuit, a second controllable switching device coupled to said second resonant circuit, and a control circuit responsive to said deflection rate signal for changing the conductive state of said first switching device at a controllable instant within the trace interval of said deflection cycle and of said second switching device within said retrace interval. 8. A deflection circuit according to claim 7 wherein said control circuit is responsive to a deflection circuit energy level to vary said controllable instant as said energy level varies. 9. A deflection circuit according to claim 8 wherein the amount of energy stored in said second resonant circuit at the end of said trace interval remains substantially unchanged as said controllable instant varies. 10. A deflection circuit according to claims 1, 7 or 9 wherein said second resonant circuit is coupled to said deflection generator by way of a transformer, a first winding thereof being coupled to said second resonant circuit, a second winding thereof being coupled to said retrace resonant circuit. 11. A deflection circuit according to claim 7 wherein said first and second controllable switching devices include first and second bidirectionally conductive main current paths, respectively, the two main current paths being coupled in series across said source of energy, said inductance and said second capacitance being coupled in series across one of said two main current paths. 12. A deflection circuit according to claim 11 wherein said second resonant circuit is coupled to said deflection generator by way of a flyback transformer, a first winding thereof being coupled in series with said inductance and second capacitance across said one main current path, a second winding thereof being coupled to said retrace resonant circuit. 13. A deflection circuit according
her of the two controllable switches, during the time that the conduction in the main current path of either of the two switches is being cut off. 17. A deflection circuit according to claim 1 wherein said deflection generator includes a controllable output device coupled to said deflection winding, a deflection oscillator coupled to a control terminal of said output device for switching said output device on within the trace interval of said deflection cycle and for switching said output device off to initiate said retrace interval, means for detecting oscillation of said retrace resonant circuit, and means coupled to said deflection oscillator and to said detecting means for maintaining said output device off when oscillation of said retrace resonant circuit is detected. 18. A deflection circuit according to claim 17 wherein said second resonant circuit is coupled to said deflection generator by way of a transformer, a first winding thereof being coupled to said second resonant circuit, a second winding thereof being coupled to said retrace resonant circuit, a third winding thereof comprising said detecting means. 19. A deflection circuit, comprising:
a deflection winding;
a deflection generator coupled to said deflection winding for generating scanning current in said deflection winding during a deflection cycle, said deflection generator including a retrace capacitance coupled to said deflection winding for forming a retrace resonant circuit therewith to develop a retrace pulse voltage during a retrace interval of said deflection cycle;
a second resonant circuit including an inductance, said retrace pulse applied voltage being applied thereto;
a source of input voltage;
first and scond controllable switches coupled to said second resonant circuit, each switch becoming conductive after the other switch becomes substantially nonconductive, said first switch when conductive coupling said source of input voltage to said second resonant circuit to enable the transfer of energy between said source and said second resonant circuit and when nonconductive decoupling said source from said second resonant circuit, said second switch when conductive enabling the transfer of energy between said second resonant circuit and said retrace resonant circuit.
20. A deflection circuit according to claim 19 wherein said first and second switches are coupled to said inductance in a push-pull relationship. 21. A deflection circuit according to claims 19 or 20 including control means coupled to control terminals of said first and second switches and responsive to a deflection circuit energy level and a deflection rate control signal for turning off said second switch at an instant within the trace interval of said deflection cycle that varies as said energy level varies to provide regulation thereof and for turning off said first switch near the beginning of the retrace interval. 22. A deflection circuit according to claim 21 wherein said two switches are bidirectionally conductive. 23. A deflection circuit according to claim 21 wherein said inductance includes a main winding coupled to output terminals of said first and second switches and first and second control windings coupled to the respective control terminals of said first and second switches to provide regenerative feedback of the voltages at said output terminals. 24. A deflection circuit according to claim 23 wherein, in the absence of said deflection rate control signal, said regenerative feedback produces oscillation of the voltages at said output terminals at a frequency lower than the frequency of said deflection cycle. 25. A deflection circuit according to claim 24 wherein said deflection generator includes a controllable output device coupled to said deflection winding, a deflection oscillator coupled to a control terminal of said output device for switching said output device on within the trace interval of said deflection cycle and for switching said output device off to initiate said retrace interval, means for detecting oscillation of said retrace resonant circuit, and means coupled to said deflection oscillator and to said detecting means for maintaining said output device off when oscillation of said retrace resonant circuit is detected. 26. A deflection circuit according to claim 21 wherein said control means includes means for detecting an overload condition within said deflection circuit, means responsive to the detected overload condition for establishing the instant within the trace interval that said second switch is turned off at an instant that provides substantially reduced energy transfer to said retrace resonant circuit. 27. A deflection circuit according to claims 19 or 20 wherein said second resonant circuit includes a capacitance, said first switch when conductive applying said input voltage across the series arrangement of said second resonant circuit capacitance and said inductance. 28. A deflection circuit according to claim 27 including a flyback transformer having a first winding coupled to said second switch and a second winding coupled to said retrace resonant circuit for developing a retrace pulse voltage across said flyback tranformer first winding, said second switch when conductive applying said retrace pulse voltage across said series arrangement. 29. A deflection circuit, comprising:
means for developing an input voltage between first and second input terminals;
first and second controllable switches, each having a main current path and a control terminal for controlling conduction therein, the two main current paths being coupled together at an output terminal and further being coupled in a series arrangement between said first and second input terminals;
a first resonant circuit including an inductance coupled between said output terminal and one of said first and second input terminals;
a deflection winding;
a deflection generator coupled to said deflection winding for generating scanning current in said deflection winding during a deflection cycle and further including a retrace resonant circuit that directly applies a retrace pulse voltage to said first resonant circuit;
a control circuit coupled to the control terminals of both switches for alternately turning off conduction in the main paths of said two switches during a deflection cycle to store energy in said inductance that is transferred to said retrace resonant circuit during application of said retrace pulse voltage to said first resonant circuit; and
a capacitance coupled between said output terminal and one of said first and second input terminals to accept the flow of current from said inductance when conduction in the main path of one switch is being turned off and prior to the commencement of conduction in the the main path of the other switch to avoid any significant simultaneous conduction in the main paths of both switches.
30. A deflection circuit according to claim 29 including a voltage divider having first and second end terminals coupled respectively to said first and second input terminals, having a third terminal intermediate the two voltage divider end terminals coupled to said output terminal, having a fourth terminal intermediate one of said voltage divider end terminals and said voltage divider third terminal coupled to the control terminal of one of said switches, and having a fifth terminal intermediate the other one of said voltage divider end terminals and said voltage divider third terminal coupled to the control terminal of the other one of said switches. 31. A deflection circuit according to claim 29 wherein said deflection generator includes a retrace capacitance coupled to said deflection winding for forming a retrace resonant circuit therwith to generate a retrace pulse voltage during a retrace interval of said deflection cycle, said retrace resonant circuit being coupled to said first resonant circuit during the retrace interval to transfer energy therebetween. 32. A deflection circuit according to claim 31 wherein the first resonant circuit is coupled to said deflection generator by way of a flyback transformer, a first winding thereof being coupled to said first resonant circuit, a second winding thereof being coupled to said retrace resonant circuit. 33. A deflection circuit according to claim 31 wherein said control circuit includes means for regneratively feeding back the voltage at said output terminal to produce free-running oscillation of said switching means in the absence of retrace pulse generation. 34. A deflection circuit according to claim 33 wherein said first resonant circuit includes a capacitance coupled in series with said inductance between said output terminal and said one input terminal. 35. A deflection circuit, comprising:
a deflection winding;
an inductance coupled to said deflection generator;
a source of energy;
switching means coupled to said source and to said inductance and responsive to a deflection rate switching signal for storing a controllable amount of energy from said source in said inductance, said retrace pulse voltage being applied to said inductance to provide for the transfer of energy between said inductance and said retrace resonant circuit; and
means for regeneratively feeding back the output of said switching means to produce free-running oscillation thereof in the absence of said deflection rate switching signal.
Known AC power line or mains isolated television receivers show a variety of design approaches for the power supply circuitry. In one design, a 50 or 60 cycle mains transformer may be used to provide electrical isolation. The mains transformer, however, is relatively heavy and bulky. The magnetic stray field produced by the transformer may introduce purity registration errors in a color television receiver. Furthermore, since the mains transformer provides only electrical isolation, additional voltage regulation circuitry may be needed.
A feature of the invention is a switching power supply requiring no specialized components and using simplified control circuitry. The power supply provides intrinsic protection against overloads and short circuits and does not require a separate start-up transformer.
A deflection generator is coupled to a deflection winding for generating scanning current during a deflection cycle. The deflection generator includes a retrace capacitance coupled to the deflection winding for forming a retrace resonant circuit therewith to produce a retrace pulse voltage during a retrace interval of the deflection cycle. A second resonant circuit including an inductance is coupled to the retrace resonant circuit to enable energy to be transferred therebetween. A switching arrangement is coupled to a source of energy and to the second resonant circuit and is responsive to a deflection rate switching signal for storing a controllable amount of energy from the source in the second resonant circuit.
In one inventive aspect, the switching arrangement forms a self-oscillating arrangement with the second resonant circuit to produce free-running oscillation, in the absence of the deflection rate switching signal. Such an arrangement provides for soft-start operation and limited energy transfer during short-circuit conditions.
In another inventive aspect, the switching arrangement comprises first and second controllable switches coupled to the second resonant circuit. Each switch becomes conductive after the other switch has become nonconductive. The first switch when conductive couples the source of energy to the second resonant circuit to enable the transfer of energy therebetween. The first switch when nonconductive decouples the source from the second resonant circuit. The second switch when conductive enables the transfer of energy between the second resonant circuit and the retrace resonant circuit.
FIGS. 1a and 1b illustrate in simplified schematic form two embodiments of a regulated deflection circuit embodying the invention;
FIGS. 2a and 2b illustrate a detailed embodiment of a regulated deflection circuit embodying the invention;
FIG. 3 illustrates an embodiment of a regulator control circuit for the circuit of FIGS. 2a and 2b;
FIG. 4 illustrates waveforms associated with the operation of the regulator control circuit of FIG. 3;
FIGS. 5-12 illustrate waveforms associated with the operation of the circuits of FIGS. 1a, 1b, 2a and 2b;
FIG. 13 illustrates another embodiment of a regulator control circuit for the circuit of FIGS. 2a and 2b; and
FIGS. 14 and 15 illustrate waveforms associated with the operation of the circuit of FIG. 13.
In the Drawing figures, the convention chosen for the direction of the voltage arrow between two terminals is such that the negative terminal is considered the reference terminal nearest which the tail of the arrow is located.
FIGS. 1a and 1b illustrate in simplified schematic form a regulated television receiver deflection circuit and power supply embodying the invention. FIG. 1a illustrates a version not conductively isolated from the AC power mains source and FIG. 1b illustrates an isolated version. Switching devices S1 and S2 form a blocking oscillator arrangement 30 with an inductor L1 and a capacitor C5. The conduction of both switches is controlled by a positive feedback signal, not illustrated in FIGS. 1a and 1b, derived from the voltage developed across inductor L1 and provided to a regulator control circuit 26. Included in FIGS. 1a and 1b are the mains supply rectifier 24 with its filter capacitor C1, the horizontal deflection circuit 60, and the flyback transformer T1. Not illustrated in FIGS. 1a and 1b are the various load circuits of the television receiver that are coupled to windings of the flyback transformer.
To describe the free-running operation of blocking oscillator 30 of FIG. 1a, for example, assume horizontal trace switch 35 of horizontal deflection circuit 60 is shortcircuited to ground. Blocking oscillator 30 will free-run at a frequency determined by the values of L1 and C5. This frequency may be chosen about 2 or more times lower than the horizontal deflection frequency, f H . The free-running frequency is selected lower than the horizontal deflection frequency in order to permit proper synchronization of blocking oscillator operation with horizontal scanning current generation when the blocking oscillator operates in the deflection synchronized mode. However, if the free-running frequency is selected too low, unnecessarily high peak currents in inductor L1 are developed during free-running operation.
The choice of the L to C ratio of inductor L1 and capacitor C5 determines the peak input current or inductor current i L that will flow during free-running operation and therefore determines the maximum available power that can be consumed. Free-running operation also occurs in case of a short-circuited load being produced across any of the windings of flyback transformer T1.
The switching voltage V S2 across switch S2 and the inductor current i L flowing during free-running operation is illustrated in FIGS. 5a and 5b. The voltage switching waveform across switch S1, not illustrated, is 180° out of phase with the waveform of FIG. 5a. Most of the power flowing through the two switches is reactive in nature and, thus, the actual power consumption is very low. The power consumption equals the losses in switches S1 and S2 and in the resistive components of inductor L1 and capacitor C5.
To describe synchronized oscillator operation, assume that horizontal output transistor Q10 of FIG. 1a is being switched at a horizontal rate to generate scanning current in horizontal deflection winding L H and that a retrace pulse voltage V r , illustrated in FIG. 6a, is being generated at the collector electrode of output transistor Q10. From time t 2 within the horizontal trace interval of FIGS. 6a-6c to the later time t 0 , the beginning of the next horizontal retrace interval, switch S2 is open and switch S1 is closed. The inductor current i L flows through switch S1, inductor L1, capacitor C5 and trace switch 35 to ground. At time t 0 , the energy, I p1 2 L/2, is stored in inductor L1 where L is the inductance of inductor L1 and I p1 is the peak current flowing in inductor L1 at time t 0 .
Between times t 1 and t 2 , the current i L circulates through switch S2, inductor L1, capacitor C5 and the now closed trace switch 35. During this interval, energy stored in capacitor C5 discharges back into inductor L1. At time t 2 , regulator control circuit 26 opens switch S2 and closes switch S1. The stored energy in inductor L1 now transfers back into the main filter capacitor C1 until the zero-crossover instant t 3 of the inductor current i L . From time t 3 until the beginning of the next retrace interval, energy is again stored in indcutor L1 for subsequent transferral to retrace resonant circuit 50 and to the load circuits coupled to the various windings of flyback transformer T1.
The operation of the circuit of FIG. 1b is similar to that of the operation of the circuit of FIG. 1a because electrically they are substantially equivalent, due to the tight coupling between windings W1 and W2 of transformer T1 in FIG. 1b. A winding W6 of flyback transformer T1 develops the retrace pulse voltage that is applied to regulator control circuit 26 along signal line s.
FIGS. 2a and 2b illustrate a detailed embodiment of a regulated television receiver deflection circuit embodying the invention. A 220 VAC, 50 Hz, power line or mains supply voltage is applied across terminals 21 and 22, full-wave rectified by rectifier 24, and filtered by a capacitor C1, to develop an unregulated direct input voltage Vin, of illustratively 290 volts, at a terminal 28. A television receiver on/off switch 23 is coupled between terminal 21 and an input terminal of bridge rectifier 24. The current return terminal of the bridge rectifier is coupled to an earth ground 25, not conductively isolated from the mains supply terminals 21 and 22. A current limiting resistor R1 is connected between the output terminal of bridge rectifier 24 and input terminal 28.
Unregulated input voltage Vin is applied to a blocking oscillator-regulator 30 that comprises the switching arrangement of controllable switches S1 and S2 coupled to a resonant circuit 40 in a push-pull relationship. Resonant circuit 40 is formed by the main winding WA of an inductor L1 and a capacitor C5. Switch S1 comprises a transistor Q1 and a damper diode D1 coupled between the collector and emitter electrodes of the transistor. Switch S2 comprises a transistor Q2 and a damper diode D2 coupled between the collector and emitter electrodes of transistor Q2. The main current paths of switches S1 and S2 are therefore bidirectionally conductive and coupled in series across the source of input voltage between terminals 28 and 25. The main current paths of switches S1 and S2 are also coupled to resonant circuit 40 at a common output junction terminal 31 of the switches S1 and S2 and the main winding WA of inductor L1.
A horizontal oscillator 34 applies a rectangular wave switching voltage, not illustrated in FIG. 2b, to the base of a driver transistor Q11 through a resistor R34 of a voltage divider comprising resistor R34 and a resistor R33. A horizontal rate switching signal is developed by driver transistor Q11 and coupled
Prior to the middle of the trace interval within a horizontal deflection cycle, driver transistor Q11 is turned off, resulting in a forward biasing voltage being applied to horizontal output transistor Q10. Immediately prior to the end of the horizontal trace interval, driver transistor Q11 is turned on, resulting in a reverse biasing voltage being applied to horizontal output transistor Q10. Shortly thereafter, collector current in output transistor Q10 ceases, thereby initiating the horizontal retrace interval. A retrace pulse voltage V r is developed across retrace capacitor C13 during the retrace interval.
The retrace pulse voltage V r of FIG. 2b is applied to a winding W2 of a flyback transformer T1 to develop retrace pulse voltages across windings W3-W5 of flyback transformer T1. A DC blocking capacitor C12 is coupled between flyback transformer winding W2 and isolated chassis ground 29.
To synchronize operation of horizontal deflection generator 60 with the picture content of the composite video signals of the television receiver, a retrace pulse 37 developed by flyback transformer winding W3 is applied to horizontal oscillator 34 along a conductor line 38, and a horizontal sync pulse, not illustrated, is applied to the oscillator at a terminal 36. A 12 volt supply voltage for horizontal oscillator 34 is provided by a regulator 33 from the voltage developed on the +25 volt supply rail.
The source of voltage for the +25 volt supply rail is obtained from the trace portion of the voltage developed across flyback transformer winding W4, as rectified by a diode D17 and filtered by a capacitor C16. A resistor R36 provides current limiting. Supply voltages for other television receiver circuits 32 such as the vertical deflection, the video, the sound, and the ultor high voltage, are derived from the voltages developed across various other flyback transformer windings, collectively illustrated in FIG. 1b as the winding W5.
To replenish losses sustained in horizontal deflection generator 60 and in the various television receiver load circuits 32, a winding W1 of flyback transformer T1 is coupled to the blocking oscillator resonant circuit 40 and transfers energy during the horizontal retrace interval of each deflection cycle from resonant circuit 40 to the retrace resonant circuit 50 and to the television receiver load circuits 32 including the ultor high voltage load circuit.
Assume, now, that blocking oscillator 30 is in the deflection synchronized mode of operation. As illustrated in FIG. 6, previously referred to with respect to operation of the simplified circuits of FIGS. 1a and 1b, during the trace interval of a horizontal deflection cycle, at a controllable instant t 2 , S1 becomes conductive and S2 becomes nonconductive, connecting the source of unregulated voltage Vin to resonant circuit 40. The current i L flowing in the winding WA of inductor L1 begins to ramp upward. Between times t 2 -t 3 when the inductor current i L is negative, energy is being returned to the source 70 of the input voltage Vin. After time t 3 , the zero-crossover instant of the inductor current i L , energy is transferred from input voltage source 70 to resonant circuit 40, principally to the magnetic field of inductor L1. At time t 0 , the beginning of the horizontal retrace interval, t 0 -t 1 , the energy stored in the inductance of resonant circuit 40 is maximum.
The rising retrace voltage V r makes controllable switch S1 nonconductive to decouple the source of input voltage from resonant circuit 40. Shortly thereafter, controllable switch S2 becomes conductive, coupling inductor L1 and capacitor C5 in series across flyback transformer winding W1. As a result, the retrace pulse voltage V r is applied by way of flyback transformer windings W2 and W1 to resonant circuit 40. Energy is then transferred from resonant circuit 40 to retrace resonant circuit 50.
Between times t 0 -t 1 , the inductor current i L ramps downwardly, at a relatively rapid rate, until substantially all the energy of inductor L1 is transferred to retrace capacitor C13 at the zero-crossover instant of the current i L at some instant between times t 0 -t 1 . Between the zero-crossover instant and time t 1 , the end of the horizontal retrace interval, a small portion of energy is returned to inductor L1 as indicated by the peak inductor current I p2 at time t 1 . This returning energy is required to keep the blocking oscillator 30 in operation. The energy transferred during each horizontal deflection cycle is substantially the difference between the energies stored in inductor L1 at times t 0 and t 1 .
Between times t 1 and t 2 , the current i L circulates through switch S2, inductor L1 and capacitor C5. During this interval, energy stored in capacitor C5 discharges into inductor L1. At time t 2 , switch S2 becomes nonconductive and switch S1 becomes conductive. The stored energy in inductor L1 immediately after time t 2 begins to transfer back into the filter capacitor C1 of the unregulated source 70 of input voltage Vin until the zero-crossover instant t 3 of the inductor current i L . From time t 3 until the beginning of the next retrace interval, energy is again stored in inductor L1 for subsequent transferral to the retrace resonant circuit 50. Retrace time modulation caused by variable loading is insignificant because blocking oscillator 30 appears as a current source to retrace resonant circuit 50 during the retrace interval.
To regulate a deflection circuit energy level, represented by the retrace pulse voltage V r , a low voltage tap point on flyback transformer winding W1 is connected to regulator control circuit 26 to apply thereto a sample V s of the retrace pulse voltage V r . The regulator control circuit 26 responds to variations in the voltage V s by pulse-width modulating the rectangular wave control voltage waveform 27 that is applied to blocking oscillator-regulator 30.
In FIG. 2a the control windings WB and WC of inductor L1 provide a positive feedback current for the switching transistors Q1 and Q2. The base currents are capacitively coupled via capacitors C2 and C3 so that the initial start-up base currents through resistors R2 and R8 do not become short-circuited by the control windings WB and WC. Capacitors C2 and C3 also provide negative cutoff voltages that are used to initiate the reverse biasing of transistors Q1 and Q2. Diodes D3 and D4 provide discharge paths for capacitors C2 and C3.
Transistors Q3 and Q4 control the flow of base current in switching transistors Q1 and Q2. The conduction of control transistors Q3 and Q4 relative to each other is such as to prevent conduction of a switching transistor, Q1 or Q2, before the other switching transistor stage stops conducting. As the voltage across switching transistor Q1 or Q2 increases, control transistor Q3 or Q4 saturates via base current through resistor R3 or R9 of voltage divider resistors R3-R9, thereby driving the respective switching transistor into cutoff.
Just prior to time t a of FIG. 7, a time corresponding to time t 0 , the beginning of the horizontal retrace interval of FIG. 6, switching transistor Q1 is in saturated conduction. Consequently, control transistor Q3 is in cutoff because essentially no voltage is being developed across resistor R5. Control transistor Q4, however, is in saturated conduction because of the base current being supplied to it through resistor R9, thereby maintaining switching transistor Q2 in cutoff. The voltage V S2 across switch S2 and across a parallel capacitor C4 equals the input voltage Vin in magnitude.
Beginning at time t a of FIG. 7, the r
From time t a to time t b of FIG. 7, the current i L flowing in the main winding WA of inductor L1, previously flowing in transistor Q1, now flows as a current i C4 in storage capacitor C4, thereby discharging the capacitor, as illustrated in FIGS. 7c and 7d. At the time t b the voltage across capacitor C4 has reached zero and is clamped to ground by diode D2 of switch S2. The current i L now flows through diode D2.
The waveform of FIG. 7b illustrates the slow fall time of the switching voltage V S2 caused by the discharge of C4, and the waveforms of FIGS. 7c and 7d illustrate that the entire current i L flows in capacitor C4 during the switching interval t a -t b of S1 and S2. The action of capacitor C4 prevents the switching voltage V S2 from changing too fast under the inductive current load i L . This action protects switches S1 and S2 from being destroyed by secondary breakdown and also significantly lowers the power dissipation in the switching devices S1 and S2.
The slow rise and fall time of V S2 indicates that during the switching intervals t a -t b and t e -t f both switching transistors Q1 and Q2 are held in cutoff by transistors Q3 and Q4 which in turn are controlled by the currents through R3 and R9. This arrangement prevents the undesirable simultaneous conduction of transistors Q1 and Q2, which would otherwise have occurred because of the longer turnoff than turn-on time characteristics exhibited by switching transistors.
At time t c of FIG. 7c, the inductor current i L becomes negative. After time t c until time t e , the negative inductor current i L flows as a positive collector current in the forward biased switching transistor Q2. As illustrated in FIG. 8, between times t a -t e , the voltage across control winding WC is positive, providing the needed forward biasing for switching transistor Q2.
From time t f to the beginning of the next horizontal retrace interval t a ', switch S1 is conductive and connects input terminal 28 to inductor L1 of resonant circuit 40, to allow a flow of input current i 0 from terminal 28 to switch S1, as illustrated in FIG. 7e.
From time t f to time t g , the zero-crossover instant of both the input current i 0 and the inductor current i L , diode D1 conducts a return current back to the input voltage terminal 28. From time t g to time t a , switching transistor Q1 conducts a forward current from input voltage terminal 28 to resonant circuit 40. Switching transistor Q1 is forward biased for conduction between times t e -t a by the positive portion of the voltage V WB being developed across control winding WB of inductor L1, as illustrated in FIG. 8. At time t a ', the operating sequence of blocking-oscillator regulator 30 repeats.
An embodiment of regulator con
The error voltage V E is applied to the base of transistor Q6 of a differential amplifier comprising transistor Q6 and a transistor Q7. The base of transistor Q7 is connected to a horizontal ramp generating capacitor C10. Capacitor C10 charges through the resistors R23 and R16 during each horizontal trace period. The horizontal retrace pulse voltage V s is applied to the base of a synchronizing transistor Q8 which keeps capacitor C8 discharged during the retrace interval.
The pulse-width modulated control voltage 27 is developed at the collector of differential amplifier transistor Q6 and controls, by means of transistor Q4 of FIG. 2a, the conduction of switching transistor Q2 of blocking oscillator-regulator 30.
A shift of the error voltage V E results in a change of the conduction time of differential amplifier transistor Q6 and consequently a change of the duty cycle of switching transistor Q2 and blocking oscillator 30. An increase in the amplitude of retrace pulse voltage V s , as illustrated by the greater amplitude dashed-line waveform of FIG. 4a, due, for example, to decreased loading by load circuits 32 of FIG. 2b, or due to an increase in the mains developed input voltage Vin, produces a decreased error voltage V E as illustrated by the dashed-line waveform of FIG. 4b. The horizontal ramp voltage V C10 produced by capacitor C10 intersects the error voltage V E earlier, turning on transistor Q6 earlier, as illustrated by the dashed-line waveform of FIG. 4c. The earlier turn-on of transistor Q6 produces an earlier turnoff of switching transistor Q2 and in turn a higher average voltage across capacitor C5 and a higher amount of return current through diode D1. Controllable switch S1 therefore becomes conductive earlier within the trace interval, but because of the higher average voltage across capacitor C5, the current i L increases at a slower rate at the decreased loading level or at the increased input voltage Vin.
The control circuit 26 generates a control waveform 27 which has a negative-going edge at the beginning of retrace when transistor Q8 begins to discharge the ramp capacitor C10 and a positive-going edge just after the end of retrace at very low loading levels by circuits 32. As the loading increases, the positive-going edge moves toward the center of trace where maximum power transfer is reached between primary and secondaries of transformer T1. This point is reached when the conduction time of switches S1 and S2 are substantially equal.
Should switch S2 conduct longer than switch S1, operation of blocking oscillator 30 becomes instable. Therefore, regulator circuit 26 provides for range limiting when load circuits 32 draw excessive current. The error voltage V E cannot increase more than that determined by the 15 volt supply rail voltage and by the voltage divider action of resistors R20 and R26. The error voltage V E therefore intersects the ramp voltage just before the center of trace. Because of the limited control range, any further, excessive loading will decrease the +45V supply rail in magnitude. This decrease in magnitude is coupled to the base of a limiter transistor Q9 by way of resistors R14 and R19. Transistor Q9 is driven into saturated conduction providing additional charging current for ramp capacitor C10. As illustrated by the dotted-dashed-line waveform of FIG. 4b, the ramp voltage V C10 now rises much faster than during normal regulator control circuit operation, resulting in a much earlier turn-on of differential amplifier transistor Q6, as illustrated by the dotted-dashed waveform of FIG. 4c. The substantially shortened conduction time of transistor Q6 produces a similarly shortened conduction time of switching transistor Q2 and a consequent substantial reduction in the net power transfer from the unregulated input voltage source to the retrace resonant circuit 50.
As previously menti
Between times T 1 -T 3 , the control voltage V WB is negative and the control voltage V WC is positive, producing a cutoff condition in switching transistor Q2. Between times T 1 -T 2 , the inductor current i L first flows in capacitor C4 and then in diode C2, and between times T 2 -T 3 , the inductor current i L flows in switching transistor Q2.
Between times T 3 -T 1 ', control voltage V WB is positive and control voltage V WC is negative, producing a forward biasing condition for switching transistor Q1 and a cutoff condition for switching transistor Q2. Between times T 3 -T 4 , the inductor current i L first flows in capacitor C4 and then in diode D1Wl; and between times T 4 -T 1 ', the current flows in switching transistor Q1. The free-running operating sequence repeats beginning at time T 1 '.
In synchronized operation, switch S1 is turned off only upon the occurrence of the retrace pulse voltage, and switch S2 is turned off only upon the occurrence of the positive-going edge of control voltage 27. Therefore, the free-running conduction times of switches S1 and S2 must each be equal to or longer than the horizontal trace interval, to prevent erroneous switching during synchronized operation.
As the start-up interval elapses, the ringing voltage in resonant retrace circuit 50 increases in magnitude. The ringing voltage is transformer coupled to regulator control circuit 26 by way of the tap terminal on flyback transformer winding W1. This voltage is rectified by diode D8 in FIG. 3. The ringing voltage is also coupled to the +25 volt supply rail by way of flyback transformer winding W4 and rectifier diode D17. When the +45 volt and +25 volt supply rail voltages increase to about one third of their normal, steady-state operating values, horizontal oscillator 34 and regulator control circuit 26 begin to operate, producing horizontal rate switching signals for horizontal output transistor Q10 of deflection generator 60 and control pulses to switching transistor Q2 of blocking oscillator 30.
FIGS. 9-12 illustrate selected voltage and current waveforms for the regulated deflection circuit of FIGS. 2a and 2b at selected sequential instants during the start-up interval, from the instant at which the input voltage Vin has attained 50% of its nominal steady-state value in FIG. 9 to the instant when the input voltage Vin has achieved 100% of its steady-state value in FIG. 12.
When the voltage Vin is less than 50% of its steady-state value, the free-running mode of operation of blocking oscillator 30 is not being influenced by the ringing of retrace resonant circuit 50. At 50% of nominal input voltage Vin, the retrace circuit ringing voltage enables the turnoff time of regulator switching transistor Q1 to be synchronized to the second ringing voltage pulse, as illustrated in FIG. 9c, resulting in blocking oscillator operation at a frequency higher than the free-running or short-circuit frequency.
At about 55% of nominal input voltage Vin, blocking oscillator 30 is fully synchronized with horizontal deflection as illustrated by FIGS. 10a and 10c. Because of the still low input voltage Vin, adequate power cannot yet be transferred from resonant circuit 40 to the retrace resonant circuit 50 and the load circuits 32. Because of the low amplitude retrace pulse voltage V r being developed, the regulator control circuit 26 operates in the partial overload mode of operation with power limiting control transistor Q9 of FIG. 3 in saturation conduction. Conduction of transistor Q9 produces a sharply upward sloping synchronizing ramp voltage V C10 , as illustrated in FIG. 10d, and produces an early turnoff of switching transistor Q2.
At 60% of nominal input voltage Vin, the power limiting control transistor Q9 is disabled, as illustrated by the shallower slope ramp voltage V C10 of FIG. 11d. The retrace pulse voltage V r has increased to near nominal value, as illustrated in FIG. 11a. The transferred power is near maximum as indicated by the near equal conduction time of switching transistors Q1 and Q2, as indicated by the near 50% duty cycle of the voltage V S2 of FIG. 11c.
Nominal or 100% input voltage Vin is illustrated in FIG. 12 for a mains power input of 60 watts, illustratively. In contrast to the situation in FIGS. 9 and 11, the error voltage V E of FIG. 12d is lower at 100% input voltage Vin, resulting in longer conduction of switching transistor Q1 and shorter conduction of switching transistor Q2.
As previously mentioned, during start-up, a ringing voltage is developed by retrace resonant circuit 50. During this interval, the horizontal output transistor Q10 may be damaged if driven into saturated conduction at a time when the ringing voltage appears at the transistor collector electrode. To prevent such a situation from occurring, flyback transformer winding W3 is connected via resistor R35 and diode D16 to the base of horizontal driver transistor Q11. Any positive voltage developed across winding W3, such as during start-up ringing, forward biases horizontal driver transistor Q11 into saturated conduction, keeping horizontal output transistor Q10 in a cutoff state. Winding W3, resistor R35 and diode D16 also protect horizontal output transistor Q10 during fault conditions, such as during malfunction of horizontal oscillator 34 and during picture tube arcing.
Operation of the regulator control circuit 26 illustrated in FIG. 13 is as follows. Horizontal retrace pulses, illustrated in FIG. 14a, are integrated via diode D3, resistors R2-R6, and capacitor C2. Across capacitor C2 appears an error ramp voltage 81. Error ramp voltage 81 is compared with a reference voltage level V REF in an error voltage amplifier comparator U1A. The reference voltage level V REF is obtained through integration, by way of a resistor R8 and a capacitor C4, of a reference ramp voltage 83 which is produced by a resistor R7, a capacitor C3 and a ramp switch comparator U1B to discharge capacitor C3.
FIG. 14b illustrates the signal waveforms at pins 6 and 7 of error voltage amplifier U1A for high and low power loading of flyback transformer T1 of FIGS. 2a and 2b. FIG. 14c illustrates the output pulse at pin 1 of amplifier U1A at both high and low load.
In order to avoid unstable operation of blocking oscillator 30, regulator control circuit 26 of FIG. 13 provides control range limiting such that the occurrence of the positive-going edge of control pulse 27' cannot be delayed beyond the center of the trace interval of the horizontal deflection cycle. Comparator U1D of FIG. 13 provides this limiting action. Comparator U1D compares the error ramp voltage 81 to the amplified error voltage V E . During normal operation the range of amplified error voltages V E is below the range of error ramp voltages 81, as illustrated in FIG. 14b, resulting in comparator U1D being in a cutoff condition throughout this range.
During an overload condition wherein the amplitude of the retrace pulse voltages V r and V s are substantially reduced, but not eliminated, the error ramp voltage 81 still intersects the reference voltage level, V REF , as illustrated in FIG. 15b. However, had no provision been made for including the range limiter comparator into the circuit of FIG. 13, the output pulse produced at pin 1 of error voltage amplifier U1A would have been the dashed-line waveform of FIG. 15c. This pulse would have been in the high state for a relatively long duration within a deflection cycle and would have produced a relatively large magnitude error voltage V E1 .
The comparison, illustrated in FIG. 15d, by output pulse generator U1C of the voltage V E1 with reference ramp 83 would have produced the dashed-line control pulse 27' of FIG. 15e. The positive-going edge of dashed-line pulse 27' would have been delayed beyond the center of horizontal trace, resulting in the transfer of excessive power to retrace resonant circuit 50 and load circuits 32 of FIG. 2b during the overload condition.
To prevent the occurrence of such a situation, the error voltage V E is applied to the negative input terminal of range limiter U1D, while the error ramp voltage 81 is applied to the positive input terminal. During an overload condition, the error voltage is of sufficient magnitude V E1 ' of FIG. 15b to intersect the error ramp voltage 81, producing a low output level at pin 14 of U1D whenever the error voltage V E1 ' is above the error ramp voltage 81.
The outputs of U1A and U1D are logically combined to produce the solid-line pulse voltage of FIG. 15c. This voltage has an average value V 1 ' much less than the average value V 1 of the dashed-line pulse of FIG. 14c, producing the lower error voltage magnitude V E1 ', previously mentioned.
When the lower error voltage V E1 ' is compared to the reference ramp 83, illustrated in FIG. 15d, the solid-line control pulse waveform 27' of FIG. 15e is produced, having a positive-going edge that occurs just before the center of trace, as is required to provide a limitation of control range during an overload condition. A still greater increase in loading produces a longer duration of the low state of the voltage waveform pulse at pin 1 of U1A. As a result, the positive-going edge of waveform 27' is shifted farther back toward the beginning of the trace interval.
A slight hysteresis to the operation of range limiter U1D is provided by connecting pin 7 of error voltage amplifier U1A to pin 8 of range limiter U1D through a resistor R9. This hysteresis stabilizes operation of range limiter U1D.
If the retrace pulse voltages V r and V s collapse, as may occur during a short-circuit, or during a very heavy overload condition, or during turnoff of the television receiver when on/off switch 23 of FIG. 2a is opened, a limiter diode D4 of FIG. 13 conducts to rapidly lower the level of the integrated reference voltage V REF . Lowering the voltage level V REF protects the television receiver from voltage overshoot stresses.
The gain of the error voltage amplifier U1A depends upon the amplitude of error ramp voltage 81--the smaller the amplitude the higher the gain. Variable resistor R5 shifts the DC level of error ramp 81 and therefore provides adjustment control of the amplitude of the retrace pulse voltage V r .
A description of selected magnetic components that may be used in the circuit of FIGS. 2a and 2b is as follows:
L1: Core, Philips U-U 25/20/13, Material 3 C 8 or similar;
Air gap 1 mm each limb;
WA 168 turns, 3 mH;
WB 7 turns;
WC 10 turns;
All windings, 0.6 mm diameter copper wire.
T1: Core, Siemens U 47, Material N 27 or similar;
Air gap 0.1 mm each limb,
W1 120 turns, tap at 6 turns;
W2 92 turns;
W3 6 turns;
W4 21 turns;
All windings, 0.5 mm diameter copper wire.
Isolation between primary and secondaries: 4000 volts.
FRAME DEFL. + SYNCH + DRIVE + E/W (VERTIKAL STEUER - MODUL Best.Nr. 7807021200)
FRAME DEFL. WITH: TDA2655 (PHILIPS)
E/W CORRECTION WITH: TDA4610 (Siemens)
SYNCHRONIZATION WITH: TDA2593 (PHILIPS)
TDA2593 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET
The TDA2593 isa circuit intended for the horizontal
deflectionof color TVsets, suppliedwith transistors
.LINE OSCILLATOR(two levels switching) .PHASE COMPARISON BETWEEN SYNCHRO-
PULSE AND OSCILLATOR VOLTAGE
Ø 1, ENABLED BY AN INTERNAL PULSE,
(better parasitic immunity) .PHASE COMPARISON BETWEEN THE FLYBACK
PULSES AND THE OSCILLATORVOLTAGE
Ø2 .COINCIDENCE DETECTOR PROVIDING A
LARGE HOLD-IN-RANGE .FILTER CHARACTERISTICS AND GATE
SWITCHING FOR VIDEO RECORDER APPLICATION
.NOISE GATED SYNCHRO SEPARATOR .FRAME PULSE SEPARATOR .BLANKING AND SAND CASTLE OUTPUT
PULSES .HORIZONTAL POWER STAGE PHASE LAGGING
CIRCUIT .SWITCHING OF CONTROL OUTPUT PULSE
WIDTH .SEPARATED SUPPLY VOLTAGE OUTPUT
STAGE ALLOWING DIRECT DRIVE OF
SCR’S CIRCUIT .SECURITY CIRCUIT MAKES THE OUTPUT
PULSE SUPPRESSED WHEN LOW SUPPLY
PHILIPS TDA2655 VERTICAL DEFLECTION CIRCUIT
The TDA2655 is a monolithic integrated circuit for vertical deflection in colour television receivers
with 110° picture tubes.
- Synchronization circuit
- Vertical oscillator; 50/60 Hz switch
- Sawtooth generator with buffer stage
- Preamplifier with fedout inputs
- Output stage with termal and shortcircuit protection
- Flyback generator
- Blanking pulse generator with guard circuit
- Voltage stabilizer
- Frequency detector with memory and storage.
VIDEO UNIT (VIDEO- MODUL Best.Nr. 780700100)
TDA3501 (MATRIX) (PHILIPS)
TDA3510 (LUMINANCE + CHROMINANCE) (PHILIPS)
PHILIPS TDA3501 VIDEO CONTROL COMBINATION:
The TDA3501 is a monolithic integrated circuit performing the control functions in a PAL/SECAM
decoder which additionally comprises the integrated circuits TDA3510 (PAL decoder) and/or
TDA3520 (SECAM decoder).
The required input signals are: luminance and colour difference —(R-Y) and —(B-Y),
while linear RGB signals can be inserted from an external source.
RGB signals are provided at the output to drive the video output stages.
The TDA3501 has the following features:
- capacitive coupling of the input signals
- linear saturation control
- (G-Y) and RGB matrix insertion possibility of linear RGB signals, e.g. video text, video games, picture-in-picture, camera or slidescanner
- equal black level for inserted and matrixed signals by clamping
- 3 identical channels for the RGB signals
- linear contrast and brightness control, operating on both the inserted and matrixed RGB signals
- horizontal and vertical blanking (black and ultra-black respectively) and black-level clamping
obtained via a 3-level sandcastle pulse
- differential amplifiers with feedback-inputs for stabilization of the RGB output stages
- 2 d.c. gain controls for the green and blue output signals (white point adjustment)
- beam current limiting possibility
QUICK REFERENCE DATA
Supply voltage V524 typ. 12 V
Supply current I5 typ. 100 mA
Luminance input signal (peak-to-peak value) V15_24(p_p) typ. 0,45 V
Luminance input resistance R15_24 typ. 12 kﬂ
Colour difference input signals (peak-to-peak values)
—(B-Y) V1g_24(p_p) typ. 1,33 V
R-Y) V17-24cp-pi tvr>- 1.05 V
Inserted RGB signals (peak-to-peak values) V12,13'-|4_24(p_p) typ. 1 V
Three level sandcastle pulse detector V1Q_24 typ. 2,5/4,5/8,0 V
Control voltage ranges
brightness V2024 I to 3 V
contrast V19_24 2 to 4 V
saturation V16_24 2,1 to 4 V
IF UNIT (BILD-ZF- MODUL Best.Nr. 7807040100)
PHILIPS TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
.SUPPLY VOLTAGE : 12V TYP
.SUPPLY CURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
TUNER UNIT (TUNER- MODUL Best.Nr. 7751100000)
SOUND+IF UNIT (TON-ZF- MODUL 10W MUSIK Best.Nr. 7825001000)
ST-BY SUPPLY UNIT (VERSORGUNGS- MODUL Best.Nr. 7807021400
MICRO-COMPUTER-MOD.1A 78080 011 00
SABA ULTRACOLOR T56Q75 QUARTZ COMPUTER CHASSIS Q110 Frequency synthesizer tuning system for television receivers:
" A method for tuning a television receiver having automatic frequency control to the carrier frequency of a selected broadcast channel with an associated channel number including generating a variable frequency signal by means of a local oscillator, generating a reference frequency signal by means of a reference oscillator, and generating a local oscillator correction signal for matching an intermediate frequency signal derived from said local oscillator signal and the carrier frequency signal with a predetermined nominal intermediate frequency signal, said method being characterized by the use of a microcomputer and comprising:
generating binary signals representing first and second digital tune words, said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading said first and second digital tune words from said first memory and generating a divided-down local oscillator frequency by the use of said first digital tune word and a divided-down reference oscillator frequency by the use of said second digital tune word;
comparing said divided-down local oscillator and reference frequencies and generating a control signal representative of the difference in frequency of said divided-down local oscillator and reference frequencies;
coupling said control signal to said local oscillator for causing it to be locked to the frequency of said received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing said intermediate frequency signal with said predetermined nominal intermediate frequency signal and providing a tuning voltage to said microcomputer, said tuning voltage being indicative of the magnitude and direction of a tuning error between said intermediate frequency signal and said predetermined nominal intermediate frequency signal;
incrementally adjusting the reference oscillator frequency by means of a tuning signal provided to said reference oscillator by said microcomputer in response to said tuning voltage;
detecting when the incrementally changing, divided-down reference oscillator frequency causes the intermediate frequency signal to pass said predetermined nominal intermediate frequency signal; and
incrementally stepping the divided-down reference oscillator frequency back a predetermined number of steps following the passage of said predetermined nominal intermediate frequency signal by said intermediate frequency signal in tuning said television receiver to the selected channel.
A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A programmable frequency divider counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator in the tuner also is applied. The phase comparator output provides a tuning voltage for controlling the tuning of the local oscillator. A microprocessor is used to control the count of the programmable frequency divider and initially to set a count corresponding to the selected channel in a counter connected between the output of the local oscillator and the phase comparator. The tuning consists of three discrete time periods. First, a settling time to allow channel change transients to settle; second, a short period of forced search at a relatively rapid rate to insure proper tuning; and third, a slower rate of step-by-step correction to accomodate for station drift and the like during reception. This third time period is initiated either by the passage of a fixed length of time following the start of the forced search period or by sensing a preestablished number of changes of state in the output of the frequency discriminator during the forced/search period.
1. A tuning system for the tuner of a television receiver capable of receiving a composite television signal and including frequency discriminator (AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a local oscillator in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider means having first and second inputs coupled respectively to the output of said reference oscillator and said local oscillator for producing signals on first and second outputs having frequencies which are a programmable fraction of the frequency of the signals applied to the inputs thereto;
phase comparator means having one input coupled with the first output of said programmable frequency divider means and having another input coupled with the second output of said programmable frequency divider means for developing a control signal and applying such control signal to said local oscillator for controlling the output frequency thereof;
counter circuit means coupled with said programmable frequency divider means for initially setting said divider means to a predetermined division ratio and operating to change the programmable fraction of division thereof in accordance with changes in the count in said counter circuit means;
control circuit means coupled with the output of said frequency discriminator means and further coupled with said counter circuit means for causing said counter circuit means to count at a first rate in a predetermined direction determined by the state of the output signal from said discriminator means in the absence of a predetermined signal output from said frequency discriminator means until a predetermined maximum count is attained, thereupon resetting said counter circuit means to a count which is a predetermined amount less than said maximum predetermined count and continuing to count at said first rate in the same predetermined direction from said new count to continuously change the programmable fraction of said frequency divider means in accordance with the state of operation of said counter circuit means, said control means operating in response to said predetermined signal output from the frequency discriminator means for terminating operation of said counter circuit means; and
further means for terminating operation of said counter circuit means at said first rate and causing operation thereof at a second slower rate.
2. The combination according to claim 1 wherein said further means includes timing means initiated into operation simultaneously with the setting of said divider means to a predetermined division ratio, and after a predetermined time interval said timing means producing an output signal applied to said counter circuit means to cause operation thereof to take place at said second slower rate. 3. The combination according to claim 1 wherein said counter circuit means includes a reversible digital counter coupled with said programmable frequency divider, means and said control circuit means causes said counter circuit means to count in said predetermined direction when the output of said frequency discriminator is of a first state and to count in the opposite direction when the output of said frequency discriminator is of second state; and said further means comprises means coupled with the output of said frequency discriminator and with said counter circuit means to take place at said second slower rate in response to a predetermined number of changes of state of frequency discriminator. 4. The combination according to claim 3 further including means responsive to the selection of a new channel in said television receiver for resetting said further means to an initial condition of operation. 5. The combination according to claim 4 wherein said further means comprises a search termination counter means operative to provide an output signal applied to said counter circuit means in response to a count thereby of a predetermined number of changes of state of said frequency discriminator to cause said counter circuit means to be operated at said second slower rate.
Both of the above mentioned patents are directed to frequency synthesizer tuning systems for use with television receivers to enable operation of the receivers with minimal viewer fine tuning adjustments. By the utilization of the frequency synthesizer tuning systems of these patents, the fine tuning adjustment which is necessary with conventional types of television receiver tuning systems has been substantially eliminated. The system employed in the '953 patent permits utilization of a frequency synthesizer tuning system which correctly tunes to a desired television station or channel even if the transmitted signals from that station are not precisely maintained at the proper frequencies. The '535 patent is directed to a signal seek tuning system adaptation of the frequency synthesizer tuning system of the '953 patent which still permits implementation of all of the desired wide-band pull in range of the frequency synthesizer system of the '953 patent.
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.
It is a further object of this invention to tune the local RF oscillator of a television receiver to the correct frequency for a selected channel with a frequency synthesizer tuning system, and automatically to change the reference frequency of the synthesizer system, or adjust the count of a programmable divider that produces a signal that divides the frequency of the local oscillator of the tuner, if the AFT signal produced by the AFT frequency discriminator of the receiver is outside a predetermined range corresponding to correct tuning.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.
In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the receiver picture carrier discriminator in the absence of a predetermined signal output derived from the discriminator. A control means causes the counter circuit to count in this direction until it is determined that a station is tuned or a predetermined maximum count is attained if no station is correctly tuned, thereupon resetting the counter circuit to a count which is a predetermined amount less than the maximum predetermined count. Counting is continued in the same predetermined direction from the new lesser count to continuously change the programmable fraction of the frequency divider in accordance with the state of operation of the counter. The high rate operation of the counter is terminated by the control means in response to a predetermined signal from the output of the discriminator, indicating that a station is correctly tuned, or after a fixed time-out interval; so that the system automatically adjusts for frequency offsets of the received signal which otherwise would cause the station to be mistuned if a conventional frequency synthesizer tuning system were used. After termination of the high rate operation of the counter, it is switched to a lower rate operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Most of the circuitry of this receiver is conventional, and for that reason it has not been shown in FIG. 1. Added to the conventional television receiver circuitry of FIG. 1, however, is a frequency synthesizer tuning system, in accordance with a preferred embodiment of the invention, which is capable of automatically changing the reference frequency when a frequency offset exists in the received signal for a particular channel.
Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14. The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.
The receiver 14 also includes a conventional AFT or automatic fine tuning discriminator circuit and additionally may include a synch separator circuit for producing an output in response to the presence of vertical synchronizatin pulses, a picture carrier detection circuit, and an automatic gain control (AGC) amplifier. Outputs representative of these sensor components are shown as being coupled over a group of lead 20 to sensory circuitry 22, which in turn couples outputs representative of the operation of these various sensor circuits to a microprocessor unit 23 for controlling the operation of the microprocessor unit.
The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.
The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase comparator circuit 37 is supplied from the selected one of the VHF or UHF oscillators in the tuner stages 11 through the programmable frequency divider 31. The phase comparator circuit 37 operates in a conventional manner to supply a DC tuning control signal through a phase locked loop filter circuit 39 and over a lead 40 to the oscillators in the tuner system 11 to change and maintain their operating frequency.
With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of the interface between the keyboard 25, the microprocessor unit 23, and the circuitry used in the frequency synthesizer portions of the system. A commercially available microprocessor which has been used for the microprocessor 23, and which forms the basis for the diagramatic representation of the microprocessor in FIG. 2, is the Matsushita Electronics Corporation MN1402 four-bit single-chip microcomputer. This microcomputer has two, four-bit parallel input ports labeled "A" and "B". In addition, three output ports, a five-bit output port "C" and two four-bit output ports "D" and "E" are provided. The internal configuration of the microcomputer 23 includes an arithmetic logic unit (ALU), a read only memory (ROM) for storing instructions and constants, and a random access memory (RAM) used for data memory, arranged into four files, each file containing 16 four-bit words. These words are selected by X and Y registers and this memory is used, for example, for timers, counters, etc., and also is used to hold intermediate results. To facilitate an understanding of the operation of the system, a portion of this memory is shown in FIG. 2 as a clock 81 and a reversible counter 82 connected between the "B" input port and the "D" output port. The microcomputer 23 is programmed to permit it to operate in conjunction with the remainder of the circuits shown in FIG. 2. The programming techniques are standard, and the microcomputer 23 itself is a standard commercially available circuit component.
There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.
The division ratio of the selector counter 31 is established by appropriate output signals from the latch circuits 44, 45 and 46, as mentioned above. The initial operation for changing, or maintaining, the division ratio of the divider 31 is established by an entry of the two digits of the selected channel number in the keyboard 25. The microcomputer 23 operates as a time division multiplex system for continuously monitoring the input ports and the output ports to control the operation of the remainder of the system. The selection of the two digits of the desired channel number is affected by a time division multiplex iscanning of the outputs of the D output port of microcomputer 23 and providing that information at the A input port. From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.
Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the time division multiplex sequence of operation of the microcomputer 23 to the five latch circuits 44, 45, 46, 49 and 50, respectively. At any given time in the sequence, only one of these latch circuits is enabled for operation. A latch load signal is applied from the upper output (EO3) at each cycle of operation of the signals appearing on the E output port to set the latch circuit which is enabled by the output of the decoding circuit 52 with the data appearing on the other inputs to the latch circuit. This data simultaneously appears on the four outputs of the D output port of the microcomputer 23.
Thus, in rapid sequence, the latch circuits 44, 45 and 46 are set to store the division number corresponding to the selected channel entered onto the keyboard 25, and the latch circuits 49 and 50 are each operated to set the programmable divider reference counter 35 to a center or nominal count, which is always the same upon the selection of a new channel on the keyboard 25. Similarly, the two right-hand outputs of the C output port (CO6 and CO5) enter the two digits of the selected channel number in the drivers of the display circuit 29 at the proper time in the binary encoded sequence when these digits appear on the four-bit binary encoded representation of the D output port. This results in a visual display of the channel number selected.
In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the microcomputer 23 provides the intelligence, decision making, and control for the system operation. It is a complete self contained computer. The decisions or signal inputs upon which the microcomputer 23 bases its operation include, in addition to the inputs from the keyboard 25, inputs on sensory inputs into the B input port and into the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are used to provide an indication to the microcomputer 23 of the presence or absence of a received signal; and if the presence of such a signal is indicated, the inputs provide a further indication of the accuracy of the tuning of the receiver to that signal. If the system is being operated solely in a manual mode of operation (AFT switch 58 open), the microcomputer 23 disregards all of this sensory information and tunes to the frequency allocation of the channel selected in the manner described above. The system will stay tuned to this condition, operating as a conventional frequency synthesizer, whether or not a station is present in the received signal.
When the system is placed in its automatic mode of operation (similar to the mode of operation of the above mentioned '953 patent), the counter 82, integrally formed as part of the microcomputer 23, continuously adds or subtracts one number at a time from the nominal value or programmable division fraction entered into the programmable frequency divider 35 at the outset of each new channel number selection when frequency offset (mistuning) is present. The counter 82 is driven at a relatively high counting rate by clock pulses from the clock 81 during this initial or forced search mode of operation. Thus, automatic offset correction is provided for any channel which is off its assigned frequency. The offset correction automatically adjusts the frequency of the local oscillator by changing the division ratio of the signal from the reference oscillator 35 applied to the lower input of the phase comparator 37. By doing this, the output of the phase comparator 37 applied to the local oscillator 11 varies to cause the oscillator to be tuned in the proper direction to compensate for the transmitting station mistuning.
When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The system shown in the drawings has a capability of correcting for frequency offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2 MHz on channels 6 and 13. The remainder of the channels have a range between these two values.
If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.
The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially that the receiver is capable of making tuning adjustments over a range of fc plus Δf to fc minus Δf, as indicated in the top waveform of FIG. 5. Three specific examples of mistuning will then be considered. Initially, assume that the local oscillator is mistuned relative to the received signal to a frequency f1 as shown in the lower graph of FIG. 5. In this condition, the outout of the frequency discriminator 60 is positive since this signal frequency lies to the lefthand side of the center or properly tuned region of operation of the discriminator. Under this condition of the operation, the input signal applied to the sensor port B12 of the microcomputer 23 is such that the microcomputer counter 82 is caused to advance in a positive direction to change the programmable division ratio or count of the reference counter 35 in a manner to force the output of the phase comparator 37 to adjust the frequency of the local oscillator until the proper tuning indicated at point B in the lower graph of FIG. 5 is reached. The time interval for accomplishing this result is measured from the upper end of the arrow representative of the frequency f1 to the point B.
Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this signal is identified by the microcomputer 23 to cause the counter 82 in it to operate in the reverse direction. As this count is applied on a step-by-step basis through the latch circuits 49 and 50 to the reference counter 35, the division ratio or count of the reference counter (divider) 35 is changed. As a result, the reference oscillator signal applied to the phase comparator 37 causes the phase comparator 37 output to drive the local oscillator frequency in a direction opposite to that considered in the first example. This is shown by the vector interconnecting the top of the arrow representative of f2 to point A on the time/frequency graph of FIG. 5.
As discussed in the general discussion above, whenever the tuning frequency reaches the narrow window on either side of fc, the outputs of the comparators 62 and 63 provide the necessary indication on the sensory input port terminal B11 to cause termination of the operation of the counter 82 in the microcomputer 23. Then the reference counter 35 remains set to the count attained just prior to the appearance of this input signal on the input port B11 of the microcomputer 23.
A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in the first example considered for frequency f1; so that the counter 82 of the microprocessor 23 operates to change the count in the reference counter 35 in a manner to cause the local oscillator frequency to go higher toward a frequency f3 +Δf, as shown in FIG. 5.
A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
The counter 82 of the microcomputer 23 is operated by the clock 81 during the foregoing sequence of operation, immediately following the selection of a new channel by the operation of the keyboard 25, at a fast or high speed operation. Typically, the counter steps are 10 milliseconds per step; so that there are no initial visual effects which can be noticed by an observer of the television screen of the receiver being tuned. The maximum forced search period is approximately 900 milliseconds in duration. At the end of this time interval, a timer in the microcomputer 23 causes a signal to be applied through the outputs of the E output port to the decoder circuit 52 indicative of the completion of this time interval. The decoder 52 then applies a pulse on an output lead connected to the B13 input of the B input port of the microcomputer 23. This pulse is sensed by the microcomputer 23 and is applied to the clock 81 to change the clock rate to a much slower rate, approximately one-third (1/3) or one-fourth (1/4) the rate used previously during the forced search mode of operation. This then permits the system to accomodate station drifts which normally occur at a very slow rate during the transmission and reception of a television signal. As a consequence, it is possible to use more filtering in the filter 39 on the tuning line (FIG. 1) and employ a smaller frequency window for the channel verification sensed by the circuitry shown in FIG. 3. The result is a more precise tuning from the receiver than is otherwise possible if only a high speed operation of the clock 81 is utilized.
When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programmable frequency counter divider 35 is the same as described above. The additional sensory inputs simply are used in conjunction with the outputs of the comparators 62 and 63 to signal the microcomputer 23 to assure that tuning is to a picture channel rather than an adjacent sound channel. This is accomplished by utilizing the output of the synchronizing signal separator 65 which is applied to a comparator 67 to produce an output signal to the SNS1 sensory input of the microcomputer 23 only when vertical synchronizing signal components are present.
In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.
The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.
Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.
FIG. 4 shows the control sequence of the system which is stored in the ROM (Read Only Memory) of the microcomputer 23. The microcomputer 23 operates by always running through the flow sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new channel selection by two digit number entry. Loop L2 corresponds to channel number increment or decrement by an up or down key operation, respectively, or by seek operation. Loop L3 corresponds to fine tuning, either manual or automatic. To obtain exact timing for system control, the microcomputer 23 receives a standard timing pulse from the output of the reference counter 35 divided in a divide-by-five counter 80 and applied to the A13 input port of the microcomputer 23. The control functions which are programmed into the microcomputer 23, as indicated in the flow chart of FIG. 4, are outlined in the following paragraphs.
Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a given channel number, a corresponding binary code for the PLL selector counter 31 is derived as described previously. For UHF channels, the local oscillator frequency separation between two adjacent channels is 6 MHz and the code for PLL is generated by the microcomputer 23 through means of a simple calculation. This code then is transferred from the microcomputer 23 to the latches 44, 45 and 46 as described previously.
PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latches of the display driver circuit 29.
Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.
The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the invention, which is not limited to the specific embodiment selected for this purpose. For example, hard-wired logic could be used to achieve the various circuit operations which are accomplished by the microcomputer 23 in conjunction with the other portions of the system. The relative ease of programming and debugging the microcomputer 23, however, make it much simpler to implement the system operation with the microcomputer than with hard-wired logic. With respect to the sensor circuit inputs to the system, an added degree of operating assurance can be provided by the addition of a sound carrier sensor in addition to the picture carrier sensor shown in FIG. 3. If this feature is desired, the output of the comparator for the sound carrier is combined with the outputs of the comparators 70 and 74 at the input terminal B10 of the B input port of the microcomputer 23. Because of the manner of the circut operation which has been described previously, however, the addition of a sound carrier detector to the system is not considered necessary, even for a system operating in the signal seek mode of operation. This is in contrast to conventional television receivers having a signal seek operation, in which detection of the sound carrier generally is a necessity to insure that mistuning of the receiver to an adjacent sound carrier does not take place.