MIVAR 12BN3V CHASSIS TV3013 INTERNAL VIEW.

Power Supply: The examples chosen are taken from manufacturers' circuit diagrams and are usually simplified to emphasise the fundamental nature of the circuit. For each example the particular transistor properties that are exploited to achieve the desired performance are made clear. As a rough and ready classification the circuits are arranged in order of frequency: this part is devoted to circuits used at zero frequency, field frequency and audio frequencies. Series Regulator Circuit Portable television receivers are designed to operate from batteries (usually 12V car batteries) and from the a.c. mains. The receiver usually has an 11V supply line, and circuitry is required to ensure that the supply line is at this voltage whether the power source is a battery or the mains. The supply line also needs to have good regulation, i.e. a low output resistance, to ensure that the voltage remains constant in spite of variations in the mean current taken by some of the stages in the receiver. Fig. 1 shows a typical circuit of the power -supply arrangements. The mains transformer and bridge rectifier are designed to deliver about 16V. The battery can be assumed to give just over 12V. Both feed the regulator circuit Trl, Tr2, Tr3, which gives an 11V output and can be regarded as a three -stage direct -coupled amplifier. The first stage Tr 1 is required to give an output current proportional to the difference between two voltages, one being a constant voltage derived from the voltage reference diode D I (which is biased via R3 from the stabilised supply). The second voltage is obtained from a preset potential divider connected across the output of the unit, and is therefore a sample of the output voltage. In effect therefore Tr 1 compares the output voltage of the unit with a fixed voltage and gives an output current proportional to the difference between them. Clearly a field-effect transistor could do this, but the low input resistance of a bipolar transistor is no disadvantage and it can give a current output many times that of a field-effect transistor and is generally preferred therefore. The output current of the first stage is amplified by the two subsequent stages and then becomes the output current of the unit. Clearly therefore Tr2 and Tr3 should be current amplifiers and they normally take the form of emitter followers or common emitter stages (which have the same current gain). By adjusting the preset control we can alter the fraction of the output voltage' applied to the first stage and can thus set the output voltage of the unit at any desired value within a certain range. By making assumptions about the current gain of the transistors we can calculate the degree of regulation obtainable. For example, suppose the gain of Tr2 and Tr3 in cascade is 1,000, and that the current output demanded from the unit changes by 0.1A (for example due to the disconnection of part of the load). The corresponding change in Tr l's collector current is 0.1mA and, if the standing collector current of Tr 1 is 1mA, then its mutual conductance is approximately 4OmA/V and the base voltage must change by 2.5mV to bring about the required change in collector current. If the preset potential divider feeds one half of the output voltage to Tr l's base, then the change in output voltage must be 5mV. Thus an 0.1A change in output current brings about only 5mV change in output voltage: this represents an output resistance of only 0.0552.


TEA2037A HORIZONTAL & VERTICAL DEFLECTION CIRCUIT

The TEA2037A is a horizontal and vertical deflection
circuit for monitors and black and white TV
sets.
This device includes all functions required for deflection,
namely :
- Line and frame sync separation
- Line oscillator with phase comparator
- Driver stage for line deflection darlington transistor
- Frame oscillator
- Frame amplifier with flyback generator for direct
drive of the vertical deflection yoke.
The TEA2037A is particularly well-suited for lowcost
monitors since it is cased in a low-cost package
and requires a few number of external
components and hence optimized for small displays.
However, application areas are by no means limited.
Sophisticated applications requiring various
adjustmentpossibilities such as for display geometry
and centering settings (amplitude, linearity,...)
and operating at different line and frame frequencies
(line frequencies up to 64kHz), are readily
configured around TEA2037A.
In large screen applications, addition of a heatsink
mounted on TEA2037A will enable the vertical
deflection yoke current to be boosted to 2A peakto-
peak.
II - FUNCTIONAL DESCRIPTION OF TEA2037A
II.1 - General Description
The TEA2037A is a 16-pin DIP package. The 4
center pins (2 on each side) are connectedtogether
and used as heatsink.
From composite video or TTL-compatible sync.
signals, the device will extract and generate all
signals required for the line scanning darlington
transistor and direct drive of the frame yoke.
The following functional blocks are implemented
on-chip :
- Line and frame sync. separator
- Line oscillator
- Line phase comparator
- Line output stage
- Frame oscillator
- Frame amplifier
- Frame flyback generator
- Shunt regulator
The common device power supply is implemented
by the on-chip shunt regulator.
In order to optimize the drive to frame deflection
yoke and also enableappropriateuse of the flyback
generator, the frame amplifier is powered by an
independentsupply.
The ground is connected to the 4 center pins of the
device.

Sync. Pulse Separator
The TEA2037A extracts, first the line and frame
sync. pulses from the composite video signal and
then the largest pulses, i.e., the frame syncs.

- The sync. detection level is set at 1.6V.
- The value of R2 is typically 1MW (fixed for a good
internal bias).
- Resistor R1 limits the output current of Pin 15.
As illustrated in the Figure 4, it is recommended to
employ a low-pass filter which will suppress highfrequency
harmonics susceptible to produce jitters
on line sync signal in composite video TV applications.

In monitor application, the sync. signal is generally
separated from the video signal.
In this case, the sync. signal is applied to Pin 15
through a single limiting resistor. Similar to the
former case, the sync. is detected when the input
voltage falls below 1.6V level.

- Line Output Stage
The line output stage has been designed for direct
base drive of the horizontal scanning darlington
transistor.
The low level interval on Pin 14, i.e. the power line
transistor blockingperiod, is determined bythe time
when the voltage of the line oscillator capacitor
(Pin 9) is below 4.8V (internally set thresholdlevel).
In a typical application, this interval corresponds to
22ms at 64ms free-running period.

Phase Comparator (PLL)
II.5.1 - Functional Description
The duty of phasecomparator is to synchronize the
horizontal scanning with the line sync pulse and
ensure correct line flyback during the horizontal
blanking phase.

The line flyback signal (i.e. the pulse on the collector
of the line scanning transistor) is compared with
the line sync. signal issued by sync. separator. If
the detected coincidence is incorrect, the comparator
will then generate an appropriate positive or
negative current so as to charge or discharge the
line oscillator capacitor thereby providing for frequency
and phase locking.

Frame Oscillator
Similar to line oscillator, the frame saw-tooth is
generated by charging an external capacitor on
Pin 1 through a resistor connected to VCC1.
The capacitor is discharged via an internal 500W
resistor. The saw-tooth amplitude is set at two
on-chip threshold levels.

The free-running period is approximately given by :
TOSC 9 0.15 RC
Synchronization is achieved by period reduction.
The frame sync. pulse issued by the sync. separator
will modify the current through the resistor
bridge which is used to set the saw-tooth threshold
levels.
The minimum synchronized frame period (MSFP)
is given by :
MSFP 9
TOSC
1.8
II.7 - Frame Output Amplifier
The frame saw-tooth generated by frame oscillator
is first inverted(Gain : - 0.4) and then applied to the
non-inverting input of the frame amplifier. The output
current capability of this amplifier is as high as
± 1Athus enabling to drive vertical deflection yokes
requiring 2A peak-to-peak.
As a function of dissipated power, the device may
require the addition of a heatsink.
Afeed-backloop is connectedto the inverting input
of the frame amplifier (Pin 6).
As the CRT screen is not part of a sphere centered
on the deflectioncenter point, if the yoke is actually
driven by a saw-tooth waveform, the image is
expanded at the top and bottom. The yoke must
therefore be provided with an ”S” waveform current,
by applying linearity correction.

The circuit configuration depicted above does not
require any linearity adjustment - only an amplitude
adjustment potentiometer ”P” has been provided
for.
- D.C. Feedback : The C1 capacitor is charged to
approximately 1/2 x VCC2. Divider bridge formed
by R2 + R4 and R5 networks will set the d.c.
feedback. The component values of this divider
network will be choosen to avoid saturation at top
and bottom of the output voltage (Pin 6 biasing
voltage is approximately 0.6V).
- LinearityCorrection: Aparabolicsignal at frame
frequency is available on ”+” terminal of the C1
capacitor. This signal is integrated by R2, C2
network. An ”S” waveformis thus obtained,which
is applied to Pin 6 via resistor R4.
Any correction to this ”S” waveform depends on
C1 and C2 values. The linearity correction depends
on ratio : R2/R4
- Vertical Amplitude : Frame current amplitude is
determined by the value of measurement resistor
”R1”, potentiometer ”P” settings and the value of
”R5” resistor.
II.8 - Frame Flyback Generator
The output stage of the vertical amplifier includes
a frame flyback generator connected to pin 3.
During the vertical scanning flyback time, the value
of the yoke inductance ”L” must be taken into
account since the time constant L/R is no longer
negligible. In television applications, the frame
blanking time is 1.6ms. Thuswhen L/R > 1.6 x 10-3,
it is necessary to increase the supply voltage to the
frame output amplifier so as to reduce the flyback
time. This surplus is required only for the frame
flyback and energy is wasted by boosting the supply
to the amplifier at all times (during the frame
scanningtime, theminimumvoltage issubstantially
RI, where I is peak-to-peak frame current).

During the second half of the vertical scanning
time, transistor T2 conducts and capacitor C is
charged toVCC throughD1, D2,R3 andT2. (Switch
K open)
On flyback, switch K closes and Pin 3 is connected
to VCC. The voltage at Pin 7 (VCC2), which was
equal to VCC - VD1, is almost doubled during the
flyback time. The only external components required
are therefore D1, D2 and C.
In addition to reducing the flyback time, the flyback
generator reduces the power consumed by the
power stage, and can in certain cases avoid the
need to use a heatsink.

Diode D2 is a low-signal diode (1N4148) but diode
D1 must be appropriately rated since the positive
current in the first part of the saw-tooth is supplied
to the yoke through D1 and T1. A 1N4001 is generally
used.

The shunt regulator
The TEA2037A incorporates an internal shunt
regulator which delivers the common supply voltage
VCC to various blocks such as oscillators,
comparator, sync separator and so on.
The voltage onPin 16 is 9.7V(9V min, 10.5V max).
The value of the series resistor R must be so
calculated to obtain a 15mAcurrent on Pin 16 - this
current can be 10mAmin. and 20mAmax.

The external current supply from VCC1 to both
oscillators (i.e. line and frame) can be neglected in
majority of cases.
The resistor value is found to be 1.2kW at
VCC = +28V.
At VCC =+ 12V, and taking into account the voltage
tolerance on Pin 16, a 150W series resistor must
be used.
II.10 - Thermal Considerations
In order to ensure reliable device operation, the
dissipatedpowershould be accurately determined.
Calculation will allow an evaluation of the dissipated
power and should be completed by package
temperature measurements in actual applications.
According to results obtained, a heatsink may or
may not be required.
• Power drawn from VCC1 supply :
P1 = VCC1 . I1
Where I1 is the current through the shunt
regulator (Pin 16).
• Power drawn from VCC2 supply :
P2 = VCC2
TYU
IPP
8 + I2
NM<

Where :
- Ipp = peak-to-peak current through the vertical
deflection yoke.
- I2 = Pin 7 quiescent current.
- VCC2 = Pin 7 voltage.


CHARACTERISTICS
- Screen : 9” Monochrome
- Frame deflection yoke : 72mH, 40W,
220mApeak-to-peak
- VCC = + 25V without flyback generator
- Frame flyback time : 1.2ms
- Vertical frequency : 50Hz (20ms)
- Vertical free-running period : 24.5ms
- Horizontal frequency : 15 625Hz
- Capture range : ±5ms
- Holding range : ±10ms
- Input signal : composite video
- Dissipated power : 1.15W
- Only one adjustment : vertical amplitude
This is a low-cost applicationused in French Minitel
type configurations and requiresminimum number
of additional components and adjustments. The
input is a composite video signal at line frequency
= 15 625Hz and frame frequency of 50Hz.
The free-running horizontal frequency is determined
by the component values of RCnetwork on
Pin 9. Since no adjustment is available, precision
components must be used to ensure correct synchronization
:
[R = 35.7kW, 1% and C = 2.2nF,
2% for fH = 15 625Hz]
The capture range is large enough to compensate
for possible variations.
- Synchronizationrange of the vertical oscillator is
quite large which consequentlyallows use of less
accurate components :
[R = 910 kW, 5 % and C = 180 nF, 5 %]
- Since the frame flyback time is short enough at
supply voltage used here, the flyback generator
is not used in this application.



TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFCDESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PN P or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).

M491B SINGLE-CHIP VOLTAGE SYNTHESIS TUNING SYSTEM
WITH 1 ANALOG CONTROL:

DESCRIPTION
The M491B is a monolithic N-MOS LSI circuit including
a Floating-gate Non-Volatile Memory for
storage of up to 16 stations. Tuning of the station
is performedwith a 8192 step D/A converter, using
the principle of voltage synthesis. It is designed for
7-segment LED displays. Direct memory selection
is possibleonly from remotecontrolwhile Up/Down
memory scanning is possible on the set and also
from remote control. An option input for 8 or 16
stations is available. The circuit also includes a
PCM remote control receiver operating in conjunction
with the transmitter M708. The highly reliable
transmission code ensures error-free signal detection
even in presence of high noise conditions.
Search of the station is possible in automatic or
manual modes. The circuit can operate with a
Digital or LinearAFT control. The Digital AFTmode
is necessary for automatic search and requires an
external circuit (TDA4433 or equivalent, e.g. dual
comparator plus TV station detector) to convert the
AFC-S-curve into an Up/Down command.Fine tuning
(detuning) is also possible with different modes
of operation.Thecircuit is assembledin 40-pindual
in-line plastic package.

16-STATION MEMORY - 7-SEGMENT LED
DISPLAY .VOLTAGESYNTHESIZER : 13 BITS .4-BAND PRESET CAPABILITY .NON-VOLATILEMEMORY : 304 BITS
- 16 WORDS OF 19 BITS FORTUNING VOLTAGE
(13 bits) - BAND (2 bits) - FINE DETUNING
(4 bits)
- 104 MODIFY CYCLES PER WORD
- MIN 10 YEARS DATA RETENTION .PCM REMOTE CONTROL RECEIVER : DECODES
SIGNAL TRANSMITTED BY M708 .VOLUME D/A : 6-BIT RESOLUTION / 8kHz .MEMORY SKIP FUNCTION .AUTOMATIC SEARCH WITH DIGITAL AFT
CONTROL .FINE DETUNING D/A ACTING ON AFT DISCRIMINATOR
(16 steps) WITH SEPARATE
STORAGE FOR EACH MEMORY POSITION.
ALTERNATIVELYIT CAN BE USED TO CONTROL
BRIGHTNESS OR COLOUR SATURATION
.MANUAL SEARCH WITH DIGITAL AFT CONTROL
.MANUAL SEARCHWITH LINEAR AFT .SWEEP SEARCH DISPLAY OUTPUT .SUPPLYVOLTAGES : VDD = + 5V,
VPP = + 25V FOR THE MEMORY .CLOCK OSCILLATOR: 445 TO 510kHz .INTEGRATED DIGITAL POWER ON RESET
(no external initialization circuitry required)

DESCRIPTION(All timings at fclock = 500kHz)
PIN 1 : VSS
The substrateof the IC isconnectedto thispin. This
is the reference pin for all parameters of the IC.
PIN 2 : MEMORY SUPPLYVOLTAGE
A supply voltage of 25 ± 1 V has to be applied to
this pin during the modify and read cycles.
MODIFY CYCLE
A modify cycle consists of three steps :
1. All ”1”s arewritten in thebits of the selected word.
2. All bits of the selected word are erased (all ”0”s)
3. The new content is written.
Thus a constant aging of all the bits of the word is
obtained.
During both write and erase cycles the memory
status is checked continuously ; therefore after
each writeor erase pulsea read operationis carried
out. The write or the erase operations are stopped
as soon as the result of the read operation is valid.
WRITE CYCLE. The peak of the current flowing
through pin 2 during a write operation is shown in
fig. 1, while fig. 2 shows the envelope of the same
current.
The typical write time is 3-4 ms for the first cycles
and increases to about 30 ms after 1000 cycles.

PIN 3 : MEMORY TIMING OUTPUT
This output gives the timing for the pulses to be
applied at Pin 2 during the modify and read cycles.
The output consists of an open drain transistor.
PIN 4 : FINE TUNING D/A (see Figure 5)
A D/A converter with 16-step resolution and a frequency
of 15kHz can be used to generatea voltage
which, if fed to a varicap diode in parallel to the AFC
discriminator, will detune the receiver by a small Df
while maintainingthe action of the Digital AFT. This
output can be used in conjunction with both Linear
and Digital AFT modes of operations.
The Fine tuning function operates as follows :
- At the start of any automatic or manual search,
the output is set at the mid range.
- When the search has been completed it is possible
to operate on FT ± commands.
The store command memorizes this information
together with the 13 tuning voltage bits and 2
information bits.
- Modification time of FT D/A is of 1 step every
200ms if issued locally or every 2 received signals
from Remote control transmitter.
PIN 5 : TUNING D/A (see Figure 6)
A 213 = 8192 step pulse modulated signal for the
tuning voltage is available on this pin.
Pulse modulation is implemented by combination
of a rate multiplier and pulse width principle.
With a tuning voltage increasing from zero, the
number of pulses increases continuously up to
28 = 256 ; starting from this point the number of
pulses remains the same but the pulses get larger
until they reach the maximum content of the internal
counter. The output consists of an open drain
transistor which offers a low impedance to ground
when in the ON state.

PIN 6 : DIGITAL AFT STATUS OUTPUT
(see Figure 7)
This output shows the status of the digital AFT. It is
low when the digital AFT is enabled and it can
directly drive a LED.
The output consists of an open drain transistor.
PINS 7 & 8 : OSCILLATORINPUT/OUTPUT
(see Figure 8)
The frequency of the clock oscillator should be
between 445 and 510kHzusing a low-cost ceramic
resonator. In these conditions the value of the
reference frequency of the transmitter can be in the
same range. In other words the transmitter and the
receiver can operate with different reference frequencies.

PIN 9 : VDD
The supply voltage has to be comprised in the
range 4.75 to 5.25V. When it is applied an internal
power on reset of 0.5s is generated.
The memory position 1 is automatically read if the
mains on option input (Pin 25) is grounded.
PIN 10 : TEST
This pin is used for testingand has to be connected
to VSS.
PIN 11 : I.R. SIGNAL INPUT (see Figure 9)
The integrated receiver decodes signals transmitted
by M708, address 9.
The minimum signal to be applied is 0.5V peak-topeak.
(AC-coupled).
The receiver input section performs the following
tests on the incoming signal to achieve the necessary
noise immunity :
- measurement of the pulse distance (time base
synchronization)

- check of the position of the received bits opening
window at the time bases
- check of the parity bit
- checkof the absenceof pulsesbetween theparity
bit and the stop pulse
- checkof noiselevel ; the receiver checks parasitic
transients inside and outside the time windows.
If the above test conditions are not fulfilled, the
received word is rejected and not decoded. If the
received signal is acknowledged as a valid word it
is stored an decoded.
The end of transmission will be acknowledged by
receiving the end of transmission code or bymeans
of an internal timer if the transmission remains interrupted for more than about 550ms.

PINS 12 & 13 : AFT1-AFT2 (STOP/AFT INPUTS)
These pins are enabled during the automatic
search and during normal operation, when the
digital AFT is enabled (see description of Pin 17).
The STOP/AFT inputs are also disabled internally
duringany programor bandchange for the duration
of the Mute signal.

These inputs have two different functions depending
on whether the system is in the search or in
normal operation (AFT control).
The inputs have internal pull-up resistors of 30kW
typ.
A) Searchmode : after depressing the Automatic
search or preset keys, the levels of the signals
coming from the TDA4433, applied to these
pins, control the search function and determine
when the searchmust stop, i.e. a TV stationhas
been recognized.
The circuit operates in the following sequence
(see Figure 10 for reference) :
1 - after pressing the search start key the
search occurs in the FAST UP mode.
2 - eventual transitions available on these
inputs are ignored during the first 15 search
steps if the system is in the UHF or CATV
bands.
If the system operates in VHF I and III bands,
the first 60 search steps are ignored. The
acceptance delay of 15 (60) search steps has
been introduced to prevent the system from
stopping at the previous station.
After this time the FAST UP speed is
automatically reduced to half during each UP
signal (MEDIUM UP = FAST UP/2).
A DOWN signal preceded by at least an UP
signal will set the search to MEDIUM DOWN
mode (FAST UP/4).
3 - the next UP signal will switch the search to
SLOWUP speed (61Hz).
At this point the systems is in normal AFT
operation.
B) Digital AFT operation : when a station is
perfectly tuned, the input signals coming from
TDA4433 are at middle condition.
If the tuning moves lower than the threshold
below 38.9MHz, the Pin 12 is put H and Pin 13
is put L ; the 13 bit internal counter is moved
SLOW UP speed to increase the varicap
voltage.
When a detuning occurs in the opposite
direction the input 12 goes Low and 13 goes
High and the tuning voltage falls at VERY
SLOWDOWN speed (7.6Hz).
The increase or decrease of the tuning voltage
is stopped as soon as the input returns to
middle conditions.
Therefore during normal operation Pins 12 and
13 act as digital AFT control commands.
C) Recall from memory : when the digital AFT is
enabled and data is recalled from Memory, a
fixed value of 8 steps (9 31.2mV) is subtracted
from the tuning voltage.
This corresponds to a detuning of 0.6MHz
(UHF) and of 0.3MHz in VHF III into that part of
the IF response curve which correspondsto the
fully transmitted sideband.
At this point the AFT operation takes over as
described in point B above and the exact tuning
is achieved in about 0.2 sec.
This feature increases the AFT capture range
and fullfills the stability requirements of the
tuner, vol tage references and the D/A
converter.
If the Digital AFTis disabled (Pin 17 at VSS), the
memory content is read without any change.

PIN 14 : SWEEP SEARCH DISPLAYOUTPUT
This output, which is normally Low, goes High
during automatic search automatic preset et intervals
of 160ms for about 40ms to blank the LED of
band display.

PIN 15 : VOLUME D/AOUTPUT
This output delivers a square wave signal of 7.8
kHz and duty cycle variable in 63 steps. In case of
a continuouscommand for varying the volume, the
duty cycle is changed at the rate of the transmitted
signal (approximately every 102ms with fref =
500kHz) or every 112ms if issued locally.
Overflow and underflow protection are provided.
The volume output can be switched to VSS and
reset to the previous level by means of the Mute
On/Off command. It is also reset by the Volume
Up/Down and the Mains On/Off commands.
The volume is muted for about 1s at each mains
on and off commandduring the power on reset time
and program change (0.5s).
At the first power on reset of VDD the volume D/A
is set at the level 21/64. The last level is preserved
until VDD is not removed.

PIN 16 : LINEAR AFT DEFEAT OUTPUT
This output is normally High and goes Low when a
Manual Up/Down command is issued.
It returns High with a 1 second delay from the
release of the key, in order to give the user the
possibility of the tuning adjustmentwithout the AFT
intervention. It goes Low for 0.5s during program
change.
20
MEMORY
UP
DIGITAL
AFT ON
BAND
SEQ.
BAND
I
MEMORY
DOWN
AUTOMATIC
SEARCH
POWER
ON/OFF
BAND
III
VOLUME
UP
BAND
UHF
MAN SEARCH
DOWN
MAN SEARCH
UP
FT.
DOWN
FT.
UP
VOLUME
DOWN
BAND
CATV
19 18
AUTOMATIC
PRESET
MEMORY
ADDRESSING
STORE
MUTE
23 22 21 24
V1 V2 V3 X1 X2 X3 X4
491B-15.EPS
Figure 13
PIN 17 : DIGITAL AFT ENABLE INPUT
If this input is connected to VSS (GND), the digital
AFT loop is always disabled. If pin 17 is left open
or is connected to VDD, the digital AFT is automatically
enabled at power on. When a manual
up/down search commandis issued, the digitalAFT
loop is disabled and the digital AFT status output is
inhibited.
The digital AFT loop is restored by the commands:
Digital AFT on/Automaticsearch/Automaticpreset.
PINS 18-19-20-21-22-23-24:
KEYBOARD MATRIX (see Figure 13)
A command is accepted if the corresponding contact
has been closed for a minimum time of 30ms.
Local input commands and I.R. commands have
the same priority.
If a complete I.R. command has been received, the
local inputs are blocked until the command has
been executed and the ”end of transmission code”
generated.
Viceversa an I.R. signal cannot be decoded until
an issued local command has been executed.
MEMORY UP/DOWN
Depressing one of these twocommands, the memory
position is stepped in the UP or DOWN direction.
If the key is kept closed, the channels are stepped
UP/DOWNevery 0.5 second or every5 commands
from the transmitter.
The memory locations 9 to 16 are jumped if pin 31
is at GND level.
BAND SELECTION
The bands can be selected either directly or with a
step-by-step command in the following sequence :
VHF I
CATV
VHF III
UHF
VHF I and so on
Only one band change is performed at each accepted
command.
Disabled bands are automatically skipped. Aband
can be disabled connecting the correspondingoutput
to VSS.

SEARCH MODES
4 modes are available :
a) Automatic search (digiatl AFT)
b) Automatic preset
c) Manual up/down (digital and linear AFT)
d) Manual up/down (linear AFT)
a) AUTOMATIC SEARCH. The search starts from
the actual tuning and band position. During the
search the tuning voltage is always changing from
lower to higher voltage levels. When the end of the
band is reached the search restarts from the beginning
of the next band after a 480 ms interruption
with the sequenceof step-by-step band selection.
Disabled bands are automaticallyskipped.
The search is stopped when the first station is
found or if a channel selection command is given.
Stop of the automatic search is determined by the
STOP/AFTinputs controlledby theTDA4433which
converts the AFC-S-curve into an up/down command.
At the end of the search the up/down command
controls the correct tuning acting on the counter of
the voltage synthesizer (Digital AFT).
It is important to call the attention to the Digital AFT
capturerangewhich is larger than the normallinear
AFT.

Additionally the use of the Digital AFT allows storage
of the tuning information corresponding to the
zero point of the AFC-S-curve. This cannot be
guaranteed using the LinearAFT method only. The
latter is a cheaper system, because it does not
require the use of the TDA4433 but it cannot guarantee
what described above.
As a result of the use of the Digital AFT, the requirements
for stability of the tuner, of the reference
voltage source and of stability of the D/A converter
are less critical.
Tuning speed in automatic search, if no station is
found is :
VHF I 8 second
VHF III 8 second
UHF 32 second
CATV 32 second
The tuning and band information can be stored
using the store/memory addressing command.
The search can be stopped by a memory selection
command.
b) AUTOMATIC PRESET. The search starts from
the lowest memory address, tuning voltage and
VHF I band as described in automatic search
mode.
When an active station is encountered, the corresponding
tuning and band information is automatically
stored in the Non-Volatile Memory.
Afterwards the system starts to search for the next
station. The cycle is repeated until all bands have
been scanned or the tuning information has been
stored into all address locations. After completing
this cycle the system reads out the tuning information
of the lowest address.
c) MANUAL UP/DOWN WITH DIGITAL AND LINEAR
AFT (pin 17 at VDD). Holding one of these
commands pressed, the tuning voltage is increased
or decreased.
During this operation, the Digital AFT is automatically
defeated and can only be reconnected with
the ”AFT on” command or by an Automatic search
or preset command.
The search speed is kept at minimum (there is no
increment with the time).

Band Sweep Timefor the
Complete Band
Number of Tuning
Steps/Second
VHF I
VHF III
UHF
CATV
seconds
128 seconds
128 seconds
512 seconds
512
16
64
64
16
In case of command received from remote control,
the counter is increased/decreased every two received
commands.
No band switching is provided at the upper or lower
tuning positions.
The volume is automaticallymuted 3 second after
the key pressure is immediately restored at the
release of the key.
d)MANUAL UP/DOWN WITHLINEARAFT (pin 17
at VSS). When this control is used the Digital AFT
is disabled.
TheLinearAFToutput goes lowafteranup ordown
command is issued and remains Low for 1 second
after the release of the key.


The volume is automatically muted for 3 seconds
after the key pressure and is immediately restored
at the release of the key.
Tuning speeds are as follows :
- FINE TUNING UP/DOWN
See description of pin 4.
- DIGITALAFT ON
See description of pin 17.
- VOLUMEUP/DOWN
See description of pin 15.
- MAINS ON/OFF
See description of pins 25 and 26.
Band
Number of Tuning Steps Second
Time 0 After 1 s After 2 s After 3 s
VHF I
VHF III
UHF
CATV
64
64
16
16
128
128
32
32
256
256
64
64
512
512
128
128
491B-06.TBL
STORECOMMANDS
2 modes of operations are available.
a)store
b)memory addressing
In order to protect the memory, the store function
is internally disabled after one store cycle.
It is enabled after a program change or a tuning
operation (it is not disabled by the Digital AFT
control).
a) STORE. The tuning information (Tuning D/A,
Fine tuning D/A and band) is stored in a previously
selected memory address when this command is
issued.
b) MEMORY ADDRESSING. The tuning information
can also be stored with this command followed
by the memory position selection.
When this command is accepted all the memory
LEDs are blanked.
Selection of the memory position initiates the store
operations and restores the display.
MUTE ON/OFF
See description of pin 15.

PIN 25 : MAINS ON OPTION INPUT
If connected to VSS (GND) the Mains output is
automatically switched on when VDD isappliedand
memory 1 is read.
If it is connected to VDD the circuit goes in stand by
condition.
PIN 26 : MAINS ON/OFF OUTPUT
Switch on of the set is controlled by the Mains on
command issued for more than 0.3 s. The output
transistor is set in the off condition to drive through
an integrated pull-up resistor, an external NPN
transistor.
+5V
491B-17.EPS
Figure 15
At each Mains on command a memory read out
occurs.AVPP (+ 25 V) is required for this operation,
a 1 second delay starts when the mains output is
switched off. For a correct reading of the memory
the VPP supply voltage must reach the value of 25
V within 1 second after a Mains on command.
In case of automatic switch on at power on caused
by pin 25 at GND, the total delay is of 1.13 second
(0.13s for VDD power on reset plus 1 second for
mains on).
TheMains on/off command,if repeated, will switch
the output on (set off).
The last addressinformation is preserved untilVDD
is present.
Next Mains on command will switch the set at the
previously selected memory address and a read
operation will be performed.
PINS 27-28-29-30-33-34-35-36:
MEMORY ADDRESS OUTPUT
These pins operate asoutput only for display of the
selected memory location. Max drive capability is
of 15 mA/1.2V with the exception of pin 36 that is
of 30 mA/1.5 V.
Direct memory selection is only possible by remote
control.Alocalmemory up/downcommand is available
in case of emergency.
Pin 32 must be grounded.
If pin 31 is grounded, the memory position 9 to 16
are skipped in case of memory up/down commands.
For normal operation pin 31 can be left open or,
better, connected to VDD.
PINS 31-32
See description of pins 27 to 30 and 33 to 36.
PINS 37-38-39-40 : BAND INPUT/OUTPUT
These outputs are provided to select up to 4 bands
via external PNPs.
If one or more bands have to be skipped, the
corresponding outputshave to be short-circuited to
VSS.