ZANUSSI CHASSIS BS950 Supply is based on TDA4600 (SIEMENS).
Power supply Description based on TDA4601d (SIEMENS)
TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
The invention relates to a blocking oscillator type switching power supply for supplying power to electrical equipment, wherein the primary winding of a transformer, in series with the emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, and a secondary winding of the transformer is provided for supplying power to the electrical equipment, wherein, furthermore, the first bipolar transistor has a base controlled by the output of a control circuit which is acted upon in turn by the rectified a-c line voltage as actual value and by a set-point transmitter, and wherein a starting circuit for further control of the base of the first bipolar transistor is provided.
Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings, in which:
FIGS. 1 and 2 are circuit diagrams of the blocking oscillator type switching power supply according to the invention; and
FIG. 3 is a circuit diagram of the control unit RS of FIGS. 1 and 2.
Referring now to the drawing and, first, particularly to FIG. 1 thereof, there is shown a rectifier circuit G in the form of a bridge current, which is acted upon by a line input represented by two supply terminals 1' and 2'. Rectifier outputs 3' and 4' are shunted by an emitter-collector path of an NPN power transistor T1 i.e. the series connection of the so-called first bipolar transistor referred to hereinbefore with a primary winding I of a transformer Tr. Together with the inductance of the transformer Tr, the capacitance C1 determines the frequency and limits the opening voltages of the switch embodied by the first transistor T1. A capacitance C2, provided between the base of the first transistor T1 and the control output 7,8 of a control circuit RS, separates the d-c potentials of the control or regulating circuit RS and the switching transistor T1 and serves for addressing this switching transistor T1 with pulses. A resistor R1 provided at the control output 7,8 of the control circuit RS is the negative-feedback resistor of both output stages of the control circuit RS. It determines the maximally possible output pulse current of the control circuit RS. A secondary winding II of the transformer Tr takes over the power supply of the control circuit, in steady state operation, via the diode D1. To this end, the cathode of this diode D1 is directly connected to a power supply input 9 of the control circuit RS, while the anode thereof is connected to one terminal of the secondary winding II. The other terminal of the secondary winding II is connected to the emitter of the power switching transistor T1.
The cathode of the diode D1 and, therewith, the power supply terminal 9 of the control circuits RS are furthermore connected to one pole of a capacitor C3, the other pole of which is connected to the output 3' of the rectifier G. The capacitance of this capacitor C3 thereby smoothes the positive half-wave pulses and serves simultaneously as an energy storage device during the starting period. Another secondary winding III of the transformer Tr is connected by one of the leads thereof likewise to the emitter of the first transistor T1, and by the other lead thereof via a resistor R2, to one of the poles of a further capacitor C4, the other pole of which is connected to the first-mentioned lead of the other secondary winding III. This second pole of the capacitor C4 is simultaneously connected to the output 3' of the rectifier circuit G and, thereby, via the capacitor C3, to the cathode of the diode D1 driven by the secondary winding II of the transformer Tr as well as to the power supply input 9 of the control circuit RS and, via a resistor R9, to the cathode of a second diode D4. The second pole of the capacitor C4 is simultaneously connected directly to the terminal 6 of the control circuit RS and, via a further capacitor C 6, to the terminal 4 of the control circuit RS as well as, additionally, via the resistor R6, to the other output 4' of the rectifier circuit G. The other of the poles of the capacitor C4 acted upon by the secondary winding II is connected via a further capacitor C5 to a node, which is connected on one side thereof, via a variable resistor R4, to the terminals 1 and 3 of the control circuit RS, with the intermediary of a fixed resistor R5 in the case of the terminal 1. On the other side of the node, the latter and, therefore, the capacitor C5 are connected to the anode of a third diode D2, the cathode of which is connected on the one hand, to the resistor R2 mentioned hereinbefore and leads to the secondary winding III of the transformer Tr and, on the other hand, via a resistor R3 to the terminal 2 of the control circuit RS.
The nine terminals of the control circuit RS have the following purposes or functions:
Terminal 1 supplies the internally generated reference voltage to ground i.e. the nominal or reference value required for the control or regulating process;
Terminal 2 serves as input for the oscillations provided by the secondary winding III, at the zero point of which, the pulse start of the driving pulse takes place;
Terminal 3 is the control input, at which the existing actual value is communicated to the control circuit RS, that actual value being generated by the rectified oscillations at the secondary winding III;
Terminal 4 is responsive to the occurrence of a maximum excursion i.e. when the largest current flows through the first transistor T1 ;
Terminal 5 is a protective input which responds if the rectified line voltage drops too sharply; Terminal 6 serves for the power supply of the control process and, indeed, as ground terminal;
Terminal 7 supplies the d-c component required for charging the coupling capacitor C2 leading to the base of the first transistor T1 ;
Terminal 8 supplies the control pulse required for the base of the first transistor T1 ; and
Terminal 9 serves as the first terminal of the power supply of the control circuit RS.
Further details of the control circuit RS are described hereinbelow.
The capacity C3 smoothes the positive half-wave pulses which are provided by the secondary winding II, and simultaneously serves as an energy storage device during the starting time. The secondary winding III generates the control voltage and is simultaneously used as feedback. The time delay stage R2 /C4 keeps harmonics and fast interference spikes away from the control circuit RS. The resistor R3 is provided as a voltage divider for the second terminal of the control circuit RS. The diode D2 rectifies the control pulses delivered by the secondary winding III. The capacity C5 smoothes the control voltage. A reference voltage Uref, which is referred to ground i.e. the potential of terminal 6 is present at the terminal 1 of the control circuit RS. The resistors R4 and R5 form a voltage divider of the input-difference control amplifier at the terminal 3. The desired secondary voltage can be set manually via the variable resistor R4. A time-delay stage R6 /C6 forms a sawtooth rise which corresponds to the collector current rise of the first bipolar transistor T1 via the primary winding I of the transformer Tr. The sawtooth present at the terminal 4 of the control circuit RS is limited there between the reference voltage 2 V and 4 V. The voltage divider R7 /R8 (FIG. 2), brings to the terminal 5 of the control circuit RS the enabling voltage for the drive pulse at the output 8 of the control circuit RS.
The diode D4, together with the resistor R9 in cooperation with the diode D1 and the secondary winding II, forms the starting circuit provided, in accordance with the invention. The operation thereof is as follows:
After the switching power supply is switched on, d-c voltages build up at the collector of the switching transistor T1 and at the input 4 of the control circuit RS, as a function in time of the predetermined time constants. The positive sinusoidal half-waves charge the capacitor C3 via the starting diode D4 and the starting resistor R9 in dependence upon the time constant R9.C3. Via the protective input terminal 5 and the resistor R11 not previously mentioned and forming the connection between the resistor R9 and the diode D1, on the one hand, and the terminal 5 of the control circuit RS, on the other hand, the control circuit RS is biased ready for switching-on, and the capacitor C2 is charged via the output 7. When a predetermined voltage value at the capacitor C3 or the power supply input 9 of the control circuit RS, respectively, is reached, the reference voltage i.e. the nominal value for the operation of the control voltage RS, is abruptly formed, which supplies all stages of the control circuit and appears at the output 1 thereof. Simultaneously, the switching transistor T1 is switched into conduction via the output 8. The switching of the transistor T1 at the primary winding T of the transformer Tr is transformed to the second secondary winding II, the capacity C3 being thereby charged up again via the diode D1. If sufficient energy is stored in the capacitor C3 and if the re-charge via the diode D1 is sufficient so that the voltage at a supply input 9 does not fall below the given minimum operating voltage, the switching power supply then remains connected, so that the starting process is completed. Otherwise, the starting process described is repeated several times.
In FIG. 2, there is shown a further embodiment of the circuit for a blocking oscillator type switching power supply, according to the invention, as shown in FIG. 1. Essential for this circuit of FIG. 2 is the presence of a second bipolar transistor T2 of the type of the first bipolar transistor T1 (i.e. in the embodiments of the invention, an npn-transistor), which forms a further component of the starting circuit and is connected with the collector-emitter path thereof between the resistor R9 of the starting circuit and the current supply input 9 of the control circuit RS. The base of this second transistor T2 is connected to a node which leads, on the one hand, via a resistor R10 to one electrode of a capacitor C7, the other electrode of which is connected to the anode of the diode D4 of the starting circuit and, accordingly, to the terminal 1' of the supply input of the switching power supply G. On the other hand, the last-mentioned node and, therefore, the base of the second transistor T2 are connected to the cathode of a Zener diode D3, the anode of which is connected to the output 3' of the rectifier G and, whereby, to one pole of the capacitor C3, the second pole of which is connected to the power supply input 9 of the control circuit RS as well as to the cathode of the diode D1 and to the emitter of the second transistor T2. In other respects, the circuit according to FIG. 2 corresponds to the circuit according to FIG. 1 except for the resistor R11 which is not necessary in the embodiment of FIG. 2, and the missing connection between the resistor R9 and the cathode of the diode D1, respectively, and the protective input 5 of the control circuit RS.
Regarding the operation of the starting circuit according to FIG. 2, it can be stated that the positive sinusoidal half-wave of the line voltage, delayed by the time delay stage C7, R10 drives the base of the transistor T2 in the starting circuit. The amplitude is limited by the diode D3 which is provided for overvoltage protection of the control circuit RS and which is preferably incorporated as a Zener diode. The second transistor T2 is switched into conduction. The capacity C3 is charged, via the serially connected diode D4 and the resistor R9 and the collector-emitter path of the transistor T2, as soon as the voltage between the terminal 9 and the terminal 6 of the control circuit RS i.e. the voltage U9, meets the condition U9 <[UDs -UBE (T2)].
Because of the time constant R9.C3, several positive half-waves are necessary in order to increase the voltage U9 at the supply terminal 9 of the control circuit RS to such an extent that the control circuit RS is energized. During the negative sine half-wave, a partial energy chargeback takes place from the capacitor C3 via the emitter-base path of the transistor T2 of the starting circuit and via the resistor R10 and the capacitor C7, respectively, into the supply network. At approximately 2/3 of the voltage U9, which is limited by the diode D3, the control circuit RS is switched on. At the terminal 1 thereof, the reference voltage Uref then appears. In addition, the voltage divider R5 /R4 becomes effective. At the terminal 3, the control amplifier receives the voltage forming the actual value, while the first bipolar transistor T1 of the blocking-oscillator type switching power supply is addressed pulsewise via the terminal 8.
Because the capacitor C6 is charged via the resistor R6, a higher voltage than Uref is present at the terminal 4 if the control circuit RS is activated. The control voltage then discharges the capacitor C6 via the terminal 4 to half the value of the reference voltage Uref, and immediately cuts off the addressing input 8 of the control circuit RS. The first driving pulse of the switching transistor T1 is thereby limited to a minimum of time. The power for switching-on the control circuit RS and for driving the transistor T1 is supplied by the capacitor C3. The voltage U9 at the capacitor C3 then drops. If the voltage U9 drops below the switching-off voltage value of the control circuit RS, the latter is then inactivated. The next positive sine half-wave would initiate the starting process again.
By switching the transistor T1, a voltage is transformed in the secondary winding II of the transformer Tr. The positive component is rectified by the diode D1, recharing of the capacitor C3 being thereby provided. The voltage U9 at the output 9 does not, therefore, drop below the minimum value required for the operation of the control circuit RS, so that the control circuit RS remains activated. The power supply continues to operate in the rhythm of the existing conditions. In operation, the voltage U9 at the supply terminal 9 of the control circuit RS has a value which meets the condition U9 >[UDs -UBE (T2)], so that the transistor T2 of the starting circuit remains cut off.
For the internal layout of the control circuit RS, the construction shown, in particular, from FIG. 3 is advisable. This construction is realized, for example, in the commercially available type TDA 4600 (Siemens AG).
The block diagram of the control circuit according to FIG. 3 shows the power supply thereof via the terminal 9, the output stage being supplied directly whereas all other stages are supplied via Uref. In the starting circuit, the individual subassemblies are supplied with power sequentially. The d-c output voltage potential of the base current gain i.e. the voltage for the terminal 8 of the control circuit RS, and the charging of the capacitor C2 via the terminal 7 are formed even before the reference voltage Uref appears. Variations of the supply voltage U9 at terminal 9 and the power fluctuations at the terminal 8/terminal 7 and at the terminal 1 of the control circuit RS are leveled or smoothed out by the voltage control. The temperature sensitivity of the control circuit RS and, in particular, the uneven heating of the output and input stages and input stages on the semiconductor chip containing the control circuit in monolithically integrated form are intercepted by the temperature compensation provided. The output values are constant in a specific temperature range. The message for blocking the output stage, if the supply voltage at the terminal 9 is too low, is given also by this subassembly to a provided control logic.
The outer voltage divider of the terminal 1 via the resistors R5 and R4 to the control tap U forms, via terminal 3, the variable side of the bridge for the control amplifier formed as a differential amplifier. The fixed bridge side is formed by the reference voltage Uref via an internal voltage divider. Similarly formed are circuit portions serving for the detection of an overload short circuit and circuit portions serving for the "standby" no-load detection, which can be operated likewise via terminal 3.
Within a provided trigger circuit, the driving pulse length is determined as a function of the sawtooth rise at the terminal 4, and is transmitted to the control logic. In the control logic, the commands of the trigger circuit are processed. Through the zero-crossing identification at input 2 in the control circuit RS, the control logic is enabled to start the control input only at the zero point of the frequency oscillation. If the voltages at the terminal 5 and at the terminal 9 are too low, the control logic blocks the output amplifier at the terminal 8. The output amplifier at the terminal 7 which is responsible for the base charge in the capacitor C2, is not touched thereby.
The base current gain for the transistor T1 i.e. for the first transistor in accordance with the definition of the invention, is formed by two amplifiers which mutually operate on the capacitor C2. The roof inclination of the base driving current for the transistor T1 is impressed by the collector current simulation at the terminal 4 to the amplifier at the terminal 8. The control pulse for the transistor T1 at the terminal 8 is always built up to the potential present at the terminal 7. The amplifier working into the terminal 7 ensures that each new switching pulse at the terminal 8 finds the required base level at terminal 7.
Supplementing the comments regarding FIG. 1, it should also be mentioned that the cathode of the diode D1 connected by the anode thereof to the one end of the secondary winding II of the transformer Tr is connected via a resistor R11 to the protective input 5 of the control circuit RS whereas, in the circuit according to FIG. 2, the protective input 5 of the control circuit RS is supplied via a voltage divider R8, R7 directly from the output 3', 4' of the rectifier G delivering the rectified line a-c voltage, and which obtains the voltage required for executing its function. It is evident that the first possible manner of driving the protective input 5 can be used also in the circuit according to FIG. 2, and the second possibility also in a circuit in accordance with FIG. 1.
The control circuit RS which is shown in FIG. 3 and is realized in detail by the building block TDA 4600 and which is particularly well suited in conjunction with the blocking oscillator type switching power supply according to the invention has 9 terminals 1-9, which have the following characteristics, as has been explained in essence hereinabove:
Terminal 1 delivers a reference voltage Uref which serves as the constant-current source of a voltage divider R5.R4 which supplies the required d-c voltages for the differential amplifiers provided for the functions control, overload detection, short-circuit detection and "standby"-no load detection. The dividing point of the voltage divider R5 -R4 is connected to the terminal 3 of the control circuit RS. The terminal 3 provided as the control input of RS is controlled in the manner described hereinabove as input for the actual value of the voltage to be controlled or regulated by the secondary winding III of the transformer Tr. With this input, the lengths of the control pulses for the switching transistor T1 are determined.
Via the input provided by the terminal 2 of the control circuit RS, the zero-point identification in the control circuit is addressed for detecting the zero-point of the oscillations respectively applied to the terminal 2. If this oscillation changes over to the positive part, then the addressing pulse controlling the switching transistor T1 via the terminal 8 is released in the control logic provided in the control circuit.
A sawtooth-shaped voltage, the rise of which corresponds to the collector current of the switching transistor T1, is present at the terminal 4 and is minimally and maximally limited by two reference voltages. The sawtooth voltage serves, on the one hand as a comparator for the pulse length while, on the other hand, the slope or rise thereof is used to obtain in the base current amplification for the switching transistor T1, via the terminal 8, a base drive of this switching transistor T1 which is proportional to the collector current.
The terminal 7 of the control circuit RS as explained hereinbefore, determines the voltage potential for the addressing pulses of the transistor T2. The base of the switching transistor T1 is pulse-controlled via the terminal 8, as described hereinbefore. Terminal 9 is connected as the power supply input of the control circuit RS. If a voltage level falls below a given value, the terminal 8 is blocked. If a given positive value of the voltage level is exceeded, the control circuit is activated. The terminal 5 releases the terminal 8 only if a given voltage potential is present.
DE2417628A1 1975-10-23 363/37
DE2638225A1 1978-03-02 363/49
Grundig Tech. Info. (Germany), vol. 28, No. 4, (1981).
IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 978, 979, Aug. 1976.
German Periodical, "Funkschau", (1975), No. 5, pp. 40 to 44.
TDA8172 TV VERTICAL DEFLECTION OUTPUT CIRCUIT.
The TDA8172 is a monolithic integrated circuit in
HEPTAWATTTM package. It is a high efficiency
power booster for direct driving of vertical windings
of TV yokes. It is intended for use in Color and B &
The power dissipated in the circuit must be removed
by adding an external heatsink.
Thanks to the HEPTAWATTTM package attaching
the heatsink is very simple, a screw or a compression
spring (clip) being sufficient.
Between the heatsink and the package it is better
to insert a layer of silicon grease, to optimize the
thermal contact ; no electrical isolation is needed
between the two surfaces, since the tab is connected
to Pin 4 which is ground.
REX (ZANUSSI) 33RS627 CHASSIS BS950 Picture in Picture (PiP) is a feature of some television receivers and similar devices. One program (channel) is displayed on the full TV screen at the same time as one or more other programs are displayed in inset windows. Sound is usually from the main program only.
Picture in Picture requires two independent tuners or signal sources to supply the large and the small picture. Two-tuner PiP TVs have a second tuner built in, but a single-tuner PiP TV requires an external signal source, which may be an external tuner, VCR, DVD player, or a cable box. Picture in Picture is often used to watch one program while waiting for another to start, or advertisements to finish.
Adding a picture into an existing picture was done long before affordable PiP was available on consumer products. The first PiP was seen on the televised coverage of the 1976 Montreal Olympics where a Quantel digital framestore device was used to insert a close-up picture of the Olympic flame during the opening ceremony. In 1980, NEC introduced its "Popvision" television (CV-20T74P)  in Japan with a rudimentary picture-aside-picture feature: a separate 6" (15 cm) CRT and tuner complemented the set's main 20" (50 cm) screen. It was pricey: its ¥298,000 MSRP was equal to about $1,200 (at $1 = ¥250 ), and $1,200 in 1980 had the approximate buying power of $3,000 in 2007 .
An early consumer implementation of Picture-In-Picture was the Multivision set-top box; it was not a commercial success. Later PiP became available as a feature of advanced television receivers, Like the SCHNEIDER STV707 DTV-2-7025-11 (49474A) CHASSIS DTV2 PIP here in collection !!
- CCU3000 PIP
Picture-in-picture means the insertion of a second programs picture on the screen of a CTV receiver (at reduced size) simultaneously with the full-size main picture. The second, smail picture may origine from anofher TV"transmitter, from a video recorder, a monitor camera or another source. It allows monitoring of the second channel while watching the main channel. Main requirementfor picture-in-picture is to store the content of the small picture when it is supplied by its source, and to deliver the content at the proper Instant when it must be inserted into the main picture which is received and displayed continuously. For storing the content of the second, small picture, two standard 64 K dynamic RAMs (16 x 4) are used, thus makingthe storage simple and economic. Todays picture-in-picture fits neatless Into the wellknown DIGIT2000 system, but is also suitable for stand-alone applications. The PIP2250 is a fast signal processor in CMOS technology which is used to filter (for anti-aliasing) and to decimate the digital Y, R-Yand B-Y signal supplied by the VSP2850 VideoSync Processor, to control the DRAMs for storing the small pictures content and for reading the same at the proper time for display. Further, a border generator supplies the borderline for the small picture VSP2850 VideoSync Processor (40-Pin Plastic Package).
is a digital signal processor in NMOS technology, which is able to cover all functions of digital signal processing In the video and sync section of a digital TV receiver which normally are combined" in the VPU and DPU processors and the MCU clock generator of the DIGIT2000 digital TV system. The VSP2850 is intended for the sec9iid video channel in digital TV receivers equipped with the picture-inpicture facility. Main features of the VSP2850 VideoSync Processor are: - luma channel with delay compensation, color trap, peaking filter, contrast multiplier and limiter - chroma channel with color demodulator, ACC, color killer, color saturation multiplier, limiter and chroma multiplexer - user-adjustment of contrast, color saturation, hue etc. - sync separation section with sync slicer, horizontal PLL, vertical separation, vertical counter, horizontal decoder and vertical decoder, output pulse generation - clock generation on-Chip, or external clock.
Picture–in–Picture Processor PIP2250
The so–called picture–in–picture facility has been introduced
for the first time by ITT in 1977, using the UAA
1000 and SAA 3000 integrated circuits. Picture–in–picture
means the insertion of a second program’s picture
on the screen of a CTV receiver (at reduced size) simultaneously
with the full–size main picture. The second
small picture may originate from another TV transmitter,
from a video recorder, a monitor camera or another
source. It allows monitoring of the second channel while
watching the main channel. Main requirement for picture–
in–picture is to store the content of the small picture
when it is supplied by its source, and to deliver the content
at the proper instant when it must be inserted into
the main picture which is received and displayed continuously.
In the past, at the first attempts of picture–in–picture, the
memory for storing the content of the small picture was
analog, a bucket brigade MOS device, according to the
state of the art at this time. Today’s state of the art is digital:
ITT’s DIGIT 2000 system with its digital processing
of the video signals opens new possibilities for picture–
in–picture which are only feasible in a digital system. For
storing the content of the second, small picture, two
standard 64 K dynamic RAMs (16 K x 4) are used, thus
making the storage simple and economic. If it is intended
to store up to four small pictures, two 256 K DRAMs (64
K x 4) are required. Page mode must be provided in both
Today’s picture–in–picture fits neatly into ITT’s DIGIT
2000 system, but is also suitable for stand–alone applications.
1.1. General Description
The PIP 2250 Picture–in–Picture Processor is a fast signal
processor in CMOS technology which is used to filter
(for anti–aliasing) and to decimate the digital Y, R–Y and
B–Y signals supplied, e.g., by the VSP 2860 Video/Sync
Processor, to control the DRAMs for storing the small
picture’s content and for reading the same at the proper
time for display. Further, a border generator supplies the
borderline for the small picture. the PIP 2250 is housed
in a 68–pin PLCC package, and is compatible to the
DIGIT 2000 system of digital signal processors with respect
to signal levels as well as pin configuration, supply
voltage, clock frequency etc.
A coarse block diagram of the PIP 2250 is shown in Fig.
1–1. The input picture processing section receives the
digitized information of the small, second picture to be
inserted into the main picture, in the shape of the so–
called input YUV bus, from the VSP 2860 Video Sync
Processor or a similar source, together with the associated
clock, skew, horizontal and vertical blanking signals.
The DRAM interface gives the filtered and decimated
YUV and sync information to the DRAM for
storing till the proper instant for insertion into the main
picture has come. At this time, the DRAM’s content is
read and processed in the output picture processing
section, which receives its required clock, skew and
blanking signals from the main system into whose picture
the second small picture is intended to be inserted.
The output picture processing section supplies the small
picture’s content in the shape of the output YUV bus,
which is connected to the YUV bus supplied by the main
picture’s video processing section (Fig. 1–2). By means
of the ODOUT Outputs Disable signal supplied by the
PIP 2250 via pin 47, the main video section is disabled
during the time of the small picture.
Main features of the PIP 2250 Picture–in–Picture Processor
– digital video filters for anti–aliasing and data decimation
– control of the two DRAMs for storage of the small picture(
– control and supervision of the PIP 2250 via the IM bus
– full compatibility with the DIGIT 2000 system
The block diagram of the video section of a digital TV receiver
according to the DIGIT 2000 concept, which is
equipped with the picture–in–picture facility, is shown in
Fig. 1–2. Besides the well known DIGIT 2000 chip set,
shown in the upper part of Fig. 1–2, there is the section
for the second (small) picture. This section is composed
of the VAD 2150 Video A/D Converter, the VSP 2860
Video/Sync Processor, optionally a SECAM processor,
the PIP 2250 Picture–in–Picture Processor and two
2.3. Pin Descriptions
Pins 1, 19 and 51 – Ground
These pins must be connected to the negative of the
Pins 2 to 9 – A7 to A0 RAM Address Outputs (Fig. 2–11)
By means of these outputs, the external DRAMs are addressed.
Pins 10 to 17 – IO7 to IO0 RAM Data Inputs/Outputs
When writing the DRAMs, these pins are the data outputs,
and when reading the DRAMs, they act as data input.
Pins 18, 49 and 67 – VSUP Supply Voltage
This pins must be connected to the positive of the supply.
Pin 20 – CAS Column Address Strobe Output (Fig. 2–11)
This output supplies the column address strobe signal
for the external DRAMs.
Pin 21 – RAS Row address Strobe Output (Fig. 2–11)
This output supplies the row address strobe signal for
the external DRAMs.
Pin 22 – WE Write enable Output (Fig. 2–11)
This output supplies the write enable signal for the external
Pin 23 – FSIN Fast Switching Input (Fig. 2–2)
This input serves for enabling the analog RGB inputs.
Pins 24 to 26 – Analog RGB Inputs (Fig. 2–12)
Via these inputs, the PIP 250 receives analog RGB signals,
e.g. Teletext or video recorder (SCART), which are
fed to the analog RGB outputs to be given to the VCU.
Pins 27 to 29 – Analog RGB Outputs (Fig. 2–12)
these outputs either supply the analog RGB signals,
which have been received via the analog RGB input pins
24 to 26, to the VCU, or are the digital outputs for the
analog border (with CMOS level).
Pin 30 – FSOUT Fast Switching Output (Fig. 2–11)
This output supplies a switching signal for enabling the
analog RGB inputs of the VCU.
Pin 31 – C0 Chroma Output and Msync Input (Fig. 2–9)
This input/output, which, in its output function, can be
disabled by the CCU via the IM bus, on the one hand
supplies the LSB of the (R–Y) and (B–Y) digital color difference
signals, which are multiplexed on four lines, to
the VCU Video Codec for D/A conversion. On the other
hand, pin 31 acts as input for the Msync multiplex sync
signal when operating in the digital insertion mode.
Pins 32 to 34 – C1 to C3 chroma Outputs (Fig. 2–13)
These open–drain outputs, which can be disabled by the
CCU via the IM bus, supply the three LSBs of the (R–Y)
and (B–Y) digital color difference signals multiplexed on
four lines to the VCU Video Codec for D/A conversion.
Pin 35 – Reset Input (Fig. 2–3)
This input is used for hardware reset of the PIP 2250. At
Low level, reset is actuated, and at High level, the PIP
is ready for communication with the CCU.
Pins 36 to 43 – L0 to L7 Luma Outputs (Fig. 2–13)
These open–drain outputs which can be disabled by the
CCU via the IM bus, deliver the processed luminance
signal in a parallel 8–bit code to the VCU Video Codec
for D/A conversion.
Pin 44 – MSKEW Skew Data Input for digital insertion
Via this pin the PIP 2250 receives skew data for phase
adjustment of the video information, from the DPU 2553
or DPU 2554 Deflection Processor of the Main system.
MHBL Horizontal Blank Input for stand–alone operation
This signal is used internally for horizontal start and for
skew data measurement.
Pin 45 – MHVBIN Horizontal and Vertical blanking Pulse
Input for Main System or Vertical Blanking Pulse Input
for Stand–Alone Systems (Fig. 2–5).
Via pin 45, the PIP 2250 is supplied with the (sandcastled)
delayed horizontal and vertical blanking pulses
by pin 22 of the DPU 2553 or DPU 2554 Deflection Processor
of the Main system, or, with stand–alone solutions,
with the vertical blanking pulse of the Main system.
Pin 46 – IM Bus Port Output (Fig. 2–11)
The output level of this pin can be defined via the IM bus
using bit 3 in address 57.
Pin 47 – ODOUT VPU Outputs Disable Output (Fig.
This output must be connected to the outputs disable input
of the PVPU or CVPU Video Processor acting together
with the picture–in–picture system, in order to
disable the main picture during the time the second
small picture is displayed. The output signal of pin 47
has High level during the time the VPU’s outputs must
be disabled. During this time, the PIP’s luma and chroma
outputs are enabled. Vice versa, if pin 47 supplies Low
level, the PIP’s outputs are disabled and the VPU’s luma
and chroma outputs are enabled.
Pin 48 – Blocking Capacitor
for analog skew data measurement and analog delay of
RGB output, ODOUT and FSOUT.
Pin 50 – FM Clock Input (Fig. 2–6)
This pin receives the FM main clock signal for the main
picture from the MCU 2600 or MCU 2632 Clock Generator.
Pins 52 to 54 – IM Bus Connections (Figs. 2–3 and 2–10)
Via these pins, the PIP 2250 is connected to the IM bus
and communicates with the CCU.
Pin 55 – PHVBIN Horizontal and Vertical Blanking Pulse
Input from PIP System (Fig. 2–5)
Via pin 55, the PIP 2250 is supplied with the (sandcastled)
delayed horizontal and vertical blanking pulses
by the VSP 2860 Video/Sync Processor of the PIP system
or another suitable source.
Pin 56 – PSKEW Skew Data Input from PIP System (Fig.
Via pin 56, the PIP 2250 receives skew data for phase
adjustment of the video information, from the VSP 2860
Video/Sync Processor of the PIP system or another suitable
Pins 57 to 66 – L7 to L2 and C3 to C0 Luma and Chroma
inputs (Fig. 2–7)
Via these inputs, the PIP 2250 receives the digital luma
and chroma signals for the PIP small picture for the VSP
2860 Video/Sync Processor or another suitable source.
The luma signals are parallel in a 6–bit code, the chroma
signals in the shape (R–Y) and (B–Y), time multiplexed
on four lines.
Pin 68 – FP Clock Input (Fig. 2–6)
Via pin 68, the PIP 2250 receives the FP clock signal required
for the PIP small picture, form the VSP 2860 Video/
Sync Processor or another suitable source.
2.4. Pin Circuits
The following figures show schematically the circuitry at
the various pins. The integrated protection structures
are not shown. The letter “N” means N–channel, the letter
“P” P–channel, both enhancement mode.
3. Functional Description
As can be seen from Fig. 1–1, the PIP 2250 Picture–in–
Picture Processor is made up of four major functional
blocks; input picture processing, output picture processing,
DRAM interface and IM bus interface. For better understanding,
two features used in digital TV receivers
according to the DIGIT 2000 concept may be described
first: skew data and chroma timing synchronization.
3.1. Skew Data
The skew data signal produced by the DPU 2553 or similar
deflection processor or the VSP 2860 Video Sync
Processor is used to align the phase position of the video
signal in the PIP 2250, as shown in Fig. 2–20. The skew
data input is normally High, or at logic 1, when inactive.
At the horizontal start (start of each line), it becomes active
(Low) with a header code of 001 or 011 followed by
5 bits of luma skew data ( or 6 bits if 2H carry is included).
Thus the start of header code is defined as any 0 preceded
by 9 or more 1s.
Luma skew is defined as the phase or time difference
between the sampling clock and the analog horizontal
sync expressed in resolution of 1/32 of the sampling
clock period (Fig. 2–17). This phase difference changes
from line to line because the sampling clock frequency
may not be a multiple of the analog horizontal frequency.
As a result, digital samples on one line may not align vertically
with those from the adjacent lines. For signal processing
in the vertical direction, like in PIP input picture
processing, samples on each line must be interpolated
by the amount of skew so that corresponding samples
on different lines are aligned vertically.
Thus the skew data defines the horizontal start timing
and carries information about the amount of luma skew.
Notice the horizontal start is NOT derived from the horizontal
3.2. Chroma Timing Synchronization
The 4–bit chroma transfer on the YUV bus is time multiplexed
for R–Y and B–Y. There must be some scheme
to synchronize the timing. There are two schemes for
chroma timing synchronization: either for PAL and
NTSC, or for D2–MAC and SECAM.
For the PAL/NTSC scheme, bit 0 of chroma bus no longer
carries video information, but is used as a sync signal
for chroma timing synchronization during vertical blanking.
Using horizontal blanking as the basis for line count,
at the 4th line after vertical blanking trailing edge, chroma
bus bit 0 will be a string of 72 (negative pulses with
25 % duty cycle (Fig. 2–21). The negative pulses are
synchronized to the R–Y LSB timing of chroma bus (Fig.
2–18). In addition, it doubles as the clock for the transmission
of 72 bits of data for VCU control with data from
bit 3 of the chroma bus.
For the D2–MAC/SECAM scheme, chroma synchronization
occurs every horizontal line, again with chroma
bus bit 0 being a string of three 25 % cycle negative
pulses synchronized to the R–Y LSB chroma bus timing
(Fig. 2–16). The sync pulses start after the leading edge
of horizontal blanking and last for 12 clocks.
3.3. Input Picture Processing
The input picture processing block (Fig. 3–2) defines a
window for the input picture to be processed. Parameters
IHS, IVS and IVSI (Fig. 3–1) define the location and
size of this window. Samples within the window are reduced
by a factor of 1/3 in both horizontal and vertical direction,
for a reduction to 1/9 of the original picture size.
Input to the input picture processing is a digitized picture
in the form of an input YUV bus and timing/deflection signals,
as are skew data, horizontal blanking and vertical
blanking. They may come from the VSP 2860 Video/
Sync Processor or a similar source.
Because of the reduction in picture size described
above, internally only 5 bits resolution is needed for luma
(Y) and 6 bits for chroma (UV). This results in only 5 pins
for luma at the input YUV bus. However, four pins are still
needed for the multiplexed chroma bus even though
only 6 bits after demultiplexing are needed.
The border for the small picture may be either digital or
analog. The digital border is merged with the small picture
inside the PIP with digital correction for skew and
output with the small picture at output YUV bus. The
analog border is output at the FSOUT Fast Switching
Output pin as border timing pulses with time delay based
on skew added to the intrinsic delay (Fig. 3–6). Digital
border is an inherent part of the small picture while analog
border has to be merged with the small picture in the
VCU.Selection of digital/analog border is via bit 1 of register
44. For digital border, LSBs of register 41 to 43 define the
luma and chroma values while three MSBs of register 43
define eight different analog borders (see IM bus registers,
The FSIN Fast Switching Input (pin 23) can be used to
switch over the analog RGB outputs (pins 27 to 29) between
analog border (supplied by register 43) and external
RGB source connected to the analog RGB inputs
(pins 24 to 26). If FSIN is High, the analog RGB inputs
are connected to the analog RGB outputs. The RGB
switch (Fig. 3–6) can also be controlled by software via
IM bus register 57 (bit 1, “RGBE”). If RGBE = 1, the external
RGB source at pins 24 to 26 is connected to the
RGB outputs, pins 27 to 29. If analog border is selected
via IM bus register 44 (bit 1, “BDI” = 0), the 3–bit analog
RGB border of register 43 is switched to the analog RGB
outputs, pins 27 to 29; during the analog border timing
The priority of the external RGB source can be programmed
by IM bus register 57 (bit 6, “RGBP”). If RGBP
= 1, the priority of the analog RGB inputs and FSIN is
higher than the analog border. Figs. 2–22 to 2–25 illustrate
the timing waveforms of the ODOUT output and the
FSOUT output for different combinations of operating
mode and border selection.
A picture-in-picture television receiver is disclosed in which a television picture to be inset is compressed at a compression rate of 1/n and inset as a small-picture in part of a main television picture or large picture, and a single field memory for small-picture reproduction is provided therein in or from which a video signal can be randomly read and written line by line as a unit. In the single field memory is stored the small-picture video signal line by line by the application of a writing clock in which case the time taken in the writing is less than 1/(n+1) of a horizontal period. Then, from the memory is read the stored small-picture information by the application of a reading clock of n times the frequency of the writing clock during the time that writing is not performed, and supplied to be inset in the main television picture. A small-capacity buffer memory is provided at the prestage or following stage of the field memory to prevent the read/write timing overlap in the field memory irrespective of whether the small-picture and the main television picture are synchronized or not in the transmission systems. Thus, the capacity of the field memory essential for the small-picture is about a half of the conventional one.
Digit 2000 VLSI Digital TV System DIGIVISION ITT Intermetal Timing correction for a picture-in-picture television system:
System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses. A second phase measure is used to delay the clock signal used to display the small picture so that the clock pulses that define the edges of the small picture occurs with the same timing relative to the large picture horizontal synchronizing pulses form line-to-line.
1. In a video signal processing system including a source of first video signal having a periodic horizontal line synchronizing signal component and a memory for holding sampled data representing a second video signal, apparatus for processing said sampled data in synchronism with said first video signal comprising:
means coupled to said source for developing horizontal synchronizing pulses representing the horizontal line synchronizing signal component of said first video signal:
a terminal for applying a clock pulse signal wherein the occurrence of clock pulses possibly exhibits varying amounts of skew relative to said horizontal synchronizing pulses;
skew measuring means coupled to said clock signal terminal and responsive to said horizontal synchronizing pulses for generating a control signal corresponding to the difference in time, as a proper fraction of the period of said clock pulse signal, between the occurrence of a horizontal synchronizing pulse and a pulse of said clock signal;
means coupled to said clock signal terminal, for controlling the reading of the sampled data from said memory; and
skew correcting means coupled to said clock signal terminal, to said memory and to said skew measuring means for effecting a time displacement of the signal represented by the sampled data read from said memory, the magnitude of said time displacement being determined by said control signal.
2. The apparatus set forth in claim 1 wherein said skew correcting means comprises:
means coupled to said clock signal terminal and responsive to said control signal for effecting a time displacement of said clock signal to develop a skew corrected clock signal; and
means for applying said skew corrected clock signal to said means for controlling the reading of sampled data from said memory.
3. The apparatus set forth in claim 2 wherein:
said skew measuring means includes means for measuring the time interval between the center point of a pulse of said horizontal line synchronizing signal and a transition of the pulse of said clock signal which occurs in time immediately prior to said center point.
4. The apparatus set forth in claim 1 wherein said skew correcting means comprises:
means for generating samples corresponding to the sums of first and second consecutive samples read from said memory and scaled by respective first and second scale factors proportional to said control signal.
5. The apparatus set forth in claim 1 wherein said skew correcting means comprises:
means for scaling the values of first and second consecutive samples read from said memory by first and second mutually complementary scale factors proportional to said control signal; and
means for combining the first and second scaled samples to develop samples representing said time displaced signal.
6. In a video signal processing system including a source of first video signal having a horizontal line synchronizing component and a source of second video signal having a horizontal line synchronizing component, apparatus for processing said second video signal in synchronism with said first video signal comprising:
means coupled to said source of first video signal for developing first horizontal synchronizing pulses representing the horizontal synchronizing component of said first video signal;
means coupled to said source of second video signal for developing second horizontal synchronizing pulses representing the horizontal line synchronizing component of said second video signal;
a terminal for applying a clock pulse signal, wherein the occurrence of clock pulses possibly exhibits respectively different varying amounts of skew relative to said first and second horizontal sync pulses;
first skew measuring means coupled to said clock signal terminal and responsive to said second horizontal synchronizing pulses for generating a first control signal corresponding to the time difference between the occurrence of one of said second horizontal synchronizing pulses and a pulse of said clock pulse signal;
first skew correcting means responsive to said first control signal and coupled to said sampling means for modifiying the values of samples provided thereby to effect a time displacement of the signal represented by said samples, the magnitude of said time displacement being determined by said first control signal;
memory means coupled to said skew correcting means for storing samples representing said time displaced second signal;
second skew measuring means responsive to said clock signal and to said first horizontal synchronizing pulses for generating a second control signal corresponding to the time difference between the occurrence of one of said first horizontal synchronizing pulses and a pulse of said clock signal;
means coupled to said clock signal terminal for controlling the reading of the sampled data from said memory means; and
second skew correcting means coupled to said clock signal terminal, to said memory and to said skew measuring means for effecting a time displacement of the signal represented by the sampled data read from said memory, the magnitude of said time displacement being determined by said second control signal.
7. The apparatus set forth in claim 6 wherein said second skew correcting means comprises:
means coupled to said clock signal terminal and responsive to said second control signal for effecting a time displacement of said clock signal to develop a skew corrected clock signal; and
means for applying said skew corrected clock signal to said means for controlling the reading of sampled data from said memory.
8. The apparatus set forth in claim 6 wherein said second skew correcting means comprises:
means for generating samples corresponding to the sums of first and second consecutive samples read from said memory and scaled by respective first and second scale factors proportional to said second control signal.
9. The apparatus set forth in claim 6 wherein said second skew correcting means comprises:
means for scaling the values of first and second consecutive samples read from said memory by first and second mutually complementary scale factors proportional to said second control signal; and
means for combining the first and second scaled samples to develop samples representing said time displaced signal.
10. The apparatus set forth in claim 6 wherein:
said first skew measuring means comprises means for measuring the time interval, as a proper fraction of a period of said clock signal, between a predetermined point on a pulse of said second horizontal line synchronizing signal and a transition of a pulse of said clock signal which is adjacent in time to said predetermined point; and
said second skew measuring means comprises means for measuring the time interval, as a proper fraction of a period of said clock signal, between a predetermined point on a pulse of said first horizontal line synchronizing signal and a transition of a pulse of said clock signal which is adjacent in time to said predetermined point.
11. The apparatus set forth in claim 10 wherein said first skew correcting means includes means for scaling the values of first and second consecutive samples representing said second signal by a factor proportional to said first control signal and by a factor proportional to the complement of said first control signal respectively and means for adding the first and second scaled samples to develop a first sample representing said time displaced signal. 12. In a picture-in-picture television display system including a source of first video signal having a periodic horizontal line synchronizing signal component and a source of second video signal having a periodic horizontal line synchronzing signal component, apparatus for processing said second video signal in synchronism with said first video signal comprising:
means including a memory for processing said second video signal to develop sampled data in said memory representing said second video signal;
a terminal for applying a clock pulse signal wherein the occurrence of pulses of said clock signal possibly exhibits varying amounts of skew relative to the horizontal synchronizing pulses of said first video signal;
skew measuring means coupled to said clock signal terminal and responsive to said horizontal synchronizing pulses of said first signal for generating a control signal corresponding to the amount time, as a proper fraction of the period of said clock signal, between the occurrence of a horizontal synchronizing pulse and a pulse of said clock signal;
skew correcting means coupled to said clock signal terminal and responsive to said control signal for effecting a time displacement of said clock signal to develop a skew corrected clock signal:
means coupled to said skew correcting means and to said memory for extracting the sampled data therefrom in synchronism with said skew corrected clock signal; and
multiplexing means coupled to said sampled data extracting means and to said source of first video signal for selectively providing signals from said source of first video signal and from said memory to a display device.
13. The apparatus set forth in claim 12 wherein:
said skew measuring means includes means for measuring the time interval between a predetermined point on a pulse of said horizontal line synchronizing signal and a transition of the pulse of said clock signal which occurs immediately prior to said predetermined point; and
said skew correcting means includes means for delaying said clock signal by an amount of time approximately equal to said time interval to develop said skew corrected clock signal.
14. The apparatus set forth in claim 12 wherein said means for processing said second video signal comprises:
means coupled to said source of second video signal for developing further horizontal synchronizing pulses representing the horizontal line synchronizing signal component of said second video signal;
means coupled to said source of second video signal for developing samples representing said second video signal at instants in time determined by said clock signal;
further skew measuring means coupled to said clock signal terminal and responsive to said further horizontal synchronizing pulses for generating a further control signal corresponding to the amount of time, as a proper fraction of the period of said clock signal, between the occurrence of a further horizontal sync pulse and a pulse of said clock signal;
further skew correcting means coupled to said sample developing means and to said clock signal terminal and responsive to said further control signal for effecting a time displacement of the signal represented by the samples provided by said sample developing means;
means coupled to said further skew correcting means for applying selected ones of the samples provided thereby to said memory.
15. The apparatus set forth in claim 14 wherein,
said second video signal may include a color synchronizing burst signal component; and
the clock pulse signal applied to said clock terminal is synchronized in frequency and phase to said color synchronizing burst signal component.
16. The apparatus set forth in claim 14, wherein:
said first and second video signals include respective first and second chrominance signal components including respective first and second color synchronizing burst signal components;
the clock pulse signal applied to said clock terminal is synchronized in frequency and phase to said first color synchronizing burst signal component;
the chrominance signal components of the samples provided by said sample providing means tend to have phase errors relative to the samples which would be provided if the clock signal were locked in frequency and phase to the second color synchronizing burst signal component; and
means coupled to said sample providing means and responsive to said second color synchronizing burst signal component for substantially correcting said phase errors.
17. In a picture-in-picture television display apparatus including a source of first video signal having a periodic horizontal line synchronizing component, means for applying a clock pulse signal wherein the occurrence of clock pulses may exhibit varying amounts of skew relative to said horizontal line synchronizing component, a memory for holding sampled data representing a second video signal, means for displaying the image represented by said first video signal and means for reading the sampled data from said memory and for displaying the image represented by said samples as an inset in the image represented by said second video signal, wherein the improvement comprises:
skew measuring means responsive to said clock signal and to said horizontal synchronizing pulses for generating a control signal corresponding to the difference in time, as a proper fraction of the period of said clock signal between the occurrence of a horizontal synchronizing pulse and a pulse of said clock signal; and
skew correcting means responsive to said clock signal and coupled to said memory and to said skew measuring means for effecting a time displacement of the sampled data read from said memory, the magnitude of said time displacement being determined by said control signal.
The timing errors relevant to the present invention occur when either the primary or secondary signal is a nonstandard signal. As used in this application, the term nonstandard signal means a video signal having a horizontal line period which may vary in width by, for example, 4 ns or more from the horizontal line period set by the signal standard to which the video signal nominally conforms (e.g. NTSC, PAL, or SECAM).
To understand how these timing errors may affect the inset image, it is helpful to know how the secondary signal is processed and displayed. In a conventional PIP display system, the secondary signal is sampled at instants determined by a sampling clock signal which, desirably, bears a fixed relationship to the horizontal line scanning frequency of the secondary signal. To aid separation of the luminance and chrominance components of color television signals, the sampling clock signal has a frequency that is a multiple of the chrominance subcarrier frequency which is itself a harmonic of one-half the horizontal line scanning frequency. This sampling clock signal may be developed by a phase locked loop which locks the clock signal to the color reference burst component of the composite video signals.
The secondary signals are separated into their component parts, generally a luminance signal and two color difference signals, and then subsampled both vertically and horizontally to develop signals which represent a reduced-size image. The lines of samples taken during one field of the secondary signal are stored in a memory. These samples are then read from the memory for display using a clock signal which is desirably related to the horizontal line scanning frequency of the primary signal.
When the secondary signal originates from a video tape recorder (VTR), video disk player or home computer, the frequency of the color burst signal may be relatively stable while the frequency of the horizontal line scanning signal may vary significantly from line to line. This variation may be caused by stretching of the tape, defects in the disk, motor speed variations in either the VTR or disk player, or inaccuracies in the frequencies used by the home computer. Since the sampling clock signal is locked to the burst signal, corresponding sampling points on successive lines may be shifted or skewed relative to each other. When these lines of samples are displayed in synchronism with the primary signal, the corresponding samples do not line up vertically. Consequently vertical lines in the inset image may appear jagged, if the timing errors randomly change the period of the horizontal sync signal, or tilted if there is a fixed error in the horizontal sync period. Assuming a 3:1 reduction in the secondary image, a timing difference of 12 ns or more in successive horizontal line periods of the secondary signal may produce noticeable skew distortion in the inset image.
Timing errors in the primary signals change the relative time difference between primary horizontal sync pulses, which define the edges of the primary image, and the first samples in lines of the inset image. Primary signal timing errors that cause the periods of successive horizontal sync pulses to vary from the applicable signal standard by 4 ns or more may produce noticeable skew distortion in the inset image. This distortion causes the entire inset image to appear jagged or tilted.
To gain a better understanding of skew and the methods which may be used to compensate for it, consider the waveforms shown in FIG. 1. The waveform A represents a portion of one horizontal line of, e.g. luminance signal, including the horizontal synchronizing pulse (note the waveforms of FIG. 1 are not drawn to scale). Waveforms B, C and C' represent sampling (system) clock waveforms. The pulses of waveform B are assumed to occur at the points in time that a subcarrier locked clock, locked to a standard signal, would occur. Put another way, if waveform A corresponds to n lines of an image, then waveform B represents the desired sampling (system) clock for each successive line, i.e. without skew. A clock signal having constant skew may also be desirable. In either a zero skew or a constant skew system, the sampling clock pulse r always occurs at the same point in time relative to the HSYNC pulse. This point in time is represented by the sample S2 on waveform A. Waveform C represents a subcarrier locked clock which exhibits a degree of skew. The number of pulses per line period contained in waveform C may not be constant from line-to-line. Generally, the difference in the number of whole clock pulses in a line period can be compensated for in the phase locked loop which generates the horizontal synchronizing signal. The sampling phase error (skew) which is a fractional portion of a clock period, however, may only be corrected by operation on the samples themselves or on the sampling clock signal.
One method of correction is to adjust the sample values on a line-by-line basis so that the adjusted samples conform to samples that would be taken by a clock with zero skew or with some constant skew. For example, the sample values generated by the clock signal of waveform C may be adjusted to equal or approximate corresponding sample values that would be generated by the clock signal of waveform B. In the FIG. 1, clock pulse r' of waveform C is assumed to correspond to clock pulse r of waveform B. Clock pulse r' is advanced in time or skewed by one-half of one clock period, TS, with respect to clock pulse r. Clock pulse r' generates a sample value S1. Desirably, clock pulse r' should occur coincident with clock pulse r and generate the sample value S2.
Replacing the sample taken coincident with clock pulse r' with a sample having a value approximately equal to S2 effectively advances the timing of the signal taken with the sampling clock signal C so that it matches the signal which would have been taken had the zero-skew sampling clock signal B been used. Neglecting the complications of chrominance decoding, an alternative method of skew correction is to adjust the phase of the sampling clock signal on a line-by-line basis so that it approximately matches the phase of the desired clock signal B or some other clock signal which exhibits equal skew from line to line. The waveform C' represents the clock signal C delayed an amount of time substantially equal to the skew. Samples taken with this delayed clock signal approximate samples taken with the desired clock signal, B.
The first skew correction method may be used to correct skew errors in the secondary signal since it does not affect the phase of the sampling clock signal. It is recalled that the phase of this clock signal cannot be changed without affecting the processing of the secondary chrominance signal components. The second skew correction method may be used to compensate for skew errors in the primary signal when the samples representing the separated luminance and color difference signal components of the secondary image are retrieved from the secondary field memory for display.
SUMMARY OF THE INVENTION
The present invention is embodied in apparatus which compensates for timing errors in a first video signal relative to a second, stored video signal. This apparatus includes circuitry for measuring the time interval between a horizontal synchronizing pulse of the first signal and a pulse of the clock signal which controls the retrieval and display of the second signal. The apparatus further includes circuitry with changes the timing of the second signal relative to the horizontal sync component of the first signal, as the second signal is displayed, to compensate for any variations in the measured time intervals from line-to-line.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a timing diagram useful in describing skew and methods of skew correction.
FIG. 2 is a block diagram of a PIP television display system incorporating the present invention.
FIG. 3 is a block diagram of a digital PIP television display system incorporating the present invention.
FIGS. 4 and 5 are a block diagrams showing skew correction circuitry which may be used in the display devices shown in FIGS. 2 and 3.
FIG. 6 is a block diagram of alternative skew correcting apparatus which may be used in the display devices shown in FIGS. 2 and 3.
DETAILED DESCRIPTION OF THE INVENTION
In the drawings, broad arrows represent busses for multiple-bit parallel digital signals and line arrows represent connections carrying analog signals or single bit digital signals. Depending on the processing speed of the devices, compensating delays may be required in certain of the signal paths. One skilled in the art of digital signal processing circuit design would know where such delays would be needed in a particular system.
FIG. 2 is a block diagram of a PIP display device in which the primary signal is processed using conventional analog apparatus and the secondary signal is processed digitally. This circuitry uses a single clock signal, synchronized to the secondary burst signal, both for sampling and processing the secondary signal and for displaying the secondary image as an inset in the main image.
A source of primary composite video signals 10 applies the primary video signals to a Y/C separation filter 12. Filter 12, which may include conventional low-pass and high-pass filters, separates the composite video signals into primary luminance signals, YP, and primary chrominance signals Cp. The primary luminance and chrominance signals are applied to a primary chroma/luma processor 14 which may include, for example, band shaping filters for peaking the high frequency components of the luminance signals to develop a signal Y'P and a chrominance signal demodulator for deriving the baseband color difference signals (R-Y)P and (B-Y)P from the primary chrominance signals, CP. The signals Y'P, (R-Y)P, and (B-Y)P applied to a matrix 16 which combines the signals to develop the color signals RP, GP and BP. These signals are applied to one set of signal input terminals of an analog multiplexer 26, the output of which drives a cathode ray tube (CRT) 28. The color signals RS, GS and BS developed from the secondary signal are applied to a second set of signal input terminals of the multiplexer 26. These signals are developed by apparatus described below.
A source of secondary composite video signals 50, which may include the tuner, IF amplifier and video detector of a conventional color television receiver, provides secondary composite video signals to an analog-to-digital converter (ADC) 52. ADC 52 samples and digitizes the secondary composite video signals at instants determined by the sampling clock signal CK. A phase-locked-loop (PLL) 56, described below, generates the signal, CK, which has a frequency 4fc substantially equal to four times the chrominance subcarrier frequency, fc. The signal CK is phase locked to the color synchronizing burst component of the secondary video signals.
ADC 52 provides digitized secondary video signals to a Y/C separation filter 54. Filter 54 may be a conventional digital filter having a clock input terminal coupled to receive the signal CK. Filter 54 may include, for example, an FIR filter which passes the chrominance signal components of composite video signal to the relative exclusion of luminance signal components and a subtracter for subtracting the chrominance signal components from the composite signal to develop luminance signal components.
The clock signal CK is applied to the skew measuring circuitry 59. Exemplary skew measuring circuitry 59 accumulates the fractional part of the horizontal skew period values, HSP, provided by the sync separator circuitry 58 to develop a secondary skew signal, SSK. The integer part of the signal SSK is fed back to the sync separator circuitry 58, where it is used in the phase-locked-loop to update the horizontal sync period measurement. The fractional part of the signal SSK is retained in the accumulator of the skew measuring circuitry 59 and applied as skew values to the skew correcting circuitry 62. As used in the present embodiment, the fractional part of the signal SSK represents the time interval between the center of the respective phase locked horizontal sync pulse and the leading edge of the clock pulse which occurs immediately before the center of the respective horizontal sync pulse. This interval is measured with a resolution substantially equal to one-sixteenth of the period of the signal CK. The sync separator circuitry 58 and the skew measuring circuitry 59 are of the type contained in the integrated circuit DPU 2532 manufactured by ITT Intermetall GmbH and which is described at pages 47-72 of the data book "Digit 2000 NTSC Double-scan VLSI Digital TV System" edition 1985/5 of ITT Intermetall, Freiburg, W. Germany.
Exemplary skew error correcting circuitry 62 is shown in FIG. 4. This circuitry interpolates between successive input samples to provide output samples that are substantially equivalent to the samples which would have been taken synchronous with a sampling clock signal having zero skew. The circuitry shown in FIG. 4 may be divided into two parts, a linear interpolator and a correction circuit. Luminance samples YS are applied to a delay element 410, which delays the samples by one period of the clock signal CK. The delayed samples are applied to a multiplier 412 which scales the samples by a factor K. The factor K may be a value between zero and one and is provided by a read only memory (ROM) 424 in response to the secondary skew signal SSK. Luminance samples YS are also applied to a multiplier 414 which scales these undelayed samples by a factor 1-K, also provided by ROM 424. The samples provided by the multipliers 412 and 414 are summed in adder 416.
The samples provided by adder 416 are linearly interpolated samples. If the frequency components of the sampled signals YS are an order of magnitude or more lower than the sampling frequency, the apparent delay of the interpolated samples is given by the product KTS, where TS is the period of the sampling clock signal CK. As the frequency components of the sampled signals approach the sampling frequency, however, the amount by which Ys appears to have been delayed becomes a function of the levels of its higher frequency components as well as of K. The correction circuit, which includes filter 422, multiplier 428 and adder 420 compensates for the frequency induced delay components. Luminance signals YS are applied to the filter 422 which has the transfer function T422 =-1+Z-1 +Z-2 -Z-3 expressed in Z transform notation. The samples provided by filter 422 are scaled by a factor C in multiplier 428. The factor C is provided by ROM 424 in response to the secondary skew signal, SSK. The samples developed by adder 416 are applied to a delay element 418 which compensates for the processing time through filter 422. These delayed samples are then added to the samples from multiplier 428 by an adder 420.
The combination of the linear interpolator and the correcting filter produce signals having an apparent delay of (1+K)Ts where the signals to be delayed have components with frequencies as high as one-third of the frequency of the sampling clock signal. In the NTSC system, for example, where the sampling clock frequency is approximately 14.3 MHz this skew correcting circuit provides uniformly spaced delays for luminance signals which may have frequency components up to 4.2 MHz. I defines the contents of ROM 424 to achieve delay steps of one-sixteenth of a sampling clock period.
|DELAY TOTAL SSK K 1-K C CHANGE DELAY|
15 1/16 15/16 1/32 TS /16
14 2/16 14/16 1/32 2TS /16
13 3/16 13/16 2/32 3TS /16
12 4/16 12/16 2/32 4TS /16
11 5/16 11/16 2/32 5TS /16
10 6/16 10/16 3/32 6TS /16
9 7/16 9/16 3/32 7TS /16
8 8/16 8/16 3/32 8TS /16
7 9/16 7/16 3/32 9TS /16
6 10/16 6/16 3/32 10TS /16
5 11/16 5/16 3/32 11TS /16
4 12/16 4/16 2/32 12TS /16
3 13/16 3/16 2/32 13TS /16
2 14/16 2/16 1/32 14TS /16
1 15/16 1/16 1/32 15TS /16
0 1 0 0 TS 2TS
The luminance samples from skew correcting circuitry 62 and the chrominance samples from delay element 63 are applied to a secondary chroma/luma processor 64. Processor 64 may include, for example, an FIR band shaping filter for peaking the frequency spectrum of the digital luminance signals to provide a modified secondary luminance signal YS ' and a digital chrominance demodulator for developing samples which represent the baseband secondary color difference signals (R-Y)S and (B-Y)S.
The signals YS ', (R-Y)S and (B-Y)S are applied to PIP field memory 68 where they are subsampled and stored under control of the write address generator circuitry 70. Memory 68 may be a conventional random access memory having a sufficient number of storage cells to hold one field of the subsampled secondary signal. This memory may be organized as three separate field memories, one for the luminance signal and one for each of the two color difference signals, or it may be organized as a single field memory with the sampled luminance and color difference signals combined into a single sampled signal. For example, these signals may be combined by alternately concatenating samples of the two color difference signals to samples of the luminance signal.
Data from the secondary chroma/luma processor 64 is written into the field memory 68 under control of the memory address generator circuity 70. The circuitry 70 develops write address signals, WADDR, and other control signals WCS, as may be needed from the clock signal CK, and the secondary vertical and horizontal sync signals SVS and SHS respectively. The write address generator circuitry 70 operates to subsample the secondary signal in, for example, a three-to-one ratio both vertically and horizontally by providing address values and control signals for the memory 68 at appropriate times.
Samples representing lines of the subsampled secondary image are read from the PIP field memory 68 under control of the read address generator circuitry 24. The signals applied to circuitry 24 are the primary vertical and horizontal sync signals, PVS and PHS respectively, and a skew corrected clock signal CK'. The circuitry 24 may for example, count pulses of the horizontal sync signal, PHS, relative to the vertical sync pulses, PVS, and pulses of the signal CK' relative to the primary horizontal sync pulses to determine when to initiate read operations for the memory 68 and when to switch the multiplexer 26 between providing primary and secondary drive signals to the display device 28. Read address generator 24 provides a read address signal, RADDR, and read control signals RCS, to the field memory 68 and a primary/secondary image selection signal, P/S to the multiplexer 26.
The write address generator circuitry 70, read address generator circuitry 24 and field memory 68 are not a part of the present invention and, so, are not described in detail. Exemplary circuitry for subsampling, storing, and retrieving the signal which produces the insert image is described in the U.S. Pat. Nos. 4,249,213 entitled "Picture-in-Picture Television Receiver" and 4,139,860 entitled "Television Receiver Equipped for Simultaneously Showing Several Programs" which are hereby incorporated by reference.
The Read address generator 24, it is recalled, operates in synchronism with the skew corrected clock signal CK'. This signal is generated as follows. Primary composite video signals from source 10 are applied to an ADC 17 which is clocked by the signal CK provided by the PLL 56. ADC 17 applies the sampled primary composite video signals to a DPU 20. DPU 20, which includes sync separator 18 and skew measuring circuitry 19 may be identical to the DPU 60 described above. The sync separator 18 develops the primary vertical sync signal, PVS, and the primary horizontal sync signal, PHS, from the primary composite video signals. The signal PHS, the horizontal sync period value HSP, and the clock signal CK are applied to the skew measuring circuitry 19. Circuitry 19 is functionally identical to the skew measuring circuitry 59 described above. It measures the time difference between the center of each pulse of the signal PHS and the leading edge of the immediately preceding pulse of the clock signal CK. The fractional part of the signal, PSK, provided by the skew measuring circuitry 19 is a four bit value indicating the skew for each primary horizontal scan line in units of one-sixteenth of the period of the clock signal CK. The integer part of the signal PSK is applied to the sync separator 18 as set forth above in reference to DPU 60. The fractional part of the signal PSK and the signal CK are applied to the skew correcting circuitry 22. Circuitry 22 may be a programmable delay element similar to that shown in FIG. 5.
In FIG. 5, the clock signal CK is applied to the input termnal of an inverter I1 which is the first inverter in a chain of thirty series-connected inverters. The inverter chain is organized as fifteen pairs of inverters, I1 and I1 ' through I15 and I15 '. The input terminal to the inverter I1 and the output terminals of all of the pairs, i.e. I1 ', I2 ' . . . I15 ' are connected to respectively different data input terminals of the multiplexer 500. The control input port of multiplexer 500 is coupled to receive the fractional part of the primary skew signal, PSK, provided by the skew measuring circuitry 19. Each pair of inverters in the chain has a signal propogation delay of approximately one-sixteenth of the period of clock signal CK so the output terminals of each of the pairs provide clock signals delayed by between one-sixteenth and fifteen-sixteenths of a clock period. The multiplexer 500 is conditioned by the fractional part of the signal PSK to provide, as its output signal CK', the signal CK when PSK is zero, the signal at the output terminal of inverter of I1 ' when PSK is one, the signal at the output terminal of inverter I2 ' when PSK is two, and so on, providing the signal at the output terminal of inverter I15 ' when PSK is fifteen. Accordingly, the signal CK' provided by the skew correcting circuitry 22 is a clock signal CK delayed by an amount of time approximately equal to the value of the fractional part of PSK times one-sixteenth of the period of the signal CK. As set forth above, in reference to FIG. 1, this signal is a skew corrected clock signal, which is to say a clock signal aligned with the horizontal sync signal PHS from line-to-line.
The samples provided by the memory 68 in synchronism with the skew corrected clock signal CK' are applied to a digital-to-analog converter (DAC) 72 which is clocked by the skew corrected clock signal CK'. DAC 72 provides analog signals representing the secondary luminance and (R-Y) and (B-Y) color difference signals to the matrix 74. Matrix 74 is a conventional analog matrix which converts secondary luminance and color difference signals into the color signals RS, GS, and BS for application to the multiplexer 26 as set forth above.
The analog multiplexer 26 is controlled by the image selection signal P/S provided by the read address generator 24 to apply either primary or secondary signals to the display device 28 to develop composite PIP images.
FIG. 6 is a block diagram showing aternative circuitry to correct for skew in the primary signal. This embodiment uses an interpolation scheme which is the same as is used to correct for the skew of the secondary signal. The read address generator circuitry 24' is clocked by the signal CK but is otherwise the same as the circuitry 24 described in reference to FIG. 2. From the clock signal CK and the primary horizontal and vertical sync signals PHS and PVS, read address generator circuitry 24' develops the read address signal RADDR and the read control signals RCS which control the reading of the subsampled secondary luminance and color difference signals from the PIP field memory 68. The luminance samples, Yss, are applied to skew correcting circuitry 22' which is responsive to the fractional part of the signal PSK. Circuitry 22' may be identical to the skew correcting circuitry 62 described above in reference to FIG. 2. Circuitry 22' interpolates between successive ones of the samples Yss to provide samples having values representing a signal delayed by the skew value. In other words, substantially the same signal as would be represented by the samples read from the memory in synchronism with a skew corrected clock signal. The luminance samples developed by the skew correcting circuitry 22' are applied to a DAC 72'. The (R-Y) and (B-Y) color difference samples provided by the field memory 68' are applied to the DAC 72' via the compensating delay elements 602 and 604 respectively. Delay elements 602 and 604 compensate for processing delay in the skew correcting circuitry 22'. As set forth in reference to the skew correcting circuitry 62, only the luminance signals need skew correction since the eye is less sensitive to changes in color than to changes in brightness. Nonetheless, it is contemplated that the delay elements 602 and 604 may be replaced by skew correcting circuitry similar to the circuitry 22' if skew correction of the color difference samples is found to be desirable. The DAC 72' is clocked by the uncorrected clock signal CK but is otherwise the same as the DAC 72 described with reference to FIG. 2. DAC 72' provides analog luminance and color difference signals representing the reduced secondary signal to the matrix 74.
FIG. 3 is a block diagram of an alternative embodiment of the invention in which both the primary and secondary signals are processed digitally. A single clock signal, PCK, which is phase locked to the primary color synchronizing burst signal, is used for both the primary and secondary processing circuitry. Since the secondary signals are sampled by a clock which is not phase locked to the secondary color burst signal, this embodiment of the invention includes circuitry to adjust the phase of the secondary chrominance signals to ensure proper color reproduction.
In the PIP system shown in FIG. 3, analog composite video signals from a source of primary composite video signals 310 are applied to an ADC 317. ADC 317 is responsive to the primary burst locked clock signal PCK to provide digital samples representing the analog primary video signals. These samples are applied to a Y/C separation filter 312 and to the DPU 320. DPU 320 is, for example, identical to the DPUs 20 and 60 described above. It provides the primary vertical and horizontal synchronization signals, PHS and PVS, a primary burst gate signal, PBG, and a signal, PSK, representing the skew of the clock signal, PCK, relative to the primary horizontal sync signal, PHS, as a proper fraction of the clock period. The Y/C separation filter 312, which may be identical to the filter 54, separates the luminance and chrominance components from the primary composite video signals.
The primary chrominance signals from filter 312 and the burst gate signal PBG from sync separator 318 are applied to the PLL 321. PLL 321, which may contain circuitry identical to that used by the PLL 56, generates the clock signal PCK having a frequency of substantially 4fc that is phase-locked to the color burst component of the primary signal.
The primary luminance and chrominance signal components are applied to the primary chroma/luma processor 314. Chroma/luma processor 314 provides processed luminance signals and (R-Y) and (B-Y) color difference signals to the DAC 315. DAC 315 converts the digital luminance and color difference signals into analog form and applies the analog signals to an RGB matrix 316. Matrix 316 develops the red, green, and blue color signals which represent the primary image, and applies them to a first set of signal input terminals of a multiplexer 326. Multiplexer 326, selects between the color signals representing the primary image and color signals representing the secondary image, which are applied to a second set of signal input terminals, to drive the display device 328. Apparatus which generates the color signals for the secondary image and which generates the selection signal, P/S, for the multiplexer 326 is described below.
Analog composite video signals from a source of secondary composite video signals 350 are applied to an ADC 352. ADC 352 is responsive to the primary sampling clock signal PCK for providing samples representing secondary composite video signals to the Y/C separation filter 354 and to the DPU 360. DPU 360, for example, is identical to the DPUs 20 and 60 described above. It provides the secondary horizontal and vertical synchronization signals, SHS and SVS respectively, a secondary burst gate signal SBG, and a signal, SSK, representing the skew of the clock signal PCK relative to the secondary horizontal sync signal SHS as a proper fraction of the clock period.
Y/C separation filter 354, separates the secondary composite video samples into a luminance signal component and a chrominance signal component. The luminance signal component and the signal SSK from skew measuring circuitry 359 are applied to skew correcting circuitry 362. The circuitry 362 may be identical to the circuitry described with reference to FIG. 4. It produces luminance samples having equal skew from line-to-line relative to the secondary horizontal sync signal SHS. These samples are applied to the secondary chroma/luma processor 364. The chrominance samples from filter 354 are applied to the processor 364 via the delay element 363. Delay element 363 compensates for the processing delays incurred by the luminance samples in the skew correction circuitry 362 by delaying the chrominance samples by two sample periods.
The secondary luma/chroma processor 364 processes the luminance signal and demodulates the chrominance signal into two quadrature phase related color difference signals. In this instance, however, the color difference signals provided by the processor 364 may not be (R-Y) and (B-Y) signals. The demodulator in the chroma/luma processor 364 will provide (R-Y) and (B-Y) signals only when the sampling clock signal has a frequency of 4fc and is phase locked to the color burst component of the secondary signal. In this embodiment, the sampling clock signal used to develop the secondary samples is phase locked to the primary color burst component. Since the primary and secondary signals may be from different sources, there may be phase and frequency differences between their respective color burst signals. Consequently, there may be phase errors in the demodulated color difference signals provided by the processor 364 relative to the (R-Y) and (B-Y) phases of the secondary signal. The present embodiment includes chrominance phase error correction circuitry 365 to detect and correct phase errors in the color difference signals provided by processor 364. This circuit is not a part of the present invention. Suitable circuitry 365 may be built by one skilled in the art from the teachings of the patent application Ser. No. 567,190 entitled "A Digital Video Signal Processing System Using Asynchronous A-to-D Encoding", which is hereby incorporated by reference. Briefly, the circuitry 365 converts the two color difference signals into a phase angle signal and an amplitude signal. The phase signal is compared against a reference phase during the secondary burst interval. The difference between the burst phase and the reference phase is used to correct the phase and amplitude signals in a closed loop control system. The corrected phase and amplitude signals are then processed to develop at least two color difference signals (e.g. (R-Y) and (B-Y)).
The phase corrected color difference signals provided by the circuitry 365 and the luminance signal provided by processor 364 via compensating delay element 367 are applied to the PIP field memory 368. The PIP field memory 368, memory write address generator circutry 370 and memory read address generator circuitry 324 may be similar to the respective field memory 68, and memory write and read address generator circutry 70 and 24 of FIG. 2. The circuitry 370 and 324 are responsive to the clock signal PCK and skew corrected clock signal PCK' respectively, but otherwise operate identically to the circuitry described above.
The skew corrected clock signal PCK' is developed by the skew correction circuitry 322. Circuitry 322, which may be similar to the circuitry 22, delays the clock signal PCK by the measured skew value times one-sixteenth of the period of PCK, to produce a skew corrected clock signal PCK'. It is contemplated that circuitry similar to that shown in FIG. 6 may be used in place of the skew correcting circuitry 622 to correct for the skew of the primary signal.
The samples provided by the PIP field memory 368 under control of the memory output address and timing control circuitry are applied to a DAC 372. DAC 372, synchronous with the skew corrected clock signal PCK', develops analog luminance and (R-Y) and (B-Y) color difference signals representing the secondary image and applies these samples to the matrix 374. Matrix 374 converts these luminance and color difference signals into red, green and blue color signals. These color signals, which represent the secondary image, are applied to the second set of signal input terminals of the analog multiplexer 326 as described above.
Although the embodiments described above use digital processing circuitry and use random access memory for the field store, it is contemplated that similar skew correction circuitry could be used with analog sampled data signals and that analog or digital shift register memories could be used for the field store.
This invention relates generally to digital television receivers and, particularly, to digital television receivers arranged for economical interfacing with a plurality of auxiliary devices.
With the proliferation of low cost microprocessors and microprocessor controlled devices, television (TV) receivers are being designed to utilize digitized signals and controls. There are many advantages associated with digital TV receivers, including uniformity of product, precise control of signal parameters and operating conditions, elimination of mechanical switches and a potential for reliability that has been heretofore unknown. Digital television receivers include a high speed communication bus for interconnecting a central control unit microprocessor (CCU) with various TV function modules for processing a TV signal. These modules include a deflection processing unit (DPU), a video processing unit (VPU), an automatic phase control (APC), a video codec unit (VCU), an audio analog to digital converter (ADC) and an audio processing unit (APU). The CCU has associated with it a non-volatile memory, a hardware-generated clock signal source and a suitable interface circuit for enabling the CCU to control processing of the TV signal throughout the various TV function modules. The received TV signal is in analog form and suitable analog to digital (A/D) converters and digital to analog (D/A) converters are provided for converting the digital and analog signals for signal processing and for reconverting them after processing for driving a cathode ray tube (CRT) and suitable speakers. The CCU microprocessor is heavily burdened because of the high speed timing required to control the various TV function modules.
To further complicate matters, modern TV receivers are increasingly being used with auxiliary devices for other than simple processing of TV signals. For example, the video cassette recorder (VCR) has enabled so-called "time-shifting" of program material by recording TV signals for later, more convenient viewing. The VCR is also extensively used with prerecorded material and with programs produced by users having access to a video camera. Other auxiliary devices providing features such as "Space Phone" whereby the user is enabled to make and receive telephone calls through his TV receiver, are desirable options. Additionally, a source selector auxiliary device enables a host of different signal sources, such as cable, over-the-air antenna, video disk, video games, etc. to be connected for use with the signal processing circuitry of the TV. In addition, all of these many auxiliary devices are preferably controllable from a remote position. A great deal of flexibility is available since each of the above auxiliary devices includes a microprocessor for internally controlling functioning of the device.
In the digital TV system described, the CCU microprocessor and the microprocessors in the auxiliary devices may be conventionally arranged to communicate over the main communication bus. Such a system would entail a specialized microprocessor with a hardware-generated clock signal in each auxiliary device in order to communicate at the high speeds used on the main communication bus. A specialized microprocessor, that is, one that is hardware configured, is significantly more expensive than an off-the-shelf microprocessor. Also, the auxiliary devices may not be required, or even desired, by all users and their low volume production cost becomes very important. It would therefore be desirable to provide a digital TV in which such auxiliary devices utilized off-the-shelf microprocessors for their control.
A digital TV system includes a CCU that is interconnected by a three-wire, high speed bus to a plurality of TV signal function modules for controlling operation thereof by means of a high speed hardware generated clock signal. A software generated clock signal in the CCU is supplied on a low speed two-wire auxiliary device bus which is connected to microprocessors in a plurality of auxiliary devices for performing functions ancillary to TV signal processing. The microprocessor in each auxiliary device is an off-the-shelf type that does not require any special hardware because the timing on the auxiliary device bus is sufficiently slow to enable software monitoring of the line and data transfer.
As mentioned, the three-wire IM bus 21 is a high speed bidirectional bus in which CCU 20 functions as the master and all of the interconnected TV signal processing function modules are slaves that communicate with the CCU in accordance with the protocol established for the system. CCU 20 is also indicated as including a software generated clock which supplies a two-wire auxiliary device bus 50. Two-wire bus 50 includes a clock lead 51 and a data lead 52 coupled to a plurality of auxiliary devices. A VCR 54, including an off-the-shelf microprocessor 55, is coupled to bus 50. A Source Selector 56, including an off-the-shelf microprocessor 57, is also coupled to bus 50. Source Selector 56 has access to four RF inputs, two baseband video and audio inputs and one separate baseband audio input. It will be appreciated that Source Selector 56 may have a greater or lesser number of signal sources to which it has access. Source Selector 56 outputs are coupled to VCR 54 and also to tuner 10 and supply, under control of CCU 20 and keyboard 44, the signal from the signal source selected by keyboard 44 or IR transmitter 46 for use with the digital TV. Auxiliary device bus 50 is also coupled to a Space Phone 58 which includes an off-the-shelf microprocessor 59 and a modem 60 that is connectable to a conventional telephone terminal.
Two-wire auxiliary device bus 50 is a relatively low speed bus and there is no need for separate hardware generated clock signals to be developed by the auxiliary device microprocessors. As mentioned above, this feature involves a significant savings in the cost and complexity of the auxiliary devices.
The protocol used on the two-wire auxiliary device bus consists of a 16 bit sequence, the first eight bits of which are used for bus address commands for the auxiliary devices. Each auxiliary device may respond to 16 addresses which allows the CCU to write into or read from various storage registers in the devices which are used for control or data storage. Thus, with this low cost system, as many as 16 auxiliary devices may be connected to the auxiliary device bus. The second eight bits of the 16 bit sequence contain data which is either transferred from the CCU to the auxiliary device addressed, or transferred from the auxiliary device to the CCU, based upon the bus address used. Thus, the various bus addresses to which a given auxiliary device will respond determine whether the auxiliary device will receive data from the CCU or send data to the CCU. The clock line timing, generated by software in CCU 20, is slow enough to permit software monitoring of the line and data reception by simple auxiliary device microprocessors that are not equipped with an external interrupt feature. The timing on the auxiliary device bus is made sufficiently fast to avoid too many instruction steps or the need for special registers in CCU 20. In the system described, data is clocked every 82.5 microseconds, thus permitting a 16 bit word to be clocked in 1.32 milliseconds. A pause of 277.5 microseconds between the first 8 bits and the second 8 bits permits the slave auxiliary device to process the bus address data contained in the first 8 bits. This timing fits into the 2 millisecond timing block structure used for the CCU in controlling the DIGIT 2000 digital TV. Two-2 millisecond timing blocks have been established in the CCU, which has a 20 millisecond timing loop divided into ten-2 millisecond timing blocks. Thus, two control words may be sent to an auxiliary device every 20 milliseconds, or a request by the CCU to receive data and the actual receipt of that data may take place in that time period.
Referring to the drawing, a digital TV includes a tuner 10 coupled to an IF/Detector 12 which has a pair of outputs 13 and 14 supplying video and audio signals, respectively. Control signals for tuner 10 are supplied through an interface circuit 16 from a CCU microprocessor 20 which functions as a single master control unit for the system. Microprocessor 20 is interconnected by means of a bidirectional three-wire IM (Intermetal) bus 21 to a DPU 22, a VPU 26, an APC 30, a TTX (teletext processor) 38, an APU 36, an ADC 32 and a non-volatile memory 24. A serial control line 29 interconnects a hardware generated clock 28, VPU 26 and VCU 34. VPU 26 and VCU 34 are also interconnected by a seven wire cable and TTX 38 is interconnected with a DRAM 42. DRAM 42 is a dynamic RAM in which TTX information is stored for display. VCU 34 is supplied with video signal and supplies a digitized 7 bit grey coded video signal to VPU 24 for processing and RGB color signals to a Video Drive 40 which, in turn, supplies a cathode ray tube (not shown). A keyboard 44 is coupled to CCU 20 and includes an IR detector that is responsive to coded IR signals supplied from an IR transmitter (IRX) 46. A resident microprocessor in keyboard 44 decodes the received IR signals and generated control commands and supplies appropriate outputs to CCU 20. The diagram, as described, is substantially identical to that for a "DIGIT" 2000 VLSI Digital TV System developed by ITT Intermetal and published in Edition 1984/85 Order No. 6250-11-2E
DIGITAL SOUND BOARD BS 781.0 (BS781) VIEW
Viewing of Digital Audio - Sound Processing: ADC 2300 (ITT ADC2300) and APU 2470 (ITT APU2470)
DIGITAL VIDEO BOARD BS 816.1 (BS815 BS816) VIEW
VCU 2133 A (ITT VCU2133 A) (Video Codec Decodec Unit)
DPU 2543 (ITT DPU2543) (Digital Deflection Processor Unit)
PVPU 2203 (ITT PVPU2203) (PAL and Video Processor Unit)
CCU-SECO-19 (CENTRAL CONTROL UNIT)
TPU 2732 (ITT TPU2732) (Teletext Processor Unit)
MCU 2600 (ITT MCU2600) (Main Clock Unit)
Contains DIGIT2000 Digital Video Processing ChipSet.
VCU 2133 A (ITT VCU2133 A) (Video Codec Decodec Unit)
DPU 2543 (ITT DPU2543) (Digital Deflection Processor Unit)
PVPU 2203 (ITT PVPU2203) (PAL and Video Processor Unit)
DTI 2222 (ITT DTI2222) (Digital Transient Improvement [Chroma])
TPU 2732 (ITT TPU2732) (Teletext Processor Unit)
MCU 2600 (ITT MCU2600) (Main Clock Unit)
REX (ZANUSSI) 33RS627 CHASSIS BS950 Deflection Signal Processing.
Video Clamping Circuit
During line retrace, the clamping circuit (output Pin 21,
DPU 2540) maintains the analog video signal at the correct
working point of the integrated analog-digital converter. at the
input of Video Codec IC VCU 2133, Pin 35. For the second
video input at Pin 37 of the VCU. Pin 4 of the DPU delivers a
further clamping pulse.
The digitized FBA8 (composite colour) signal, which is supplied
as a parallel 7-bit signal from the Video Codec IC 650
(VCU 2133, Pins 2-8) to IC 620 (DPU 2540, Pins 15-9), passes
through a digital low-pass ﬁlter internally for interference
elimination, and is then led in parallel to the clrcults for
separating the horizontal and vertical synchronous pulses. The
circuits function independemly of each other. and thus ensure
Two operating modes are provided for horizontal
synchronization. depending on whether the station received (or
the video recorder connected) is transmitting a standard PAL
signal, in which a fixed frequency-response ratio between colour
carrier frequency and line frequency does or does not apply. in
the former case, we speak of colour-locked mode, in the second
case of non-locked mode. Switch-over between these two
modes is performed automatically by the standard-signal
detector. In colour-locked mode. after the phase position has
been adjusted in non-locked mode, the programmable
frequency divider is set to the standard divider ratio, and the
phase comparison function between synchronous pulses and
horizontal retrace is switched off. so that interference pulses
and noise no longer affect the horizontal deﬂection fucntion. in
non-locked mode, which is necessary when the colour can'ier
frequency and the line frequency of the station do not have a
ﬁxed frequency ratio, the line frequency is generated by dividing
down the clock pulse frequency of 17.7 MHz in the
programmable divider so as to produce the correct line
frequency. Correct phase position of this line frequency is
ensured by the phase comparator. which detects the phase and
frequency errors by means of digital phase comparison between
the separated horizontal synchronous pulses and the horizontal
retrace pulses at Pin 23, and corrects the programmable divider
The line-frequency deflection signal is then available at Pin 31
of DPU 2540 for controlling the deflection circuit and generating
the high voltage. Note that this signal already contains all
necessary corrections, which have been carried out inside the
IC via the lM Bus by comparison with the alignment data stored
in the CCU memory.
As with horizontal synchronization, we also distinguish here
between colour-looked and non-locked modes. In colour-locked
mode, the line frequency is divided down in a fixed ratio so as to
obtain the vertical frequency. In non-locked mode, the settable
divider is operated as a trigger oscillator, and trigered by the
integrated vertical synchronous pulse, with a large trigger
window being used to trap the synchronization, while for
operation the system then switches over to a small trigger
window. All these mode switch-over functions are performed
The vertical deflection sawtooth is generated digitally, including
all correction values such as linearity, amplitude and position,
and results from the output signals of Pins 26 and 27. it is
passed via DV 2 to Pin 1 of IC 401, the integrated vertical output
stage TDA B172. The vertical parabola required for controlling
the east-west modulator is also supplied at Pin 28 by the
deflection processor, and fed via DV 23 to the base of T 562.
VCU 2133 Video Codec UNIT
High-speed coder/decoder IC for analog-to-digital and di-
gital-to-analog conversion of the video signal in digital TV
receivers based on the DIGIT 2000 concept. The VCU 2133
is a VLSI circuit in Cl technology, housed in a 40-pin Dil
plastic package. One single silicon chip combines the fol-
lowing functions and circuit details (Fig. 1):
- two input video amplifiers
- one A/D converter for the composite video signal
- the noise inverter
- one D/A converter for the luminance signal
- two D/A converters for the color difference signals
- one RGB matrix for converting the color difference sig-
nals and the luminance signal into RGB signals
- three RGB output amplifiers
- programmable auxiliary circuits for blanking, brightness
adjustment and picture tube alignment
- additional clamped RGB inputs for text and other analog
- programmable beam current limiting
1. Functional Description
The VCU 2133 Video Codec is intended for converting the
analog composite video signal from the video demodulator
into a digital signal. The latter is further processed
in the VPU 2203 Video Processor and in the DPU 2553 De-
flection Processor. After processing in the VPU 2203 (color
demodulation, PAL compensation, etc.), the VPU‘s digital
output signals (luminance and color difference) are recon-
verted into analog signals in the VCU 2133. From these an-
alog signals are derived the RGB signals by means of the
RGB matrix, and, after amplification in the integrated RGB
amplifiers, the RGB signals drive the RGB output amplifiers
of the color T\/ set.
For TV receivers using the NTSC standard the VPU 2203
may be replaced by the CVPU 2233 Comb Filter Video Pro-
cessor which is pin-compatible with the VPU 2203, but of-
fers better video performance. In the case of SECAM, the
SPU 2220 SECAM Chroma Processor must be connected
in parallel to the VPU 2203 for chroma processing, while
the luma processing remains inthe VPU 2203.
In a more sophisticated CTV receiver according to the Dl-
GIT 2000 concept, after the VPU Video Processor may be
placed the DTI 2223 Digital Transient Improvement Proces-
sor which serves for sharpening color transients on the
screen. The output signals of the DTI are fed to the VCU’s
luma and chroma inputs. To achieve the desired transient
improvement, the R-Y and B-Y D/A converters of the VCU
must be stopped for a certain time which is done by the
hold pulse supplied by the DTI and fed to the Reset pin 23
of the VCU. The pulse detector following this pin seperates
the (capacitively-coupled) hold pulse from the reset signal.
In addition, the VCU 2133 carries out the functions:
- brightness adjustment
- automatic CRT spot-cutoff control (black level)
- white balance control and beam current limiting
Further, the VCU 2133 offers direct inputs for text or other
analog RGB signals including adjustment of brightness and
contrast for these signals.
The RGB matrix and RGB amplifier circuits integrated in
the VCU 2133 are analog. The CRT spot-cutoff control is
carried out via the RGB amplifiers’ bias, and the white bal-
ance control is accomplished by varying the gain of these
amplifiers. The VCU 2133 is clocked by a 17.7 or 14.3 MHz
clock signal supplied by the MCU 2632 Clock Generator IC.
1.1. The A/D Converter with Input Amplifiers and Bit
The video signal is input to the VCU 2133 via pins 35 and 37
which are intended for normal TV video signal (pin 35) and
for VCR or SCART video signal (pin 37) respectively. The
video amplifier whose action is required, is activated by the
CCU 2030, CCU 2050 or CCU 2070 via the IM bus by soft-
ware. The amplification of both video amplifiers is doubled
during the undelayed horizontal blanking pulse (at pin 36)
in order to obtain a higher digital resolution of the color
synchronization signal (burst). At D 2-MAC reception, the
doubled gain is switched off by means of bit p = 1 (Fig. 8).
The A/D converter is of the flash type, a circuit of 2" com-
parators connected in parallel. This means that the number
of comparators must be doubled if one additional bit is
needed. Thus it is important to have as few bits as possi-
ble. For a slowly varying video signal, 8 bits are required.
order to achieve an 8-bit picture resolution using a 7-bit
converter, a trick is used: during every other line the refer-
ence voltage of the A/D converter is changed by an
amount corresponding to one half of the least significant
bit. ln this procedure, a grey value located between two 7-
bit steps is converted to the next lower value during one
line and to the next higher value during the next line. The
two grey values on the screen are averaged by the viewer’s
eye, thus producing the impression of grey values with
8-bit resolution. Synchronously to the changing reference
voltage of the A/D converter, to the output signal of the Y
D/A converter is added a half-bit step every second line.
The bit enlargement just described must be switched off in
the case of using the D2-MAC standard (q = 1 and r = 1
in Fig. 8). ln the case of using the comb filter CVPU instead
of the VPU, the half-bit adding in the Y D/A converter must
be switched off (r = 1 in Fig. 8).
The A/D converter’s sampling frequency is 17.7 MHZ for
PAL and 14.3 MHz for NTSC, the clock being supplied by
the MCU 2632 Clock Generator IC which is common to all
circuits for the digital T\/ system. The converter’s resolu-
tion is 1/2 LSB of 8 bits. Its output signal is Gray-coded to
eliminate spikes and glitches resulting from different com-
parator speeds or from the coder itself. The output is fed to
the VPU 2203 and to the DPU 2553 in parallel form.
1.2. The Noise Inverter
The digitized composite video signal passes the noise in-
verter circuit before it is put out to the VPU 2203 and to the
DPU 2553. The noise inverter serves for suppressing bright
spots on the screen which can be generated by noise
pulses, p. ex. produced by ignition sparks of cars etc. The
function of the noise inverter can be seen in Fig. 2. The
maximum white level corresponds with step 126 of the A/D
converter’s output signal (that means a voltage of 7 V at
pin 35). lf, due to an unwanted pulse on the composite
video signal, the voltage reaches 7.5 V (what means step
127 in digital) or more, the signal level is reduced by such
an amount, that a medium grey is obtained on the screen
(about 40 lFiE). The noise inverter circuit can be switched
off by software (address 16 in the VPU 2203, see there).
1.3. The Luminance D/A Converter (Y)
After having been processed in the VPU 2203 (color de-
modulation, PAL compensation, etc.), the different parts of
the digitized video signal are fed back to the VCU 2133 for
further processing to drive the RGB output amplifiers. The
luminance signal (Y) is routed from the VPU’s contrast mul-
tiplier to the Y D/A converter in the VCU 2133 in the form of
a parallel 8-bit signal with a resolution of 1/2 LSB of 9
This bit range provides a sufficient signal range for contrast
as well as positive and negative overshoot caused by the
peaking filter (see Fig. 3 and Data Sheet VPU 2203).
The luminance D/A converter is designed as an R-2R lad-
der network. lt is clocked with the 17.7 or the 14.3 MHz
clock signal applied to pin 22. The cutoff frequency of the
luminance signal is determined by the clock frequency.
1.4. The D/A Converters for the Color Difference Signals
R-Y and B-Y
ln order to save output pins at the VPU 2203 and input pins
at the VCU 2133 as well as connection lines, the two digital
color difference signals R-Y and B-Y are transferred in time
multiplex operation. This is possible because these signals’
bandwidth is only 1 MHZ and the clock is a 17.7 or 14.3
The two 8-bit D/A converters R-Y and B-Y are also built as
R-2R ladder networks. They are clocked with ‘A clock fre-
quency, but the clock for the multiplex data transfer is 17.7
or 14.3 MHz. Four times 4 bits are transferred sequentially,
giving a total of 16 bits. A sync signal coordinates the
plex operations in both the VCU 2133 and the VPU 2203.
Thus, only four lines are needed for 16 bits. Fig. 4 shows
the timing diagram of the data transfer described.
ln a CTV receiver with digital transient improvement (DTI
2223), the R-Y and B-Y D/A converters are stopped by the
hold pulse supplied by the DTI, and their output signal is
kept constant for the duration of the hold pulse. Thereafter,
the output signal jumps to the new value, as described in
the DTl’s data sheet.
Timing diagram of the multiplex data transfer of the chroma
channel between VPU 2203, VCU 2133 and SPU 2220
a) main clock signal QSM
b) valid data out of the VCU 2133’s video A/D converter.
AIAD is the delay time of this converter, about 40 ns.
c) valid data out of the VPU 2203.
d) MUX data transfer of the chroma signals from VPU 2203
to VCU 2133, upper line: sync pulse from pin 27 VPU to
pin 21 VCU during sync time in vertical blanking time,
see Fig. 8; lower line: valid data from pins 27 to 30
(VPU) to pins 18 to 21 (VCU)
1.5. The RGB Matrix and the RGB Output Amplifiers
ln the RGB matrix, the signals Y, R-Y and B-Y are dema-
trixed, the reduction coefficients of 0.88 and 0.49 being tak-
en into account. In addition, the matrix is supplied with a
signal produced by an 8-bit D/A converter for setting the
brightness of the picture. The brightness adjustment range
corresponds to 1/2 of the luminance signal range (see Fig.
3). It can be covered in 255 steps. The brightness is set by
commands fed from the CCU 2030, CCU 2050 or CCU 2070
Central Control Unit to the VPU 2203 via the IM bus.
There are available four different matrices: standard PAL,
matrix 2, 3 and 4, the latter for foreign markets. 'The re-
quired matrix must be mask-programmed during produc-
tion. The matrices are shown in Table 1, based on the for-
R = r1~(R-Y)+ l'2~(B-Y) +Y
G = Q1-(Ft-Y)+ Q2 - (B-Y) +Y
B = b1-(Ft-Y)+ bg - (B-Y) +Y
The three RGB output amplifiers are impedance converters
having a low output impedance, an output voltage swing of
6 V (p-p), thereof 3 V for the video part and 3 V for bright-
ness and dark signal. The output current is 4 mA. Fig. 5
shows the recommended video output stage configuration.
For the purpose of white-balance control, the amplification
factor of each output amplifier can be varied stepwise in
127 steps (7 bits) by a factor of 1 to 2. Further, the CRT
spot-cutoff control is accomplished via these amplifiers’ bi-
as by adding the output signal of an 8-bit D/A converter to
the intelligence signal. The amplitude of the output signal
corresponds to one half of the luminance range. The eight
bits make it possible to adjust the dark voltage in 0.5 %
steps. By means of this circuit, the factory-set values for
the dark currents can be maintained and aging of the pic-
ture tube compensated.
1.6. The Beam Current and Peak Beam Current Limiter
The principle of this circuitry may be explained by means of
Fig. 6. Both facilities are carried out via pin 34 of the VCU
2133. For beam current limiting and peak beam current li-
miting, contrast and brightness are reduced by reducing
the reference voltages for the D/A converters Y, Ft-Y and
B-Y. At a voltage of more than +4 V at pin 34, contrast and
brightness are not affected. In the range of +4 V to +3 V,
the contrast is continuously reduced. At +3 V, the original
contrast is reduced to a programmable level, which is set
by the bits of address 16 of the VPU as shown in Table 2. A
further decrease of the voltage merely reduces brightness,
the contrast remains unchanged. At 2 V, the brightness is
reduced to zero. At voltages lower than 2 V, the output
goes to ultra black. This is provided for security purposes.
The beam current limiting is sensed at the ground end of
the EHT circuit, where the average value of the beam cur-
rent produces a certain voltage drop across a resistor in-
serted between EHT circuit and ground. The peak beam
current limiting can be provided additionally to avoid
“blooming” of white spots or letters on the screen. For
this, a fast peak current limitation is needed which is
sensed by three sensing transistors inserted between the
RGB amplifiers and the cathodes of the picture tube. One
of these three transistors is shown in Fig. 6. The sum of the
picture tube’s three cathode currents produces a voltage
drop across resistor R1. If this voltage exceeds that gen-
erated by the divider R2, B3 plus the base emitter voltage
of T2, this transistor will be turned on and the voltage at
34 of the VCU 2133 sharply reduced. Time constants for
both beam current limiting and peak beam current limiting
can be set by the capacitors C1 and C2.
1.7. The Blanking Circuit
The blanking circuit coordinates blanking during vertical
and horizontal flyback. During the latter, the VCU 2133's
output amplifiers are switched to “ultra black”. Such
switching is different during vertical flyback, however, be-
cause at this time the measurements for picture tube align-
ment are Carried out. During vertical flyback, only the ca-
thode to be measured is switched to “black” during mea-
suring time, the other two are at ultra black so that only the
dark current of one cathode is measured at the same time.
For measuring the leakage current, all three cathodes are
switched to ultra black.
The sequence described is controlled by three code bits
contained in a train of 72 bits which is transferred from the
VPU 2203 to the VCU 2133 during each vertical blanking in-
terval. This transfer starts with the vertical blanking pulse.
During the transfer all three cathodes of the picture tube
are biased to ultra black. In the same manner, the white-
balance control is done.
The blanking circuit is controlled by two pulse combina-
tions supplied by the DPU 2553 Deflection Processor
(“sandcastle pulses"). Pin 39 of the VCU 2133 receives the
combined vertical blanking and delayed horizontal blanking
pulse from pin 22 of the DPU (Fig. 7 b), and pin 36 of the
VCU gets the combined undelayed horizontal blanking and
color key pulse from pin 19 of the DPU (Fig. 7 a). The two
outputs of the DPU are tristate-controlled, supplying the
output levels max. 0.4 V (low), min. 4.0 V (high), or high-im-
pedance, whereby the signal level in the high-impedance
mode is determined by the VCU’s input configuration, a
voltage divider of 3.6 KS! and 5 KQ between the +5 V sup-
ply and ground, to 2_8 V. The VCU’s input amplifier has two
thresholds of 2.0 V and 3.4 V for detecting the three levels
of the combined pulses. ln this way, two times two pulses
are transferred via only two lines.
1.8. The Circuitry for Picture Tube Alignment
During vertical flyback, a number of measurements are tak-
en and data is exchanged between the VCU 2133, the VPU
2203 and the CCU 2030 or CCU 2050. These measure-
ments deal with picture tube alignment, as white level and
dark current adjustment, and with the photo current sup-
plied by a photo resistor (Fig. 5) which serves for adapting
Data sequence during the transfer of test results from the
VPU 2203 to the VCU 2133. Nine Bytes are transferred, in
each case the LSB first. These 9 Bytes, 8 bits each, coin-
cide with the 72 pulses of 4.4 MHz that are transferred dur-
ing vertical flyback from pin 27 of the VPU 2203 to pin 21 of
the VCU 2133 (see Fig. 9).
l and mi beam current limiter range
l<: noise inverter on/off
n: video input switching bit
S: SECAM chroma sync bit; S = 1 means that the chroma
demultiplexer is synchronized every line. The switch-over
time from C0 to demux counter begins with the end of the
undelayed horizontal blanking pulse and remains valid for a
time of 12 Q M clock periods.
the contrast of the picture to the light in the room where
the TV set is operated. The circuitry for transferring the
ture tube alignment data, the sensed beam currents and
the photo current is clocked in compliance with the VPU
2203 by the vertical blanking pulse and the color key pulse.
To carry out the measurements, a quadruple cycle is pro-
vided (see Table 3). The timing of the data transfer during
the vertical flyback is shown in Fig. 9, and Fig. 8 shows the
data sequence during that data transfer.
Ft, G, B: code bits
p=1; no doubled gain in the input amplifier during horizon-
tal blanking (see section 1.1.)
q=1: no changing of the A/D converter’s reference vol-
tage during every other line (see section 1.1.)
r=1: when operating with the DMA D2-MAC decoder or
the CVPU comb filter video processor, the adding of
a step of ‘/2 LSB to the output signal of the Y D/A
converter is switched off (see section 1.1.).
s=1; the blankirig pulse in the analog video output signal
at pins 26 to 28 is switched off, as is required in
1.9. The Additional RGB Inputs
The three additional analog RGB inputs are provided for
inputting text or other analog RGB signals. They are con-
nected to fast voltage-to-current converters whose output
current can be altered in 64 steps (6 bits) for contrast set-
ting between 100 % and 30 %. The three inputs are
clamped to a DC black level which corresponds to the level
of 31 steps in the luminance channel, by means of the color
key pulse. So, the same brightness level is achieved for
normal and for external RGB signals. The output currents
ofthe converters are then fed to the three RGB output am-
plifiers. Switchover to the external video signal is also
1.10. The Reset Circuit and Pulse Detector
The reset pulse produced by the external reset RC network
in common for the whole DIGIT 2000 system, switches the
RGB outputs to ultra black during the power-on routine of
the TV set. At other times, high level must be applied to the
reset input pin 23.
There is an additional facility with pin 23 which is used only
in conjunction with the DTl 2223 Digital Transient Improve-
ment Processor. The hold pulse produced by the latter
which serves for stopping the R-Y and B-Y D/A converters,
is also fed to pin 23, capacitively-coupled. The pulse detec-
tor responds on positive pulses which exceed the 5 V sup-
ply by about 1 V. The two DACs are stopped as long as the
hold pulse lasts, and supply a constant output signal of the
amplitude at the begin of the hold pulse.
5. Description of the Connections and the Signals
Pins 1, 9, and 25 - Supply Voltage, +5 V
The supply voltage is +5 V. Pins 1 and 25 supply the ana-
log part and must be filtered separately.
Pins 2 to 8 - Outputs V0 to V6
Via these pins the VCU 2133 supplies the digitized video
signal in a parallel 7-bit Gray code to the VPU 2203 and the
DPU 2553. The output configuration is shown in Fig. 16.
Pins 10 to 17 - Inputs L7 to L0
Fig. 17 shows these inputs’ configuration. Via these pins,
the VCU 2133 receives the digital luminance signal from the
VPU 2203 in a paraliel 8-bit code.
Pins 18 to 21 - Inputs C0 to C3
Via these inputs, whose circuitry and data correspond to
those of pins 10 to 17, the VCU 2133 is fed with the digi-
tized color difference signals R-Y and B-Y and with the
control and alignment signals described in section 1.8., in
multiplex operation. Pin 21 is additionally used for the
plex sync signal.
Pin 22 - QSM Main Clock Input
Via this pin, whose circuitry is shown in Fig. 18, the VCU
2133 is supplied with the clock signal QSM produced by the
MCU 2600 or MCU 2632 Clock Generator IC. The clock fre-
quency is 17.7 MHz for PAL and SECAM and 14.3 MHz for
NTSC. The clock signal must be DC-coupled.
Pin 23 - Reset and Hold Pulse Input (Fig. 19)
Via this pin, the VCU 2133 is supplied with the reset and
hold signals which are supplied by pin 21 of the DTI 2223
Digital Transient Improvement Processor for stopping the
R-Y and B-Y D/A converters, and for Reset.
Pins 24 and 29 - Analog Ground, 0
These pins serve as ground connections for the supply and
for the analog signals (GND pin 24 for RGB).
Pins 26 to 28 - RGB Outputs
These three analog outputs deliver an analog signal suit-
able for driving the RGB output transistors. Their diagram
is shown in Fig. 20. The output voltage swing is 6 V total,
3 V for the black-to-white signal and 3 V for adjusting
the brightness and the black level.
Pins 30 to 32 - Additional Analog Inputs R, G and B
Fig. 21 shows the configuration of these inputs. They serve
to feed analog RGB signals, for example for Teletext or si-
milar applications, and they are clamped during the color
key pulse. At a 1 V input, full brightness is reached. The
bandwidth extends from 0 to 8 MHz.
Pin 33 - Fast Switching Input
This input is connected as shown in Fig. 22. It ser\/es for
fast switchover of the video channel between an internally-
produced video signal and an externally-applied video sig-
nal via pins 30 to 32. With 0 V at pin 33, the RGB outputs
will supply the internal video signal, and at a 1 V input
the RGB outputs are switched to the external video signal.
Bandwidth is 0 to 4 MHz, and input impedance 1 KQ mini-
Pin 34 - Beam Current Limiter Input
The diagram of pin 34 is shown in Fig. 25. The input voltage
may be between +5 V and 0 V. The input impedance is 100
kQ. The function of pin 34 is described in section 1.6.
Pin 35 - Composite Video Signal Input 1
To fully drive the video A/D converter the following ampli-
tudes are required at pin 35: +5 V = sync pulse top level,
all bits low; +7 V = peak white, all bits high. Fig. 24 shows
the configuration of pin 35.
Pin 36 - Undelayed Horizontal Blanking and Color Key
The circuitry of this pin is shown in Fig. 23. Pin 36 receives
the combined undelayed horizontal blanking and color key
pulse which are “sandcastled” and are supplied by pin 19
of the DPU 2553 Deflection Processor. During the undelay-
ed horizontal blanking pulse, the input amplifiers’ gain is
doubled, and the bit enlargement circuit is also switched
by this pulse, and the counter for the data transmission
gap started. The color key pulse is used for clamping the
RGB inputs pins 30 to 32.
Pin 37 - Composite Video Signal Input 2
This pin has the same function and properties as pin 35,
except the gain of the input amplifier which is twice the
gain as that of the amplifier at pin 35. This means an input
voltage range of +5 V to +6 V.
Pin 38 - Supply Voltage, +12 V »
The 12 V supply is needed for certain circuit parts to obtain
the required input or output voltage range, as the video in-
put and the RGB outputs (see Figs. 20 and 24).
Pin 39 - Vertical Blanking and Delayed Horizontal Blanking
This pin receives the combined vertical blanking and delay-
ed horizontal blanking. pulse from pin 22 of the DPU 2553
Deflection Processor. Both pulses are “sandcastled” so
that only one connection is needed for the transfer of two
pulses. These two pulses are separated in the input circui-
try of the VCU 2133, and are used for blanking the picture
during vertical and horizontal flyback. Fig. 23 shows the cir-
cuitry of pin 39.
Pin 40 - Digital Ground, O
This pin is used as GND connection in conjunction with the
pins 2 to 8 and 10 to 21 which carry digital signals.
DPU 2553, DPU 2554 Deflection Processors UNIT
Note: lf not otherwise designated, the pin numbers
mentioned refer to the 40-pin Dil package.
These programmable VLSI circuits in n-channel mOS
technology carry out the deflection functions in digital
colorTV receivers based onthe DiGiT 2000 system and
are also suitable for text and D2~mAC application. The
three types are basically identical, but are modified ac-
cording to the intended application:
normal-scan horizontal deflection, standard CTV re-
ceivers, also equipped with Teletext and D2-mAC fa-
double-scan horizontal deflection, for CTV receivers
equipped with double-frequency horizontal deflection
and double-~frequency vertical deflection for improved
picture quality. At power-up, this version starts with
double horizontal frequency.
1.1. General Description
The DPU 2553/54 Deflection Processors contain the fol-
lowing circuit functions on one single silicon chip:
- video clamping
- horizontal and vertical sync separation
~ horizontal synchronization
- normal horizontal deflection
-east-west correction, also for flat-screen picture
- vertical synchronization
- normal vertical deflection
~ sawtooth generation
-text display mode with increased deflection frequen-
cies (18.7 kHz horizontal and 60 Hz vertical)
- D2-mAC operation mode
and for DPU 2554 only:
- double-scan horizontal deflection
- normal and double-scan vertical deflection
ln this data sheet, all information given for double~scan
mode is available with the DPU 2554 only. Type DPU
2553 starts the horizontal deflection with 15.5 kHz ac-
cording to the normal TV standard, whereas type DPU
2554 starts with 31 kHz according to the double-scan
The following characteristics are programmable:
~ selection ofthe TV standard (PAL, D2-mAC or NTSC)
- selection ofthe deflection standard (Teletext, horizon-
tal and vertical double-scan, and normal scan)
- filter time»constant for horizontal synchronization
- vertical amplitude, S correction, and vertical position
for in-line, flat-screen and Trinitron picture tubes
- east-west parabola, horizontal width, and trapezoidal
correction for in-line, flat-screen and Trinitron picture
- switchover characteristics between the different syn-
~characteristic of the synchronism detector for PLL
switching and muting
Fig. 1-1 showsthe simplified block diagram ofthe video
and deflection section of a digital TV receiver based on
the DIGIT 2000 system. The analog video signal derived
from the video detector is digitized in the VCU 2133,
VCU 2134 or VCU 2136 Video Codec and supplied in a
parallel 7 bit Gray code. This digital video signal is fed to
the video section (PVPU, CVPU, SPU and DmA) and to
the DPU 2553/54 Deflection Processorwhich carries out
all functions required in conjunction with deflection, from
sync separation to the control of the deflection power
stages, as described in this data sheet.
3. Functional Description
3.1. Block Diagram
The DPU 2553 and DPU 2554 Deflection Processors
perform all tasks associated with deflection in TV sets;
- sync separation
- generation and synchronization of the horizontal and
the vertical deflection frequencies
-the various eastevvest corrections
- vertical savvtooth generation including S correction
as described hereafter. The DPU communicates, viathe
bidirectional serial lm bus, with the CCU 2050 or CCU
2070 Central Control Unit and, via this bus, is supplied
with the picture-correction alignment information stored
in the mDA 2062 EEPROM during set production, vvhen
the set is turned on. The DPU is normally clocked with
a trapezoidal 17.734 mHz (PAL or SECAm), or 14.3 mhz
(NTSC) or 20.25 mHz (D2-mAC) clock signal supplied
by the mCU 2600 or mCU 2632 Clock Generator IC.
The functional diagram of the DPU is shovvn in Fig. 3-1.
3.2. The Video Clamping Circuit and the Sync Pulse
The digitized composite video signal delivered as a 7»bit
parallel signal by the VCU 2133, VCU 2134 or VCU 2136
Video Codec is first noise-filtered by a 1 mHz digital lovv-
pass filter and, to improve the noise immunity ofthe
clamping circuit, is additionally filtered by a 0.2 mHz low-
pass filter before being routed to the minimum and back
porch level detectors (Fig. 3-3).
The DPU has tvvo different clamping outputs, no. 1 and
No. 2, one of vvhich supplies the required clamping
pulses to the video input of the VCU as shovvn in Fig.
3-1. The following values forthe clamping circuit apply
for Video Amp. l. since the gain of Video Amp. ll istwice
th at of Video Amp l, all clamping and signal levels of Vid-
eo Amp ll are halt those of Video Amp l referred to +5 V.
Afterthe TV set is switched on,thevideo clamping circuit
first of all ensures by means of horizontal-frequency
current pulses from the clamping output of the DPU to
the coupling capacitor of the analog composite video
signal, that the video signal atthe VCU’s input is optimal-
ly biased for the operation range of the A/D converter of
5 to 7 V. For this, the sync top level is digitally measured
and set to a constant level of 5.125 V by these current
pulses. The horizontal and vertical sync pulses are novv
separated by a fixed separation level of 5.250 V so that
the horizontal synchronization can lock to the correct
phase (see section 3.3. and Figs. 3-2 and 3-3).
vvith the color key pulse which is now present in syn-
chronism with the composite video signal, the video
clamping circuit measures the DC voltage level of the
porch and by means of the pulses from pin 21 (or pin4),
sets the DC level ofthe porch at a constant 5.5 V (5.25 V
for Video Amp ll). This level is also the reference black
to Video Processorffeletext Processor, D2-MAC Processor tc.
level for the PVPU 2204 or CvPU 2270 Video Proces-
When horizontal synchronization is achieved, the slice
level for the sync pulses is set to 50 % of the sync pulse
amplitude by averaging sync top and black level. This
ensures optimum pulse separation, even with small
sync pulse amplitudes (see application notes, section
3.3. Horizontal Synchronization
Two operating modes are provided for in horizontal syn-
chronization. The choice of mode depends on whether
or not the Tv station is transmitting a standard PAL or
NTSC signal, in which there is a fixed ratio between color
subcarrier frequency and horizontal frequency. ln the
first case we speak of “color-locked” operation and in
the second case of “non-color-locked” operation (e.g.
black-and-white programs). Switching between thetwo
modes is performed automatically by the standard sig-
3.3.1. Non-Color-Locked Operation
ln the non»locked mode,which is needed in the situation
where there is no standard fixed ratio between the color
subcarrier frequency and the horizontal frequency ofthe
transmitter, the horizontal frequency is produced by subdemding the clock frequency (1 7.7 mHz for PAL and SECAM, 14.3
mHz for NTSC) in the programmable fre-
quency dmder (Fig. 3-4) until the correct horizontal
frequency is obtained. The correct adjustment of fre-
quency and phase is ensured by phase comparator l.
This determines the frequency and phase deviation by
means of a digital phase comparison between the sepa-
rated horizontal sync pulses and the output signal of the
programmable dmder and corrects the dmder accordingly. For
optimum adjustment of phase iitter, capture
behavior and transient response of the horizontal PLL
circuit, the measured phase deviation is filtered in a digi-
lowpass filter (PLL phase filter). ln the case of non-
OZMH synchronized horizontal PLL, this filter is set to
wideband PLL response with a pull-in range of 1800 Hz. if the
- sync sync PLL circuit is locked, the PLL filter is
automatically switched to narrow-band response by an internal
synchronism detector in order to limit the phase jitter to a
minimum, even in the case of weak and noisy signals.
A calculator circuit in phase comparator , which analyzes the
edges of the horizontal sync pulses, increases
the resolution of the phase measurement from 56 ns at
Fig. 3-3: Principle ofvideo clamping and pulse separa- 17.7
mHz clock frequency to approx. 6 ns, or from 70 ns
NON at 14.3 MHz clock frequency to approx. 2.2 ns.
The various key and gating pulses such as the color key
pulse (tKe(,), the normal-scan (1 H) and double-scan
(2H) horizontal blanking pulse (tAZ(/) and the 1 H hori-
zontal undelayed gating pulse (t/(Z) are derived from the
output signals ofthe programmable dmder and an addi-
tional counter forthe2H signals and the 1 H and 2H skew
data output. These pulses retain a fixed phase position
with respect to the 1 H inputvideo signal andthe double-
scan output video signal from the CvPU 2270 Video Pro-
Forthe purpose of equalizing phase changes in the hori-
zontal output stage due to switching response toler-
ances or video influence, a second phase control loop
is used which generates the horizontal output pulse at
pin 31 to drivethe horizontal output stage. ln phase com-
parator li (Fig. 3~4), the phase difference between the
output signal of the programmable dmder and the lead-
ing edge (or the center) of the horizontal flyback pulse
(pin 23) is measured by means of a balanced gate delay
line. The deviation from the desired phase difference is
used as an input to an adder. ln this, the information on
the horizontal frequency derived from phase com-
parator l is added to the phase deviation originating form
phase comparator ll. The result of this addition controls
a digital on-chip sinewave generator (about 1 mHz)
which acts as a phase shifter with a phase resolution of
1/128 of one main clock period m_
By means of control loop ll the horizontal output pulse
(pin 31) is shifted such that the horizontal flyback pulse
(pin 23) acquiresthe desired phase position with respect
to the output signal of the programmable dmder which,
in turn, due to phase comparator l, retains a fixed phase
position with respect to the video signal. The horizontal
output pulse itself is generated by dmding the frequency
ofthe 1 mHz sinewave oscillator by a fixed ratio of 64 in
the case of norm al scan and of 32 in the case of double-
3.3.2. Color-Locked Operation
When in the color~locked operating mode, after the
phase position has been set in the non-color-locked
mode, the programmable dmder is set to the standard
dmsion ratio (1135:1 for PAL, 91O:1 for NTSC) and
phase comparator is disconnected so that interfering
pulses and noise cannot influence the horizontal deflec-
tion. Because phase comparator ll is still connected,
phase errors ofthe horizontal output stage are also cor-
rected in the color»locKed operating mode. The stan-
dard signal detector is so designed that it only switches
to color-locked operation when the ratio between color
subcarrier frequency and horizontal frequency deviates
no more than 1O'7 from the standard dmsion ratio. To
ascertain this requires about 8 s (NTSC). Switching off
color-locked operation takes place automatically, in the
_ case of a change of program for example, within approx-
imately 67 ms (e.g. two NTSC fields, 60 Hz).
3.3.3. Skew Data Output and Field Number Informa-
with non-standard input signals, the TPU 2735 or TPU
2740 Teletext Processor produce a phase error vvith re-
spect to the deflection phase.
The DPU generates a digital data stream (skevv data,
pin 7 ofthe DPU), which informs the PSP and TPU on
the amount of phase delay (given in 2.2 ns increments)
used in the DPU for the 1H and 2h output pulse com-
pared With the Fm main clock signal of 17.7 mHz (PAL
or SECAm) or 14.3 mhz (NTSC), see also Figs. 3-6 to
3-8. The skew data is used by the PSP and by the TPU
to adjust the double-scan video signal to the 1 H and 2H
phase of the horizontal deflection to correct these phase
For the vmC processor the skew data contains three additional
bits for information about frame number, 1 V
sync and 2 V sync start.
3.3.4. Synchronism Detector for PLL and Muting
To evaluate locking ofthe horizontal PLL and condition
of the signal, the DPU’s HSP high-speed processor
(Fig. 3~1) receives two items of information from the hor-
izontal PLL circuit (see Fig. 3-11).
a) the overall pulsevvidth of the separated sync pulses
during a 6.7 us phase window centered to the horizontal
sync pulse (value A in Fig. 3-11).
b) the overall pulsevvidth of the separated sync pulse
during one horizontal line but outside the phase window
(value B in Fig. 3-11).
Based on a) and b) and using the selectable coefficients
KS1 and KS2 and a digital lovi/pass filter, the HSP pro-
cessor evaluates an 8-bit item of information “SD” (see
Fig. 3-12). By means of a comparator and a selectable
level SLP, the switching threshold for the PLL signal
“UN” is generated. UN indicates Whether the PLL is in
the synchronous or in the asynchronous state.
To produce a muting signal in the CCU, the data SD can
be read by the CCU. The range ot SD extends from O
(asynchronous) to +127 (synchronous). Typical values
torthe comparator levels and their hysteresis B1 = 30/20
and for muting 40/30 (see also HSP Bam address Table
DPU 2553, DPU 2554
3.4. Start Oscillator and Protection Circuit
To protect the horizontal output stage of the TV set dur-
ing changing the standard and for using the DPU as a
low power start oscillator, an additional oscillator is pro-
vided on-chip (Fig. 3-4), with the output connected to
pin 31. This oscillator is controlled by a 4 mHz signalin-
dependent trom the Fm main clock produced by the
MCU 2600 or mCU 2632 Clock Generator IC and is pow-
ered by a separate supply connected to pin 35. Thefunc-
tion ofthis circuitry depends on the external standard se-
lection input pin 33 and on the start oscillator select input
pin 36, as described in Table 3-3. Using the protection
circuit as a start oscillator, the following operation modes
are available (see Table 3-3).
With pin 33 open-circuit, pin 36 at high potential (con-
nected to pin 35) and a 4 mHz clock applied to pin 34,
the protection circuit acts as a start oscillator. This pro-
duces a constant-frequency horizontal output pulse of
15.5 kHz in the case of DPU 2553, and of 31 khz in the
case of DPU 2554 while the Beset input pin 5 is at low
potential. The pulsewidth is 30 us with DPU 2553, and
16 us with DPU 2554. main clock at pin 2 or main power
supplies at pins 8, 32 and 40 are not required for this start
oscillator After the main power supply is stabilized and
the main clock generator has started, the reset input pin
5 must be switched to the high state. As long as the start
values from the CCU are invalid, the start oscillator will
continuously supply the output pulses of constant fre-
quency to pin 31 _ By means of the start values given by
the CCU via the lm bus, the register FL must be set to
zero to enable the stan oscillator to be triggered by the
horizontal PLL circuit. After that, the output frequency
and phase are controlled by the horizontal PLL only.
It the external standard selection input pin 33 is con-
nected to ground or to +5 V, the start oscillator is
switched off as soon as it ls in phase with PLL circuit. Pin
33to ground selects PAL or SECAm standard (17.7 mHz
main clock), and pin 33 to +5 V selects NTSC standard
(14.3 MHz main clock). After the main power supplies to
pins 8, 32 and 40 are stabilized, the start oscillator can
be used as a separate horizontal oscillator with a con-
stant frequency of 15.525 khz. For this option, pin 33
must be unconnected. By means ofthe lm bus register
SC the start oscillator can be switched on (SC = 0) or oft
(SC = 1). Setting SC =1 is recommended.
By means of pin 29 (horizontal output polarity selectin-
put and start oscillator pulsewidth select input), the out-
put pulsewidth and polarity ofthe start oscillator and pro-
tection circuit can be hardware-selected. Pin 29 at low
potential gives 30 us for DPU 2553 and 16 us for DPU
2554,with positive output pulses. Pin 29 at high potential
gives 36 us for DPU 2553 and 18 its for DPU 2554, with
negative output pulses. Both apply forthetime period in
which no start values are valid from the CCU. If pin 29
is intended to be in the high state, it must be connected
to pin 35 (standby power). Pin 29 must be connected to
ground or to +5 V in both cases.
Table 3-3: Operation modes ofthe start oscillator and
Operation Mode Pins
33 34 35 36
Horizontal output stage protected not connected 4 mHz Clock at
+5 V at ground
during main clock frequency changing
(for PAL and NTSC)
Horizontal output stage protected not connected 4 MHz Clock +5
V with connected to
and start oscillator function start oscilla- pin 35
(for PAL and NTSC) tor supply
Only start oscillator function with at +5 V 4 mHz Clock +5 V
with connected to
NTSC standard after Beset start oscilla- pin 35
Only start oscillator function with at ground 4 mHz Clock +5 V
with connected to
PAL or SECAM standard after Beset start oscilla~ pin 35
5 tor supply
_ with 17.7 mHz clock at ground at ground at +5 V at ground
3.5. Blanking and Color Key Pulses
Pin 19 supplies a combination ofthe color key pulse and
the undelayed horizontal blanking pulse in the form of a
three-level pulse as shown in Fig. 3-13. The high level
(4 V min.) and the low level (0.4 V max.) are controlled
by the DPU. During the low time of the undelayed hori-
zontal blanking pulse, pin 19 of the DPU i sin the high--
impedance mode and the output level at pin 19 is set to
2.8 V by the VCU.
At pin 22, the delayed horizontal blanking pulse in com-
bination with the vertical blanking pulse is available as
athree-level pulse as shown in Fig. 3-13. Output pin 22
is in high-impedance mode during the delayed horizon-
tal blanking pulse.
ln double-scan operation mode (DPU 2554), pin 22 sup-
plies the double-scan (2H) horizontal blanking pulse in-
stead ofthe 1H blanking pulse (DPU 2553). ln text dis-
play mode with increased deflection frequencies (see
section 1.), pin 22 ofthe respective DPU (DPU 2553, as
defined by register ZN) delivers the horizontal blanking
pulse with 18.7 kHz and the vertical blanking pulse with
60 Hz according to the display. At pin 24 the undelayed
horizontal blanking pulse is output.
normally,pin3suppliesthe samevertical blanking pulse
as pin 22. However, with“DVS” = 1, pin 3 will be in the
single-scan mode also with double-scan operation of
the system. The pulsewidth of the single-scan vertical
blanking pulse at pin 3 will be the same as.that of the
double-scan vertical blanking pulse at pin 22. The out-
put pulse of pin 3 is only valid if the COU register “VBE”
is set to 1 . The default value is set to 0 (high-impedance
state of pin 3).
Fig. 3-13: Shape of the output pulses at pins 19 and 22
*) The output level is externally defined
3.6. Output for Switching the Horizontal Power
Stage Between 15.6 kHz (PAL/NTSC) and 18 kHz
This output (pin 37) is designed as a tristate output. High
levels (4 V mln.) and low levels (0.4 V max.) are con-
trolled bythe DPU. During high-impedance state an ex-
ternal resistor network defines the output level,
For changing the horizontal frequency from 15 kHz to
18 kHz, the following sequence of output levels is
derived at pin 37 (see Fig. 3-14).
After register ZN is set from ZN = 2 (15 kHz) to ZN = 0
(18 kHz) by the CCU, pin 37 is switched from High level
to high-impedance state synchronously with the fre-
quency change at pin 31. Following a delay of 20ms, pin
37 is set to Low level and remains in this state forthetime
the horizontal frequency remains 18 kHz (with ZN == 0).
This 20 ms delay is required for switching-over the hori-
zontal power stage.
To change the horizontal frequency in the opposite di-
rection, from 18 kHz to 15.6 kHz, the sequence de-
scribed is reversed.
3.7. Text Display Mode with Increased Deflection
As already mentioned, the DPU 2553 provides the fea-
ture of increased deflection frequencies for text display
for improved picture quality in this mode of operation. To
achieve this, the processor acting as deflection proces-
sor has its register Zn set to 0. The horizontal output fre-
quency at pin 31 is then switched to a frequency of
18746.802 Hz which is generated by dmding the Fm
main clock frequency by 946 i 46. The horizontal PLL is
then able to synchronize to an external composite sync
signal offH = 18.746 kHzi 46. The horizontal PLL isthen
able to synchronizeto an external composite sync signal
of fH = 18.746 kHzi 5 % and f\, = 60 Hz i 10 % and can
be set to an independent horizontal and vertical sync
generator by setting register VE = 1 and register VB = 0.
That means a constant dmder of 946 for horizontal fre-
quency and constant 312 lines per frame.
The DPU working in this mode supplies the TPU 2740
Teletext Processor or the respective Viewdata Proces-
sor with the 18.7 kHz horizontal blanking pulses form pin
24 and the 60 Hz vertical blanking pulses form pin 22
(see Fig. 3-8).
To be able to receive and store data from an IF video sig-
nal at the same time, the Teletext or Viewdata Processor
requires horizontal and vertical sync pulses from this IF
signal. Therefore, the second DPU provides video
clamping and sync separation forthe external signal and
supplies the horizontal sync pulses (pin 24) and the ver-
tical sync pulses (pin 22) to the Teletext or viewdata Pro-
cessor. For this, the second DPU is set to the PAL stan-
dard by register ZN = 2, and the clamping pulses of the
other DPU are disabled by CLD = 1.
To change the output frequency ofthe DPU acting as de-
flection processor from 18.7 kHz to 15.6 kHz, the control
switch output pin 37 prepares the horizontal output
stage for 15.6 khz operation (pin 37 is in the high-impe-
dance state) beforethe DPU changesthe horizontal out-
put frequencyto 15.6 kHz, after a minimum delay of one
vertical period. Switching the horizontal deflection fre-
quency from 15.6 kHzto 18.7 kHz is done in the reverse
sequence. Firstly, the horizontaloutput frequency of pin
31 is switched to 1 8.7 khz, and after a delay of one verti-
cal period, pin 37 is set low.
3.8. D2-MAC Operation Mode
When receiving Tv signals having the D2-mAC stan-
dard (direct satellite reception), register ZN is set to 3.
The programmable dmder is set to a dmsion ratio of
1296 i48 to generate a horizontal frequency of 15.625
khz with the clock rate of 20.25 mHz used in the
D2-mAC standard. ln this operation mode, pin 6 acts as
input forthe composite sync signal supplied by the DmA
2271 D2-mAC Decoder. The DPU is synchronized to
this sync signal, and after locking-in (status register
UN = 0), the CCU switches the DPU to a clock-locked
mode between clock signal and horizontal frequency
clock by 1024, during the vertical sync signal separated
from the received video signal. To use an 8-bit register,
the result of the count is dmded by 2 and given to the
DPU status register. ln the CCU, the vertical frequency
can be evaluated using the following equation:
fv I __lL1’_l\
1024- vP- 2
fm), = 17.734475 mHz with PAL and SECAm
fq,M =14.31818 mHz with NTSC
rw = 2o_25 MHZ with D2-mAc
VP = status value, read from DPU.
The interlace control output pin 39 supplies a 25 Hz (for
PAL and SECAm) or 80 Hz (for NTSC) signal for control-
ling an external interlace-off switch, which is required
with A.C.-coupled vertical output stages, becausethese
are not able to handle the internal interlace-off proce-
dure using register “ZS”.
For operation with the vmC Processor the DPU 2554
hasthree interlace control modes in double vertical scan
mode (DVS = 1). These options can be selected with the
register “IOP” and can be used together with the control
output pin 39 only. This output has to be connected to the
vertical output stage, so that the vertical phase can be
shifted by 16 us (or 32 us with DPU 2553).
REX (ZANUSSI) 33RS627 CHASSIS BS950 ITT DIGIT2000 CATHODE RAY TUBE (Kinescope) driver with kinescope current sensing circuit:CHASSIS BS950
A television receiver includes a kinescope and a current sensing transistor for conveying amplified video signals to the kinescope, and for providing at a sensing output terminal an output signal related to the magnitude of kinescope current conducted during given sensing intervals. A clamping circuit clamps the sensing output terminal during normal image intervals, and unclamps the sensing output terminal during the sensing intervals. The clamping circuit facilitates interfacing the sensing transistor with utilization circuits which process the sensed output signal, and assists to maintain a proper operating condition for the sensing transistor.
1. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage with a video signal input and a video signal output for providing an amplified video signal;
means for conveying said amplified video signal to said image reproducing display device, said conveying means having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
clamping means for selectively clamping said sensing output during normal image intervals, and for unclamping said sensing output during intervals when said sensed signal representative of current conducted by said image reproducing display device is subject to processing by said utilization means; wherein
said clamping means comprises clamping transistor means with an output first electrode coupled to said sensing output, a second electrode coupled to an operating potential, and an input third electrode coupled to said sensing output, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed representative signal.
2. Apparatus according to claim 1, wherein:
said video output stage comprises a video amplifier with a video signal input and a video signal output for providing said amplified video signal; and
said conveying means comprises an active current conducting device with an input first terminal for receiving said amplified video signal, an output second terminal for conveying said amplified video signal to said image reproducing display device, and a third terminal for providing said sensed signal.
3. Apparatus according to claim 2, wherein
said active current conducting device is a transistor with a base input for receiving said amplified video signal, an emitter output for providing said amplified video signal to said image reproducing display device, and a collector output for providing said sensed signal.
4. Apparatus according to claim 1, wherein
said first and second electrodes define a main current conduction path of said clamping transistor means.
5. Apparatus according to claim 4, wherein
said clamping means includes resistive means coupled to said sensing output for providing a voltage in accordance with the magnitude of said sensed signal; and
said third electrode of said clamping transistor means is coupled to said resistive means.
6. Apparatus according to claim 1, and further comprising
filter means for bypassing high frequency signal components at said sensing output.
7. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage coupled to said image reproducing display device for providing an amplified video signal thereto, and having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
control means responsive to said sensed signal for developing a control signal;
means for coupling said control signal to said image reproducing display device to maintain a desired conduction characteristic of said image reproducing display device; and
clamping means for selectively clamping said sensing output during normal image intervals, and for unclamping said sensing
output during intervals when said control means operates to monitor said sensed signal; wherein
said clamping means comprises clamping transistor means with an output first electrode coupled to said sensing output, a second electrode coupled to an operating potential, and an input third electrode coupled to said sensing output, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed signal.
8. Apparatus according to claim 7, wherein
said control means includes digital signal processing circuits; and
said control means includes an input analog-to-digital signal converter network.
9. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video amplifier with a video signal input for receiving video signals, and a video signal output for providing an amplified video signal;
a signal coupling transistor with an input first electrode for receiving said amplified video signal from said video amplifier, an output second electrode for providing a further amplified video signal to said image reproducing display device, and a third electrode for providing a sensed signal representative of the magnitude of the current conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
clamping means for selectively clamping said third electrode of said coupling transistor during normal image intervals, and for unclamping said third electrode during interval when said sensed representative signal is subject to processing by said utilization means, said clamping means comprising clamping transistor means with an output first electrode coupled to said third electrode of said signal coupling transistor, a second electrode coupled to an operating potential, and an input third electrode coupled to said third electrode of said signal coupling transistor, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said input third electrode of said clamping transistor means.
10. Apparatus according to claim 9, wherein
said coupling transistor is an emitter follower transistor with a base input electrode, an emitter output electrode, and a collector output electrode corresponding to said third electrode.
Video signal processing and display systems such as television receivers commonly include a video output display driver stage for supplying a high level video signal to an intensity control electrode, e.g., a cathode electrode, of an image display device such as a kinescope. Television receivers sometimes employ an automatic black current (bias) control system or an automatic white current (drive) control system for maintaining desired kinescope operating current levels. Such control systems typically operate during image blanking intervals, at which time the kinescope is caused to conduct a black image or a white image representative current. Such current is sensed by the control system, which generates a correction signal representing the difference between the magnitude of the sensed representative current and a desired current level. The correction signal is applied to video signal processing circuits for reducing the difference.
Various techniques are known for sensing the magnitude of the black or white kinescope current. One often used approach employs a PNP emitter follower current sensing transistor connected to the kinescope cathode signal coupling path. Such sensing transistor couples video signals to the kinescope via its base-to-emitter junction, and provides at a collector electrode a sensed current representative of the magnitude of the kinescope cathode current. The representative current from the collector electrode of the sensing transistor is conveyed to the control system and processed to develop a suitable correction signal.
In accordance with the principles of the present invention, there is disclosed a kinescope current sensing arrangement wherein a current sensing device is coupled to a kinescope for providing at an output terminal a signal representative of the magnitude of the kinescope current. A clamping circuit clamps the output terminal to a given voltage during normal image trace intervals. During prescribed kinescope current sensing intervals, however, the clamping circuit is inoperative and the sensed signal representative of the kinescope current is developed at the output terminal. The clamping circuit advantageously facilitates interfacing the current sensing device with control circuits for processing the sensed signal, and assists to maintain a proper operating condition for the current sensing device which, in a disclosed embodiment, also conveys video signals to the display device. In accordance with a feature of the invention, the clamping circuit is self-keyed between clamping and non-clamping states in response to the representative signal at the output terminal.
In the drawing:
FIG. 1 shows a circuit diagram of a kinescope driver stage with associated kinescope current sensing and clamping apparatus in accordance with the present invention; and
FIG. 2 depicts, in block diagram form, a portion of a color television receiver incorporating the current sensing and clamping apparatus of FIG. 1.
In FIG. 1, low level color image representative video signals r, g, b are provided by a source 10. The r, g and b color signals are coupled to similar kinescope driver stages. Only the red (r) color signal video driver stage is shown in schematic circuit diagram form.
Red kinescope driver stage 15 comprises a driver amplifier including an input common emitter amplifier transistor 20 arranged in a cascode amplifier configuration with a common base amplifier transistor 21. Red color signal r is coupled to the base input of transistor 20 via a current determining resistor 22. Base bias for transistor 20 is provided by a resistor 24 in association with a source of negative DC voltage (-V). Base bias for transistor 21 is provided from a source of positive DC voltage (+V) through a resistor 25. Resistor 25 in the base circuit of transistor 21 assists to stabilize transistor 21 against oscillation.
The output circuit of driver stage 15 includes a load resistor 27 in the collector output circuit of transistor 21 and across which a high level amplified video signal is developed, and opposite conductivity type emitter follower transistors 30 and 31 with base inputs coupled to the collector of transistor 21. A high level amplified video signal R is developed at the emitter output of follower transistor 30 and is coupled to a cathode electrode of an image reproducing kinescope via a kinescope arc current limiting resistor 33. A resistor 34 in the collector circuit of transistor 31 also serves as a kinescope arc current limiting resistor. Degenerative feedback for driver stage 15 is provided by series resistors 36 and 38, coupled from the emitter of transistor 31 to the base of transistor 20.
A diode 39 connected between the emitters of transistors 30 and 31 as shown is normally reverse biased and therefore nonconductive by the voltage difference across it equalling the sum of the two base-emitter voltage drops of transistors 30 and 31, but is forward biased and therefore rendered conductive under certain conditions in response to positive-going transients at the emitter of transistor 30, corresponding to the output terminal of driver stage 15. The arrangement of transistor 31 prevents the amplifier feedback loop including transistors 20, 21 and 31 and resistors 36 and 38 from being disrupted, thereby preventing feedback transients and signal ringing from occurring. Additional details of the arrangement including transistors 30 and 31 and diode 39 are found in my copending U.S. patent application Ser. No. 758,954 titled "FEEDBACK DISPLAY DRIVER STAGE".
The emitter voltage of transistor 30 follows the voltage developed across load resistor 27, and transistor 30 conducts the kinescope cathode current. Substantially all of the kinescope cathode current flows as collector current of transistor 30, through a kinescope arc current limiting protection resistor 37a, to a clamping network 40. Transistor 30 acts as a current sensing device in conjunction with network 40 as will be explained. Clamping network 40 in this example is self-keyed to exhibit clamping and non-clamping states in response to the magnitude of the current conducted by transistor 30.
Clamping network 40 is common to all three driver stages of the receiver, as will be seen subsequently in connection with FIG. 2, and is coupled to the green and blue signal driver stages via protection resistors 37b and 37c. Network 40 includes clamping transistors 41 and 42 arranged in a Darlington configuration, and series voltage divider resistors 43 and 44 which bias clamp transistors 41 and 42. A high frequency bypass capacitor 46 filters signals in the collector circuit of transistor 30 in a manner to be described below. The series combination of a mode control switch 49 and a scaling resistor 48 is coupled across resistors 43 and 44. A voltage related to the magnitude of kinescope current is developed at a terminal A and, as will be explained with reference to FIG. 2, the voltage at terminal A can be used in conjunction with a feedback control loop to maintain a desired kinescope operating current condition which is otherwise subject to deterioration due to kinescope aging and temperature effects, for example.
Assuming switch 49, the function of which will be explained below, is open, the kinescope cathode current flowing in the collector of transistor 30 is conducted to ground via resistors 43 and 44. When this current causes a voltage drop across resistor 44 to sufficiently forward bias the base-emitter junctions of transistors 41 and 42, transistor 42 will conduct in a linear region, and will clamp terminal A to a voltage VA according to the following expression, where V BE41 and V BE42 are the base-emitter junction voltage drops of transistors 41 and 42: VA=(V BE41 +V BE42 ) (R43+R44)/R44
During normal image intervals typically there are greater than approximately 25 microamperes of current conducted by transistor 30, which is sufficient to render transistors 41 and 42 conductive for developing clamping voltage VA at terminal A. At other times, as will be discussed, transistors 41 and 42 are rendered nonconductive whereby clamping action is inhibited and a (variable) voltage is developed at node A as a function of the magnitude of the kinescope cathode current, for processing by succeeding control circuits.
Illustratively, the arrangement of FIG. 1 can be used in connection with digital signal processing and control circuits in a color television receiver employing digital signal processing techniques, as will be seen in FIG. 2. Such control circuits include an input analog-to-digital converter (ADC) for converting analog voltages developed at terminal A to digital form for processing.
When the control circuits are to operate in an automatic kinescope black current (bias) control mode, wherein during image blanking intervals the kinescope conducts very small cathode currents on the order of a few microamperes, approximating a kinescope black image condition, clamp transistors 41 and 42 are rendered nonconductive because such small currents flowing through resistors 43 and 44 from the collector of transistor 30 are unable to produce a large enough voltage drop across resistor 44 to forward bias transistors 41 and 42. Consequently terminal A exhibits voltage variations, as developed across resistors 43 and 44, related to the magnitude of kinescope black current. The voltage variations are processed by the control circuits coupled to terminal A to develop a correction signal, if necessary, to maintain a desired level of kinescope black current conduction by feedback action. In this operating mode switch 49, e.g., a controlled electronic switch, is maintained in an open position as shown in response to a timing signal VT developed by the control circuits.
When the control circuits are to operate in an automatic kinescope white current (drive) control mode wherein during image blanking intervals the kinescope conducts much larger currents representing a white image condition, switch 49 closes in response to timing signal VT, thereby shunting resistor 48 across resistors 43 and 44. The value of resistor 48 is chosen relative to the combined values of resistors 43 and 44 so that the larger current conducted via the collector of transistor 30 divides between series resistors 43, 44 and resistor 48
such that the magnitude of current conducted by resistors 43 and 44 is insufficient to produce a large enough voltage drop across resistor 44 to render clamping transistors 43 and 44 conductive. Unclamped terminal A therefore exhibits voltage variations related to the magnitude of kinescope white current, which voltage variations are processed by the control circuits to develop a correction signal as required. As used herein, the expression "white current" refers to a high level of individual red, green or blue color image current, or to combined high level red, green and blue currents associated with a white image.
With the illustrated configuration of transistors 41 and 42 clamping voltage VA is relatively low, approximately +2.0 volts. The clamping voltage could be provided by a Zener diode rather than the disclosed arrangement of Darlington-connected transistors 41 and 42, but the disclosed clamping arrangement is preferred because Zener diodes with a voltage rating less than about 4 volts usually do not exhibit a predictable Zener threshold voltage characteristic, i.e., the "knee" transition region of the Zener voltage-vs-current characteristic is usually not very well defined. In addition, the disclosed transistor clamp operates with better linearity than a Zener diode clamp and radiates less radio frequency interference (RFI).
The relatively low clamping voltage is compatible with the analog input voltage requirements of the analog-to-digital converter (ADC) at the input of the control circuits which receive the sensed voltage at terminal A as will be explained in greater detail with respect to FIG. 2. In this example the ADC is intended to process analog voltages of from 0 volts to approximately +2.5 volts, and the clamping voltage assures that excessively high analog voltages are not presented to the ADC during normal video signal intervals.
The relatively low clamping voltage also assists to prevent transistor 30 from saturating, which is necessary since transistor 30 is intended to operate in a linear region. To achieve this result and to maximize the cathode current conduction capability of transistor 30, the clamping voltage should be as low as possible to maintain a suitably low bias voltage at the collector of transistor 30. On the other hand, the value of arc current limiting resistor 37a should be large enough to provide adequate arc protection without compromising the objective of maintaining the collector bias voltage of transistor 30 as low as possible. Operation of transistor 30 in a saturated state renders transistor 30 ineffective for its intended purpose of properly conveying video drive signals to the kinescope cathode, and for conveying accurate representations of cathode current to clamping network 40 particularly in the white current control mode when relatively high cathode current levels are sensed. In addition, undesirable radio frequency interference (RFI) can be generated by transistor 30 switching into and out of saturation. Also, when saturation occurs transistor base storage effects can result in video image streaking due to the time required for a transistor to come out of a saturated state.
Thus clamping network 40 advantageously limits the voltage at terminal A to a level tolerable by the analog-to-digital converter at the input of the control circuits coupled to terminal A, and protects the analog-to-digital converter input from damage due to signal overdrive. Network 40 also provides a collector reference bias for transistor 30 to prevent transistor 30 from saturating on large negative-going signal amplitude transitions at its emitter electrode. The clamping voltage level is readily adjusted simply by tailoring the values of resistors 43 and 44.
Capacitor 46 bypasses high frequency video signals to ground to prevent transistor 30 from saturating in response to such signals. Capacitor 46 also serves to smooth out undesirable high frequency variations at terminal A to prevent potentially troublesome signal components such as noise from interfering with the signal processing function of the input analog-to-digital converter of the control circuits, e.g., by smoothing the current sensed during the settling time of the analog-to-digital converter.
The latter noise reducing effect is particularly desirable, for example, when the input ADC of the control circuits coupled to terminal A is of the relatively inexpensive and uncomplicated "iterative approximation" type ADC, compared to a "flash" type ADC. The operation of an iterative ADC, wherein successive approximations are made from the most significant bit to the least significant bit, requires a relatively constant or slowly varying analog signal to be sampled during sampling intervals, uncontaminated by noise and similar effects.
The value of capacitor 46 should not be excessively large because a certain rate of current variation should be permitted at terminal A with respect to kinescope cathode currents being sensed. If the value of capacitor 46 is too small, excessive voltage variations, particularly high frequency video signal variations, will appear at terminal A, increasing the likelihood of transistor 30 saturating. The speed of operation of the clamp circuit itself is restricted by an RC low pass filter effect produced by the base capacitance of transistor 41 and the equivalent resistance of resistors 43 and 44.
FIG. 2 shows a portion of a color television receiver system employing digital video signal processing techniques. The FIG. 2 system utilizes kinescope driver amplifiers and a clamping network as disclosed in FIG. 1, wherein similar elements are identified by the same reference number. By way of example, the system of FIG. 2 includes a MAA 2100 VCU (Video Codec Unit) corresponding to video signal source 10 of FIG. 1, a MAA 2200 VPU (Video Processor Unit) 50, and a MAAA 2000 CCU (Central Control Unit) 60. The latter three units are associated with a digital television signal processing system offered by ITT Corporation as described in a technical bulletin titled "DIGIT 2000 VLSI DIGITAL TV SYSTEM" published by the Intermetall Semiconductors subsidiary of ITT Corporation.
In unit 10, a luminance signal and color difference signals in digital form are respectively converted to analog form by means of digital-to-analog converters (DACs) 70 and 71. The analog luminance signal (Y) and analog color difference signals r-y and b-y are combined in a matrix amplifier 73 to produce r, g and b color image representative signals which are processed by preamplifiers 75, 76 and 77, respectively, before being coupled to kinescope driver stages 15, 16 and 17 of the type shown in FIG. 1. A network 78 in unit 10 includes circuits associated with the automatic white current and black current control functions.
The high level R, G and B color signals from driver stages 15, 16 and 17 are coupled via respective current limiting resistors (i.e., resistor 33) to cathode intensity control electrodes of a color kinescope 80. Currents conducted by the red, green and blue kinescope cathodes are conveyed to network 40 via resistors 37a-37c, for producing at terminal A a voltage representative of kinescope cathode current conducted during measuring intervals, as discussed previously.
VPU unit 50 includes input terminals 15 and 16 coupled to terminal A. Through terminal 15 the VPU receives the analog signal from terminal A and, via an internal multiplex switching network 51, the analog signal is supplied to an analog-to-digital-converter (ADC) 52. Terminal 16 is connected to an internal switching device (corresponding to switch 49 in FIG. 1) which, in conjunction with scaling resistor 48, controls the impedance and therefore the sensitivity at input terminal 15. High sensitivity for black current measurement is obtained with resistor 48 ungrounded by internal switch 49, and low sensitivity for white current measurement is obtained with resistor 48 grounded by internal switch 49.
The digital signal from ADC 52 is coupled to an IM BUS INTERFACE unit 53 which coacts with CCU unit 60 and provides signals to an output data multiplex (MPX) unit 55. Multiplexed output signal data from unit 55 is conveyed to VCU unit 10, and particularly to control network 78. Control network 78 provides output signals for controlling the signal gain of preamplifiers 75, 76 and 77 to achieve a correct white current condition, and also provides output signals for controlling the DC bias of the preamplifiers to achieve a correct black current condition.
More specifically, during vertical image blanking intervals the three (red, green, blue) kinescope black currents subject to measurement and the three white currents subject to measurement are developed sequentially, sensed, and coupled to VPU 50 via terminal 15. The sensed values are sequenced, digitized and coupled to IM Bus Interface 53 which organizes the data communication with CCU 60. After being processed by CCU 60, control signals are routed back to interface 53 and from there to data multiplexer 55 which forwards the control signals to VCU 10.
ZANUSSI CHASSIS BS950 Digital signal peaking apparatus with controllable peaking level:
A digital signal peaking apparatus combines input digital signals with filtered and scaled representations thereof to produce controllably peaked digital signals. A digital filter produces the relatively higher frequency components of the input digital signals which are controllably scaled by a digital multiplier in accordance with a multiplier coefficient. A control arrangement develops the multiplier coefficient having a value determined in accordance with the peak magnitude of the higher frequency components of the input digital signals relative to the value of a peaking control level signal.
1. Digital signal processing apparatus comprising:
a source for providing digital input signals to be processed;
digital filtering means coupled to said source for developing filtered digital signals including relatively higher frequency components of said digital input signals;
scaling means coupled to said digital filtering means for scaling the magnitudes of said filtered digital signals in accordance with a scaling signal to develop scaled digital signals;
combining means, coupled to said source and to said scaling means, for combining said input digital signals and said scaled digital signals to produce processed digital signals; and
control means coupled to said digital filtering means for developing said scaling signal in response to said filtered digital signals and coupled to said scaling means for applying said scaling signal thereto.
2. The apparatus of claim 1 wherein said control means comprises comparing means for developing said scaling signal in response to the relative magnitudes of said filtered digital signals and of a control level signal.
3. The apparatus of claim 2 wherein said control means further comprises means for developing signals representative of the peak magnitude of said filtered digital signals and for applying said peak-representative signals to said comparing means.
4. The apparatus of claim 2 wherein said comparing means comprises detecting means for developing said scaling signal having first and second predetermined values corresponding to first and second non-overlapping ranges of the ratio of the magnitude of said filtered digital signals to that of said control level signal.
5. The apparatus of claim 4 wherein said detecting means comprises a first comparator developing said first predetermined value scaling signal in response to said ratio not exceeding approximately unity, and a second comparator developing said second predetermined value scaling signal in response to said ratio exceeding a value substantially greater than unity.
6. The apparatus of claim 4 wherein said detecing means includes counting means for storing a count therein from which said scaling signal is developed, wheren said counting means is set to first and second predetermined counts corresponding to said first and second predetermined values, respectively.
7. The apparatus of claim 4 wherein said comparing means further comprises second detecting means for developing said scaling signal having values intermediate said first and second predetermined values in accordance with values of said ratio in a range intermediate said first and second ranges thereof.
8. The apparatus of claim 7 wherein said comparing means includes counting means for storing a count therein from which said scaling signal is developed, wherein said counting means is set by said detecting means to fiist and second predetermined counts corresponding to said first and second predetermined values, respectively, and is responsive to said second detecting means for storing counts intermediate said first and second predetermined values.
9. The apparatus of claim 1 further comprising digital coring means interposed between said digital filtering means and said scaling means for coring a range of magnitudes of said filtered digital signals coupled to said scaling means.
10. Digital signal processing apparatus comprising:
a source for providing digital input signals to be processed;
digital filtering means coupled to said source for developing filtered digital signals including relatively higher frequency components of said digital input signals;
multiplying means coupled to said digital filtering means for controllably scaling the magnitudes of said filtered digital signals in accordance with the value of a multiplier coefficient to develop scaled digital signais;
first detecting means coupled to said digital filtering means for developing a detected signal repres entative of the peak magnitude of said filtered digital signals;
second detecting means coupled to said first detecting means for developing first signals indicating that said detected signal exceeds a range of values in a first sense and developing second signals indicating that said detected signals exceed said range of values in a second sense;
control means coupled to said second detection means for developing said multiplier coefficient having first and second values in response to said first and second signals, respectively, and developing said multiplier coefficient having values intermediate said first and second values in response to said detected signal; and
combining means coupled to said source and to said multiplying means for combining said digital input signals and said scaled digital signals to produce processed digital signals.
11. The apparatus of claim 10 wherein said control means includes counting means for storing a count therein from which said multiplier coefficient is developed, wherein said counting means is set to first and second predetermined counts corresponding to said first and second values, respectively, in response to said first and second signals, respectively.
12. The apparatus of claim 10 wherein said second detecting means includes:
first comparator means for comparing said detecied signals to a first control level signal to develop said first signals, said first control level signal representing one boundary of said range of values, and
second comparator means for comparing said detected signals to a second control level signal to develop said second signals, said second control level signal representing a second boundary of said range of value.
13. The apparatus of claim 12 wherein said control means includes counting means for storing a count therein from which said multiplier coefficient is developed, wherein said counting means is set to first and second predetermined counts corresponding to said first and second values, respectively, in response to said first and second signals, respectively.
14. The apparatus of claim 13 wherein said control means includes third detecting means for developing counting signals representative of the difference between the value of said detected signals and one of said first and second control level signals, and means for applying said counting signals to said counting means to change the count stored therein in accordance with said difference.
15. The apparatus of claim 12 including means for developing said second control level signal having a magnitude responsive to that of said first control level signal.
16. The apparatus of claim 10 wherein said control means includes counting means for storing a count therein from which said multiplier coefficient is developed, wherein said counting means is set by said first and second signals to first and second predetermined counts corresponding to said first and second values, respectively, and is responsive to said detected signal for storing counts intermediate said first and second predetermined counts.
17. The apparatus of claim 10 further comprising digital coring means interposed between said digital filtering means and said multiplying means for coring a range of magnitudes of said filtered signals coupled to said multiplying means.
18. A digital signal peaking system for controllably peaking relatively higher frequency signal components of digital input signals comprising:
a digital filter means to which said digital input signals are applied for producing filtered digital signals including said relatively higher frequency signal components;
peak detector means coupled to said digital filter means for developing a peak-level signal representative of the peak magnitude of said filtered digital signals;
digital counter means for producing a multiplier coefficient factor in accordance with a digital count stored therein;
first detector means, coupled to said peak detector means and to said digital counter means, for setting the stored digital count to a first predetermined value in response to said peak-level signal being greater than a first control value;
second detector means, coupled to said peak detector means and to said digital counter means, for setting the stored digital cou
nt to a second predetermined value in response to said peak level signal being less than a second control value;
third detector means, coupled to said peak detector means and to said digital counter means, for changing the stored digital count to a value intermediate said first and second predetermined values in accordance with the value of said peak-level signal intermediate said first and second control values;
digital multiplier means, coupled to said digital filter means and to said digital counter means, for scaling said filtered digital signals in accordance with said multiplier coefficient factor produced by said digital counter means;
delay means to which said digital input signals are applied for producing delayed digital signals in temporal alignment with corresponding scaled digital signals produced by said digital multiplier means; and
digital combining means, coupled to said digital multiplier means and to said delay means, for combining said delayed digital signals and said scaled digital signals to develop peaked digital signals.
19. The peaking system of claim 18 wherein said third detector means comprises means for developing counting signals representative of the difference between the values of said peak-level signal and of one of said first and second predetermined values, and means for applying said counting signals to said digital counting means to change the count stored therein in accordance with said difference.
Peaking is a signal processing operation in which higher frequency signal components are emphasized or deemphasized so as to adjust the overall signal frequency spectrum. It is useful where the higher frequency signal components have been undesirably attenuated by prior signal processing operations or apparatus. For television (TV) signals, for example, attenuation of higher frequency luminance signals causes undesirable loss of horizontal details in the reproduced picture. Such attenuation can be introduced by the RF tuner and amplifiers, the IF amplifiers or by the apparatus separating luminance and chrominance signal components. Fixed peaking arrangements are inadequate in a TV receiver because they cannot respond to changes in the received signals or the receiver performance and cannot be adjusted to suit viewer preference (which not only differs among viewers but which can differ for any one viewer in accordance with the program content).
Thus, it is desirable to provide a controllable peaking arrangement which can adjust the degree to which signals are peaked in response to a viewer-controllable setting and in response to changes in the condition of the signals being processed. When such peaking arrangements are employed in TV receivers, they tend to enhance the horizontal detail content of the reproduced pictures. Analog circuit arrangements providing such characteristics for TV receivers having analog signal processing are described in U.S. Pat. No. 4,437,123 entitled DYNAMICALLY CONTROLLED HORIZONTAL PEAKING SYSTEM filed on Apr. 30, 1982 by W. E. Harlan and U.S. Pat. No. 4,509,080 entitled VIDEO SIGNAL PEAKING SYSTEM filed on July 2, 1982 by W. A. Lagoni and W. E. Harlan, which are assigned to the same assignee as is the present invention.
In digital signal processing apparatus, however, a digital signal peaking apparatus must perform the peaking operation on signals which are digital numbers representing signal levels rather than directly upon the signal levels per se. Thus, digital circuitry must be employed to generate a peak-level representative digital signal, to develop a multiplier coefficient signal therefrom under certain digital signal conditions, and to develop peaked digital signals in response to the multiplier coefficient signal.
The analog peaking systems described in the patent applications referred to above employ a feedback arrangement including a bandpass filter for controlling the peaking level. In digital signal peaking apparatus, however, the ability to scale digital signals with predictability and accuracy permits avoidance of a feedback arrangement and the complexity associated therewith. Further, the band pass filter just referred to is eliminated.
Accordingly, the digital signal processing apparatus of the present invention comprises a digital filter producing certain frequency components of input digital signals which are scaled by a scaling device in accordance with a scaling signal and are combined with the input digital signals. A control arrangement develops the scaling signal in accordance with the certain frequency components of the input digital signals and applies the scaling signal to the scaling device.