SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) INTERNAL VIEW.

SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) CIRCUITS DESCRIPTIONS:



SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) Synchronized switch-mode power supply:

In a switch mode power supply, a first switching transistor is coupled to a primary winding of an isolation transformer. A second switching transistor periodically applies a low impedance across a second winding of the transformer that is coupled to an oscillator for synchronizing the oscillator to the horizontal frequency. A third winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a DC control voltage in the capacitor that varies in accordance with a supply voltage B+. The control voltage is applied via the transformer to a pulse width modulator that is responsive to the oscillator output signal for producing a pulse-width modulated control signal. The control signal is applied to a mains coupled chopper transistor for generating and regulating the supply voltage B+ in accordance with the pulse width modulation of the control signal.

Description:

The invention relates to switch-mode power supplies.

Some television receivers have signal terminals for receiving, for example, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR or a teletext decoder.

To simplify the coupling of signals between the external devices and the television receiver, the common conductors of the receiver and of the external devices are connected together so that all are at the same potential. The signal lines of each external device are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as of the television receiver, may be held "floating", or conductively isolated, relative to the corresponding AC mains supply source that energizes the device. When the common conductor is held floating, a user touching a terminal that is at the potential of the common conductor will not suffer an electrical shock.

Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials of the terminals of the AC mains supply source that provide power to the television receiver. Such isolation is typically achieved by a transformer. The isolated common conductor is sometimes referred to as a "cold" ground conductor.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled, for example, directly, and without using transformer coupling, to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced that is, for example, referenced to a common conductor, referred to as "hot" ground, and that is conductively isolated from the cold ground conductor. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of an isolating flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce a DC output supply voltage such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver. The primary winding of the flyback transformer is, for example, conductively coupled to the hot ground conductor. The secondary winding of the flyback transformer and voltage B+ may be conductively isolated from the hot ground conductor by the hot-cold barrier formed by the transformer.

It may be desirable to synchronize the operation of the chopper transistor to horizontal scanning frequency for preventing the occurrence of an objectionable visual pattern in an image displayed in a display of the television receiver.

It may be further desirable to couple a horizontal synchronizing signal that is referenced to the cold ground to the pulse-width modulator that is referenced to the hot ground such that isolation is maintained.

A synchronized switch mode power supply, embodying an aspect of the invention, includes a transfromer having first and second windings. A first switching arrangement is coupled to the first winding for generating a first switching current in the first winding to periodically energize the second winding. A source of a synchronizing input signal at a frequency that is related to a deflection frequency is provided. A second switching arrangement responsive to the input signal and coupled to the second winding periodically applies a low impedance across the energized second winding that by transformer action produces a substantial increase in the first switching current. A periodic first control signal is generated. The increase in the first switching current is sensed to synchronize the first control signal to the input signal. An output supply voltage is generated from an input supply voltage in accordance with the first control signal.


 

THOMSON  TEA2162 / TEA2164 / TEA2165  WORKING OF A CHOPPED POWER SUPPLY CONTROL CIRCUIT WITH AUTOMATIC START-UP:

 

 

Inventors: De Sartre, Jean (Meylan, FR) ; Thomson-csf (Paris, FR) 

 

 The invention provides an integrated chopped power supply control circuit intended to receive regulation control signals and to produce square waves for enabling a switch. It comprises automatic start up means producing, in the absence of regulation signals, bursts of start up attempts with a very low recurrence period. Each burst lasts about 10% of this period and is followed by a rest time.

  1. A chopped power supply control circuit intended to receive periodic regulation control signals and to produce periodic square waves enabling a main switch of the power supply, the square waves having a variable width as a function of their regulation control signals, which circuit comprises:

means for detecting the presence of regulation control signals,

a very low frequency oscillator controlled by the detection means, this oscillator producing, in the absence of regulation signals, a succession of very low frequency periodic cycles, the oscillator being inhibited by the regulation control signal detection means,

a high frequency oscillator producing chopping signals palliating the absence of regulation signals for producing enabling square waves,

an inhibition means for allowing transmission of the chopping siganls to the switch only during a first phase of each very low frequency periodic cycle and for preventing such transmission during the rest of the cycle, the first phase of each cycle having a duration which is long compared with the period of the high frequency oscillator and short compared with the period of the very low frequency oscillator.


2. The control circuit as claimed in claim 1, wherein said high frequency oscillator has a free oscillation period slightly greater than the period of the regulation control signals and it is synchronized by these signals when they are present.

3. The control circuit as claimed in claim 1, wherein the regulation control signals comprise a positive pulse followed by a negative pulse, one of them being used for synchronizing the high frequency oscillator, the positive pulse being transmitted through the inhibition means to a set input of a flip flop for triggering off the beginning of conduction of the main switch, and the negative pulse being transmitted to a reset input of the flip flop for causing stopping of the conduction of the switch.

4. The control circuit according to claim 1 further comprising:

a threshold comparator for receiving a signal measuring the current in said switch and for outputting a signal stopping the conduction of said switch when a threshold is exceeded;

means for varying the threshold of said comparator including a means for producing a first threshold value during normal operation of said circuit, a means for producing a second threshold value at the beginning of said first phase of said very low frequency cycle, said second threshold corresponding to a current in said switch which is lower than during said normal operation, and a means for producing a gradually decreasing threshold during said first phase of said very low frequency cycle.


5. The control circuit as claimed in claim 4, wherein said very low frequency oscillator is a relaxation oscillator delivering a saw tooth signal and the means for varying the threshold is driven by the output of the very low frequency oscillator.

6. The control circuit as claimed in one of claims 4 and 5, wherein another threshold converter is provided receiving a signal of measurement of the current in the main switch and delivering a signal for complete inhibition of enabling of the switch when the current in the switch exceeds a third threshold value higher than the first value.

7. The control circuit as claimed in claim 6, wherein said inhibition signal delivered by the other comparator is cancelled out when the circuit, after having partially or totally ceased to be supplied with power, is again normally supplied.

Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to stabilized power supplies called chopped power supplies.

A chopped power supply operates in the following way: a transformer primary winding receives a current which comes for example from a rectifier bridge receiving the power from the AC mains. The current in the transformer is chopped by a switch (for example a power transistor) placed in series with the primary winding.

A circuit controlling the transistor establishes periodic square waves for enabling the transistor. For the duration of the square wave the current is allowed to pass; outside the square wave, the passage of the current is prevented.

On one (or more) secondary windings of the transformer an AC voltage is then collected. This voltage is rectified and filtered so as to obtain a DC voltage which is the DC output voltage of the chopped power supply.

To stabilize the value of this DC voltage, the cyclic periodic conduction ratio of the switch is adjusted, that is to say the ratio between the conduction time and the disablement time in a chopping period.

2. Discussion of Background

In a chopped power supply architecture proposed by the applicant and shown in FIG. 1, two integrated circuits are used. One of the circuits, CI1, serves for controlling the base of a power transistor Tp for applying thereto periodic enabling and disabling control signals. The space control circuit CI1 is placed on the primary winding side (EP) of the transformer (TA) for reasons which will be better understood further on in the description. The integrated circuit, regulation circuit CI2, is on the contary placed on the secondary side (winding ES1) and its serves for examining the output voltage Vs of the power supply for elaborating regulation signals which it transmits to the first integrated circuit through a small transformer TX. The first integrated circuit CI1 uses these regulation signals for modifying the cyclic conduction ratio of the switching transistor TP and thus for regulating the output voltage Vs of the power supply.

We will come back in more detail hereafter to the circuit shown in FIG. 1.

Numerous problems arise during designing of a chopped power supply, and the problems with which we will be particulary concerned here are problems of starting up the power supply and problems of safety should over voltages or over currents occur at different points in the circuit. The first problem which is met with is that of starting up the power supply : on switching on, the regulation circuit CI2 will tend to cause the base control circuit CI1 to generate square waves of maximum cyclic ratio until the power supply has reached its nominal output voltage. This is all the more harmful since there is then a heavy current drain on the side of the secondary windings which are connected to initially discharged filtering capacitors. There is a risk of destruction of the power transistor through over-currents during the start-up phase.

Progressive start-up circuits have already been proposed which limit the duration of the enabling square waves during a start-up phase, on switching on the device; the U.S. Pat. No. 3,959,714 describes such a circuit in which charging of a capacitor from switch-on defines initially short square waves which gradually increase in duration until these square waves reach the duration which the regulation circuit normally assigns thereto. The short square waves have priority; but, since they become gradually longer during the start-up phase, after a certain time they cease to have priority; this time is defined by the charging time constant of the capacitor.

Another problem which arises is the risk of accidental overcurrents, or sometimes overvoltages which may occur in the circuit. These over-currents and over-voltages may cause damage and often result in the destruction of the power transistor if nothing is done to eliminate them. In particular, a short circuit at the output of the stabilized power supply rapidly destroys the power transistor. If the short circuit occurs on start-up of the power supply, it is not the gradual start-up system with short square waves which gradually increase which will allow the over-currents resulting from this short circuit to be efficiently accomodated.

Finally, another problem, particularly important in an architecture such as the one shown in FIG. 1, is the risk of disappearance of the regulation signals which should be emitted by the regulation circuit CI2 and received by the base control circuit CI1: these signals determine not only the width of the square waves for enabling the power transistor but also their periodicity; in other words, they serve for establishing the chopping frequency, possibly synchronized from a signal produced on the secondary side of the transformer. The disappearance of these signals causes a particular disturbance which must be taken into account.

Furthermore, the architecture of FIG. 1, in which the secondary circuits have been voluntarily separated galvanically from the primary circuits, is such that the base control circuit may function rapidly after switch on, as will be explained further on, whereas the regulation circuit CI2 can only function if the chopped power supply is in operation; consequently, at the beginning, the base control circuit CI1 does not receive any regulation signals and this difficulty must be taken into account.

SUMMARY OF THE INVENTION

In an attempt to resolve as well as possible the whole of these different problems which relate to safety against accidental disturbances in the operation of the power supply (initial start-up being able to be considered moreover as transitory disturbed operating phase), the present invention proposes an improved chopped power supply control circuit which accomplishes a function of gradual start-up of the power supply on switch-on and a function of passing to the safety mode should a malfunction occur such as a disappearance of appropriate regulation signals: the safety mode consists of a succession of very low frequency periodic cycles, each cycle consisting in a gradual start-up attempt during a first phase which is short compared with the period of the cycle and long compared with the chopping period of the chopped power supply, the first phase being followed by a pause at the end of the cycle, and periodic cycles succeeding each other until normal operation of the power supply is established or re-established; a very low frequency oscillator establishes these cycles when the power supply is not normal operating conditions (start up or malfunction); this oscillation is disabled when normal operation is ascertained; a high frequency oscillator generates a burst of chopping signals palliating the absence of regulation signals; these signals are transmitted solely during the first phase of each cycle; they are inhibited during the second phase.

According to a very important characteristic of the invention; gradual start-up operates not by limiting the duration of the square waves from the charging of a capacitor with a fixed time constant, but by limiting the current in the power transistor to a maximum value, this maximum value increasing gradually during the start-up phase, overshooting of this current value causing interruption of the power transistor.

Thus, even in the case of a quasi short circuit, the value of a current in the transistor is limited, which was not the case in gradual start-up circuits of the prior art.

More precisely, the chopped power supply control circuit, intended to receive periodic regulation control signals and to produce periodic square waves for enabling a main switch of the power supply, the square waves having a variable width depending on the regulation control signals; comprises:

a means for detecting the presence of regulation control signals,

a very low frequency oscillator controlled by the detection means, this oscillator establishing, in the case of absence of regulation signals, a succession of very low frequency periodic cycles, the oscillator being inhibited by the detection means when regulation control signals are present,

a high frequency oscillator producing chopping signals palliating the absence of regulation signals for producing enabling square waves,

an inhibition means only allowing chopping signals to be transmitted to the switch during a first phase of each very low frequency periodic cycle and for preventing such transmission during the rest of the cycle, the first phase of each cycle having a duration which is long compared with the period of the high frequency oscillator and short compared with the period of the very low frequency oscillator.

Preferably, the high frequency oscillator has a free oscillation period slightly greater than the period of the regulation control signals and it is synchronized by these signals when they are present.

The regulation control signals may comprise a positive pulse followed by a negative pulse, one of them serving for synchronizing the high frequency oscillator, the positive pulse being transmitted through the inhibition means to a set input of a flip flop for enabling the switch, whereas the negative pulse is transmitted to the reset input of this flip flop for disabling.

In so far as limiting the current to a gradually increasing value during the start-up cycles is concerned, a threshold comparator (92) is preferably provided receiving a signal for measuring the current in the switch in order to generate a signal for disabling the switch should the threshold be exceeded and a means (90) for causing the threshold of the comparator to vary in the following way:

under normal operating conditions the threshold is fixed at a first value;

at the beginning of the first phase of each very low frequency periodic cycle, the threshold passes suddenly from the first value to a second value corresponding to a lower current in the switch;

during the first phase of each cycle the threshold passes gradually back from the second value to the first one.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the invention will be clear from the following detailed description made with reference to the accompanying drawings in which:

FIG. 1 shows a general chopped power supply diagram using two integrated circuits placed respectively on the primary side and on the secondary side of a transformer,

FIG. 2 shows a diagram of an integrated circuit for controlling the power transistor placed on the primary side,

FIGS. 3 to 6 show timing diagrams of signals at different points of the circuit, and

FIG. 7 shows a circuit detail for producing a variable threshold.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring again to FIG. 1, which represents a chopped power supply architecture given by way of example illustrating the utility of the invention, the line of the public electric mains has been designated by the reference 10 (mains at 100 or 220 volts, 50 or 60 hertz). This line is connected through a filter 12 to the input of a rectifier bridge 14 whose output is connected on the one hand to a primary electric ground, shown throughout by a black triangle pointing downward and, on the other hand, to one end of the primary winding EP of the power transformer TA.

A filtering capacitor 16 is placed in parallel across the outputs of the rectifier bridge 14. The other end of the primary winding is connected to the collector of a switching transistor TP whose emitter is connected to the primary ground through a small current measuring resistor 18.

The transformer has several secondary windings which are preferably isolated galvanically from the mains and connected for exmaple to a secondary electric ground isolated galvanically from the primary ground.

Here, each of the secondary windings has one end connected to the secondary ground. The other end feeds a respective low pass filtering capacitor through a respective rectifier diode.

The description hereafter will refer to a single secondary winding ES1, connected by a diode 20 to a capacitor 22. The DC output voltage of the chopped power supply is the voltage Vs at the terminals of the capacitor 22; but of course other DC output voltages may be obtained at the terminals of the other filtering capacitors connected to secondary windings. These output voltages forms stabilized power supply voltages for user circuits not shown. By way of example, a secondary winding ES2 supplies a stabilized voltage of a few volts for the integrated regulation circuit CI2, which has already been discussed. It can be verified therefore in this connection that this circuit is not fed with power and cannot therefore deliver signals as long as the chopped power supply is not operating.

The same goes a priori for the integrated circuit CI1 controlling the base of the power transistor TP, which circuit is supplied with a stabilized voltage delivered from a secondary winding ES3, a diode 24 and a capacitor 26 (it will be noted in passing that this winding, although a secondary winding, is connected to the primary ground and not to the secondary ground, for the very simple reason that the integrated circuit CI1 is necessarily coupled galvanically to the primary).

However, since start-up of the chopped power supply must be ensured, it is provided for the power supply terminal 28 of the integrated circuit CI1 to be also connected directly to the mains through a high resistor 30 and a diode 32; this is possible since the integrated circuit CI1 is connected to the primary gorund; this is not possible for the integrated circuit CI2 which must remain galvanically isolated from the mains. As soon as the chopped power supply is operating normally, the stabilized DC voltage delivered by winding ES3 and diode 24 take precedence over the voltage from the mains and diode 32; this diode 32 is disabled and the direct supply from the mains no longer occurs after the initial start-up phase.

The role of integrated circuits CI1 and CI2 will now be described.

The regulation circuit CI2 receives, from a divider bridge 34 placed at the terminals of the capacitor 22 that is to say at the output of the stabilized power supply, information concerning the value of the voltage to be stabilized Vs.

This information is compared with a reference value and applied to a pulse width modulator which produces periodic square waves of variable width depending on the value of the output voltage Vs; the lower Vs the wider the square waves.

The square waves are produced at the chopping frequency of the chopped power supply. This frequency is therefore established on the secondary side of the circuit; it is generated either inside circuit CI2, or outside in a circuit not shown, in the form of a saw tooth voltage at the chosen chopping frequency. This saw tooth voltage is used in a way known per se for obtaining width modulation.

The variable width square waves, at the chopping frequency, are applied to a primary winding 36 of a small transformer TX whose secondary winding 38, isolated galvanically from the primary, delivers positive and negative pulses at the rising and falling fronts respectively of the variable width square waves.

It is these pulses, whose position and frequency are determined by the regulation circuit CI2, which form regulation signals applied to an input 40 of the base control circuit CI1.

Transformer TX is formed by a few turns wound on a ferrite rod, the turns of the primary and the turns of the secondary being sufficiently spaced apart from each other for complying with the standards of galvanic isolation between primary circuits and secondary circuits in the chopped power supply.

The integrated base control circuit CI1 comprises different inputs among which have already been mentioned a power supply input 28 and a regulation signal input 40; a current measuring input 44 is connected to the current measuring resistor 18; an inhibition input monitors the magnetization condition of a transformer. Finally, inputs may be provided for connecting elements (resistors, capacitors) which should form part of the integrated circuit itself but which, for technological reasons (space) or for practical reasons (possiblities of adjustment by the user) are mounted on the outside.

The integrated circuit CI1 finally comprises an output 46 which is intended to be coupled by direct galvanic coupling to the base of the power transistor Tp. This output delivers square waves for enabling and disabling the transistor Tp.

FIG. 2 shows the general architecture of the integrated circuit CI1, limited to the elements which relate more particularly to the invention.

The output 46 of the circuit is the output of a push-pull amplification stage designated as a whole by the reference 48, this stage comprising preferably two separate amplifiers one of which receives enabling square waves and the other of which receives disabling signals formed by enabling square waves inverted and delayed by a few microseconds. Such amplifiers are now well known.

The enabling signals are delivered by a logic flip flop 50 having a set input 52 and a reset input 54. The set input causes the power transistor to be enabled. The reset input causes it to be disabled.

The set input 52 receives the pulses which pass through a logic AND gate 58, so that enabling only occurs if several conditions are simultaneously satisfied; one unsatisfied condition will be sufficient to inhibit enabling.

The reset input 54 receives the pulses which pass through a logic OR gate 60, so that disabling (after enabling) will occur as soon as a disabling signal is present at one of the inputs of this gate.

In the diagram of FIG. 2, the AND gate 58 has three inputs. One of these inputs receives periodic pulses from an output 62 of a high frequency oscillator 64; the other inputs serve for inhibiting the transmission of these pulses.

The oscillator defines the periodicity of the chopping of the power supply (20 kilohertz for example). Under normal operating conditions, the oscillator is synchronized by the regulation signals; under start-up conditions, it is self oscillating at a free frequency defined by the values of a resistor Ro and a capacitor Co external to the integrated circuit CI1 and connected respectively to an access terminal 66 and an access terminal 68. The free frequency fo is in theory slightly lower than the normal chopping frequency.

Oscillator 64 is a relaxation oscillator which produces at an output 70 a saw tooth whose zero return is caused by the appearance of a positive pulse arriving at terminal 40. This is why oscillator 64 is shown with one input connected to an output 72 of a separation and shaping circuit 74 which receives the regulation signals from terminal 40 and shapes them while separating the positive pulses from the negative pulses. The shaping circuit 74 has two outputs; 72 for the positive pulses, 76 for the negative pulses (the notation of positive pulses, negative pulse will be kept for distinguishing the enabling pulses and the disabling pulses even if the shaping circuit produces pulses of the same sign at both its outputs 72 and 76).

Oscillator 64 has two outputs: one output 70 delivering a saw tooth and one output 62 delivering a short pulse at the time of the zero return of the saw tooth.

A pulse width modulator 78 is connected on the one hand to the output 70 of the oscillator and on the other to a reference voltage adjustable by means of a resistor R1 external to the integrated circuit and connected to a terminal 80 giving access to the circuit. Modulator 78 delivers periodic square waves synchronized with the signals of the oscillator, these square waves defining a maximum conduction duration Tmax beyond which the power transistor must be disabled in any case for safety reasons. These square waves and modulator 78 are applied to an input of the OR gate 60. The duration Tmax is adjustable by means of the external resistor R1.

The elements which have just been described ensure the essential part of the operation under normal conditions of the integrated circuit CI1. The following elements are more specifically provided for controlling abnormal operation or start-up of the power supply.

A very low frequency oscillator 82 is connected to an external capacitor C2 through an access terminal 86. This external capacitor allows the very low frequency oscillation to be adjusted. The frequency may be 1 hertz for example.

Oscillator 82 is a relaxation oscillator delivering a saw tooth. This saw tooth is applied on the one hand to a threshold comparator 88 which causes periodic square waves to be produced synchronized with the very low frequency saw tooth of the oscillator. These square waves have a brief duration compared with the period of a saw tooth; this duration is fixed by the threshold of comparator 88; it may be for example be 10% of the period; it must be long compared with the free oscillation period of the high frequency oscillator 64 so that a burst of numerous pulses from the high frequency oscillator may be emitted and used during this 10% of the very low frequency period; this burst defines at start-up attempt during the first part of a start-up cycle; it is followed by a pause during the rest of the period, i.e. during the remaining 90%.

The oscillator only serves at start up; it is inhibited when regulation signals appear at terminal 40 and indicate that the chopped power supply is operating. This is why a control has been shown for inhibiting this oscillator, connected to the output 72 of the shaping circuit 74 through a flip flop 89. This flip flop switches under the action of the pulses appearing at the output 72. It is brought back to its initial state by the output 62 of oscillator 64 when there are no longer any pulses at output 71.

The saw teeth of the very low frequency oscillator are further transmitted to a circuit 90 producing a variable threshold whose purpose is to produce a threshold signal (current or voltage) having a first value Vs1 under normal operating conditions, and a threshold cyclically variable between a first value and a second value under start-up conditions. The method of varying this threshold will be described further on, but it may already be noted that the variation is driven by the very low frequency saw tooth.

The threshold signal produced by circuit 90 is applied to an input of a comparator 92 another input of which is connected to the terminal 44 already mentioned, for receiving at this input a signal representative of the amplitude of the current flowing through the power switch. The output of comparator 92 is applied to an input of the OR gate 60. It therefore acts for disabling the power transistor Tp, after it has been enabled, disabling occurring as soon as overshooting of the threshold (fixed or variable) defined by circuit 90 has been detected.

Another threshold comparator 94 has one input connected to the current measuring terminal 44 whereas another input receives a signal representing a third threshold value Vs3. The third value Vs3 corresponds to a current in the switch higher than the first value Vs1 defined by the circuit 90. The output of comparator 94 is connected through a storage flip flop 96 to an input of the AND gate 58 so that, if the current in the power switch exceeds the third threshold value Vs3, disabling of transistor Tp is not caused (such disabling being caused by the comparator 92) but any new enabling of the transistor is inhibited. Such inhibition lasts until the flip flop 96 is switched back to its initial state corresponding to normal operation.

In theory, this resetting will only take place when the integrated circuit CI1 has ceased to be supplied normally with power and is again switched on. For example, resetting of flip flop 96 is caused through a hysteresis threshold comparator 98 which compares a fraction of the power supply voltage Vcc of the circuit (taken from terminal 28) with a reference value and which resets the flip flop when Vcc first passes above this reference after dropping below another reference value lower than the first one (hysteresis).

Finally, it may be stated that the output of the flip flop 89 (which detects the presence of regulation signals at terminal 40 therefore normal operation of the power supply), is connected to an input of an OR gate 100 which receives at another input the output of comparator 88 so that the output of comparator 88 ceases to inhibit enabling of transistor Tp (inhibition during 90% of the very low frequency cycles) as soon as operation of the power supply has become normal.

OPERATION OF THE BASE CONTROL CIRCUIT

This operation will be described by illustrating it with voltage wave forms inside the chopped power supply and inside the integrated circuit CI1.

(a) Start-up on switching on

At the outset, the integrated circuit is not supplied with power at all.

The voltage at the power supply terminal 28 increases from 0 to a value Vaa which is not the nominal value Vcc but which is a lower value supplied by diode 32 and resistor 30 (cf. FIG. 1) as long as the chopped power supply does not deliver its nominal output voltage Vcc at terminal 28. Vaa is a voltage sufficient for ensuring practically normal operation of all the elements of the circuit CI1. Vaa is also sufficient for reinitializing the flip flop 96 which, as soon as that happens, no longer inhibits enabling of the power transistor Tp.

There are no regulation signals at the input 40. Consequently, the high frequency oscillator oscillates with its free frequency and the very low frequency oscillator also oscillates (it is not inhibited by the flip flop 89 since this latter does not receive any regulation signals from the output 72 of the shaper circuit 74).

The very low frequency oscillator 82 and comparator 88 define periodic cycles of start-up attempts repeated at a very low frequency.

Each cycle comprises a first part defined by the square waves of short duration at the output of comparator 88, and a second part formed by the end of the very low frequency period; the first part is an effective attempt at start-up. The second part is a pause if the effective attempt has failed. The pause lasts much longer than the effective attempt so as to limit power consumption.

During the first part of the cycle, the enabling signals delivered by the high frequency oscillator 64 are allowed to pass through the AND gate 58. They are then prevented from passing. Each pulse from the output 62 of the oscillator 64 enables the transistor Tp. There is therefore a burst of enabling pulses which is emitted for about 10% of the very low frequency period.

During start-up, the current intensities in the transistor tend to be very high. It is essentially comparator 92 which causes interruption of the conduction, after each enabling pulse delivered by oscillator 64, as soon as the current exceeds the threshold imposed by the variable threshold elaboration circuit 90. If comparator 92 does not cause enabling, modulator 78 will do so in any case at the end of the time Tmax.

The threshold elaboration circuit, which delivers to the comparator 90 a first fixed threshold value Vs1 under normal operating conditions (i.e. when the very low frequency oscillator 82 is disabled by the flip flop 89), delivers a variable threshold as a function of the saw tooth of the very low frequency oscillator in in the following way:

at the initial outset of a start-up attempt cycle (beginning of the saw tooth or zero return of the preceding saw tooth), the threshold passes suddenly from the first value Vs1 to a second value Vs2 corresponding to a lower current than the first value, then this threshold increases gradually (because driven by the very low frequency saw tooth) from the second value to the first. The growth time coincides preferably with the duration of a start-up attempt square wave (i.e. about 10% of the very low frequency period).

Then the threshold is stabilized at the first value Vs1 until the end of the period, but in any case if the circuit has not started up at that time, comparator 88 closes gate 58, through the OR gate 100 and inhibits any further enabling of the power transistor during the rest of the very low frequency period (90%). It is then the second part of the start-up attempt cycle which takes place: a pause during which the pulses of oscillator 64 are not transmitted through the AND gate 58.

Thus, the start-up cycles act from two points of view: on the one hand, a burst of enabling pulses is emitted (10% of the time) then stopped (90% of the time) until the next cycle; on the other hand, during this burst, the current limitation threshold passes gradually from its second relatively low value to its normal higher value.

Consequently, if the peak amplitude of the current in transistor Tp is observed during the start-up bursts, it can be seen that in practice it increases linearly from the second value to the first. Thus gradual start-up is obtained by a much more efficient action than that which consists simply for example in causing the duration Tmax to increase from a low value to a nominal value.

If start-up is not successful, a new burst of enabling pulses is transmitted during the first part of the next cycle (it will be recalled that this cycle is repeated about once per second and that the burst may last 100 milliseconds).

If start-up is successful, regulation signals appear at terminal 40. These signals are shaped by circuit 74. They cause the very low frequency oscillator 82 to be stopped by the flip flop 89 which prevents the zero return of the saw tooth. Furthermore, flip flop 89 sends through the OR gate 100 a signal for cancelling out the inhibition effect imposed by the comparator 88. Finally, as soon as start-up is successful, the regulation signals cause the high frequency oscillator 64 to be synchronized.

FIG. 3 illustrates the high frequency signals during the start-up period:

line a: saw tooth at the output 70 of the oscillator 64 (free oscillation at frequency fo, period To),

line b: pulses for enabling the transistor Tp : these pulses coincide with the zero return of the saw tooth signal (output 62 of oscillator 64);

line c: output square waves from modulator 78 defining the maximum cyclic conduction time of the transistor,

line d: pulses delivered comparator 92 when the current in the switch exceeds the threshold (gradually increasing during start up) defined by the circuit 90.

The conduction of transistor Tp, after being enabled by a pulse from line b, is stopped either by the square waves of line c if the current threshold is not exceeded, or by an output pulse from comparator 92.

FIG. 4 shows the very lwo frequency signals during the start-up cycles. The diagrams are not to the same time scale as in FIG. 3 since it will be recalled that an example of the frequency of the high frequency oscillator 64 is 20 kilohertz whereas an example of the very low frequency of oscillator 82 is 1 hertz. The high frequency pulses have however been shown symbolically in FIG. 4, in number more limited than in reality for facilitating the representation.

line e: saw tooth output of the very low frequency oscillator (frequency f2, period T2),

line f: output of comparator 88 showing the first phase (start-up attempt by allowing conduction of transistor Tp) and the second phase (pause by inhibiting the conduction of each very low frequency start up cycle,

line g: pulses delivered by the freely oscillating high frequency oscillator,

line h: bursts of enabling pulses at the output of the AND gate 58,

line i: diagram of the cyclic variation of the threshold produced by circuit 90 during the start-up cycles: fixed value Vs1 in theory, sudden drop to Vs2 at the beginning of the very low frequency saw tooth, and gradual rise from Vs2 to Vs1, driven by the linear growth of the saw tooth, during the start-up burst.

(b) Operation of the power supply under normal established operating
conditions

The very low frequency oscillator is not operating.

The high frequency oscillator is synchronized by the regulation signals.

The zero return of the high frequency saw tooth, coinciding with the positive pulses of the regulation signals, causes enabling of transistor Tp (no inhbition by the AND gate 58 during normal operating conditions). The negative pulses cause disabling, through the OR gate 64, except if such disabling has been caused:

either by overshooting of the first current threshold value, detected by the comparator 92,

or by the modulator 78 if the time interval between the positive pulse and the negative pulse which immediately follows it is greater than the maximum duration Tmax which is allowed.

FIG. 5 shows the high frequency signals under normal operating conditions,

line j: alternate positive and negative pulses received at the input 40 of the circuit (these are the regulation signals defining the times at the beginning and end of conduction of the power transistor Tp),

line k: shaped pulses at the output 72 of the separation and shaping circuit 74: they correspond to the positive pulses only of the regulation signals,

line l: saw tooth at the output 70 of oscillator 62; the saw tooth is synchronized with the regulation signals in that its zero return coincides with the pulses of line k,

line m: pulses at output 62 of oscillator 64; these pulses are emitted during zero returns of the saw tooth of line l,

line n: output square waves of modulator 78 further defining the maximum conduction time of the power transistor;

line o: pulses from the output 76 of the separation and shaping circuit 74: these pulses correspond to the negative pulses of the regulation signals,

line p: as a reminder, pulses have been shown at the output of comparator 92 in the case where the current in the power transistor exceeds the threshold corresponding to Vs1.

The conduction of transistor Tp, after being enabled by a pulse of line k, is normally stopped by the pulse from line o which immediately follows it, or, more exceptionally by the pulses from line p if the threshold Vs1 is exceeded before the apearance of the pulse of line o, or else, by the square waves of line n if the threshold is not exceeded and if the pulse of line o appears after the beginning of a square wave of line n.

FIG. 6 shows the very low frequency signals at the time of passing over from start-up conditions to normal operating conditions (same scale as FIG. 4).

line q: regulation signals at the input 40; these signals are initially absent and appear at a certain moment,

line r: output of the flip flop 89 indicating the absence then the presence of regulation signals,

line s: very low frequency saw tooth which rises to its high level and does not drop again if the output o the flip flop 89 is at the high level (indicating the presence of regulation signals)

line t: output of the OR gate 100 showing initially a square wave of short duration, delivered by comparator 88 and causing a start-up burst (cf. FIG. 4), then blocking at the high level which prevents subsequent inhibition of the AND gate 58 by the comparator 88.

(c) Safety mode in the case of a malfunction

The safety mode consists in fact in establishing start-up cycles as during switch on.

These cycles are triggered by start up of the very low frequency oscillator 82 when the regulation signals disappear at input 40.

Flip flop 89 returns to an intial state when it no longer receives pulses from the output 72 of the separation and shaping circuit 74. Thus, oscillator 82 will be able to oscillate again and the above described cycles are established.

(d) Serious incident: very high over current

Whatever the operating conditions, normal or start-up, over-currents in transistor Tp are detected by the comparator 92 and cause interruption of the conduction. But if there is for example a short circuit at the output of the power supply, an over-current may occur such that the current continues to increase before the conduction has time to be completely interrupted. In this case, it is provided for the threshold comparator 94 to deliver an order inhibiting the enabling when the current in transistor Tp exceeds a third threshold value which is for example greater by 30% than the first value. This inhibition order is stored by flip flop 96 which switches under the action of the comparator and disables the AND gate 58; flip flop 96 can only come back to its initial state when the integrated circuit, after having partially or totally ceased to be supplied with power, is again normally supplied. For example, the power supply must be switched off and switched on again to allow pulses to pass again for enabling the transistor Tp.

To finish this description, there has been shown in FIG. 7 one example of the circuit 90 which produces a variable threshold for the comparator 92: the very low frequency saw tooth deliveredy by the oscillator is applied to a voltage/current converter 102 which produces a saw tooth current increasing from 0 to a maximum value.

This current is applied to a series assembly of a voltage source 104 (value Vs2) and a resistor 106. A voltage clipper, represented by a Zener diode 108 (value of the conduction threshold: Vs1) is connected in parallel across the assembly 104, 106. The junction point between the output of the converter 102, resistor 106 and the voltage clipper 108 forms the output of circuit 90 and is connected to the input of comparator 92. Thus, when the saw tooth returns to zero, the output voltage of circuit 90 is Vs2. Then it increases as the current in the resistor 106 increases (linearly). When the voltage at the terminals of resistor 106 reaches and exceeds the value Vs1-Vs2, the voltage clipper conducts and diverts the current surplus so that the output voltage remains limited to Vs1.

 

 

 

  THOMSON  TEA2162 / TEA2164 / TEA2165  WORKING OF CONTROL CIRCUIT FOR A CHOPPED POWER SUPPLY WITH PROGRESSIVE START UP :

A chopped power supply control circuit is provided intended to receive regulation control signals and to produce square waves for enabling a switch. A current comparator measures the current in the switch and opens the switch when the threshold is exceeded. Under normal operating conditions the threshold is fixed. Under start-up conditions of should a malfunction occur a threshold variation circuit causes the threshold to vary gradually from a low value to its normal value. Thus the risk of over-current at start-up is reduced.

Inventors: De Sartre, Jean (Meylan, FR)  ;  Maige, Philippe (Syssinet Pariset, FR) Thomson-csf (Paris, FR)

 1. A chopped power supply control circuit intended to receive regulation control signals and to produce square waves for enabling a mains switch of the power supply, wherein said square waves having a variable width depending on the signals received, said circuit comprising:

a current limiting circuit including a threshold comparator receiving at one input a signal and at another input a threshold signal;

a means for said comparator to generate a signal for disabling the switch when the threshold is exceeded, in order to ensure gradual start-up of the chopped power supply at the beginning of its operation and in the case of a disturbance of operation;

a means for establishing a variable threshold signals in response to circuit means which

establish a first fixed threshold value under normal established operating conditions,

establish periodically a threshold variation cycle in the opposite case, this cycle comprising

means to cause the threshold to pass to a second value at a time representing the beginning of a periodic threshold variation cycle, the second threshold value corresponding to a lower current in the switch,

means to bring the threshold gradually back from the second value to the first in a first part of the threshold variation cycle,

means for maintaining the threshold at the first value until the end of the current cycle,

means to begin a second start-up cycle again at the end of the current cycle if regulation control signals are still not received at the end of the first cycle,

means for stopping the establishment of threshold variation cycles when regulation control signals are received.


2. The control circuit as claimed in claim 1 wherein the first part of each periodic cycle corresponds to a short time compared with the period of the cycle and a long time compared with the switching period of the chopped power supply.

3. The control circuit as claimed in claim 1, wherein a very low frequency oscillator is provided for defining the periodic two phase threshold variation cycles, said oscillator being inhibited by the reception of appropriate regulation control signals.

4. The control circuit as claimed in claim 3, wherein said very low frequency oscillator is a relaxation oscillator delivering a saw tooth signal driving the threshold establishment means for establishing:

a sudden variation of the threshold at the time of the zero return of the saw tooth,

a slow linear increase of the threshold at the beginning of the saw tooth.


5. The control circuit as claimed in claim 4, wherein a high frequency oscillator is provided producing chopping signals palliating the absence of regulation signals for the production of square waves enabling the switch and an inhibition means for allowing transmission of these signals only during the first phase of each periodic cycle.

6. The control circuit as claimed in claim 5, wherein said high frequency oscillator has a free oscillation period slightly greater than the period of the regulation control signals and it is synchronized by these signals when they are received.

7. The control circuit as claimed in claim 1, wherein a second threshold comparator is provided for receiving a signal representative of the current in the switch and delivering a signal completely inhibiting enabling of the switch in the case where the current in the switch exceeds a third threshold value greater than the first value, the signal only ceasing when the circuit, after having partially or totally ceased to be supplied with power, is again normally supplied.

Description:

BACKGROUND OF THE INVENTION

The present invention relates to stabilized power supplies called chopped supplies.

A chopped power supply operates in the following way: a primary transfer winding receives a current which is for example delivered by a rectifier bridge receiving the power of the AC mains. The current in the transformer is chopped by a switch (for example a power transistor) placed in series with the primary winding.

A circuit for controlling the transistor produces periodic square waves for enabling the transistor. A current is allowed to pass for the duration of the square waves; outside the square wave, the current cannot pass.

On one (or more) secondary windings of the transformer, an AC voltage is collected. This is rectified and filtered so as to obtain a DC voltage which is the output DC voltage of the chopped power supply.

For stabilizing the value of this DC voltage, the cyclic period conduction ratio of the switch is adjusted, that is to say the ratio between the duration of conduction and the duration of non conduction in a chopping period.

In chopped power supply architecture proposed by the applicant and shown in FIG. 1, two integrated circuits are used. One of the circuits CI1, serves for controlling the base of a power transistor Tp for applying thereto periodic enabling and disabling control signals. The base control circuit CI1 is placed on the primary winding side (EP) of the transformer (TA) for reasons which will be better understood in the rest of the description. The other integrated circuit, regulation circuit CI2, is on the contrary placed on the secondary side (winding ES1) and it serves for examining the output voltage Vs of the power supply for forming regulation signals which it transmits to the first integrated circuit through a small transformer TX. The first integrated circuit CI1 uses these regulation signals for modifying the cyclic conduction ratio of the switching transistor Tp and thus regulating the output voltage Vs of the power supply.

We will come back further on in more detail to the circuit of FIG. 1.

Numerous problems arise during the design of a chopped power supply, and here we will consider more particularly the problems of starting up the supply and the problems of safety in the case of over voltages or over currents at different points in the circuit.

The first problem which is met with is that of starting up the power supply: at switch on, the regulation circuit CI2 will tend to cause the base control circuit CI1 to generate maximum cyclic ratio square waves until the power supply has reached its nominal output voltage. This is all the more harmful since there is a high current drain on the side of the secondary windings which are connected to initially discharged filtering capacitors. There is a risk of destruction of the power transistor through an overcurrent during the start up phase.

Circuits for gradual start up have already been proposed which limit the duration of the enabling square waves during a start up phase, on switching on the device; the U.S. Pat. No. 3,959,714 describes such a circuit in which charging of a capacitor from switch-on defines initially short square waves of gradually increasing duration until these square waves reach the duration which the regulation circuit normally assigns to them. The short square waves have priority; but, since they become gradually longer during the start up phase, they cease to have priority after a certain time; this time is defined by the charging time constant of the capacitor.

Another problem to be reckoned with is the risk of accidental over-currents, or sometimes over-voltages which may occur in the circuit. These overcurrents and over-voltages may be very detrimental and often result in the destruction of a power transistor if nothing is done to eliminate them. In particular, a short circuit at the output of the stabilized power supply rapidly destroys the power transistor. If this short circuit occurs on switching-on of the supply, it is not the gradual start up system with short and progressively increasing square waves which can efficiently accomodate the over-currents which result from this short circuit.

Finally, another problem particularly important in an architecture such as the one shown in FIG. 1, is the risk of disappearance of the regulation signal which should be emitted by the regulation circuit CI2 and received by the base control circuit CI1: these signals determine not only the width of the square waves enabling the power transistor but also their periodicity; in other words, they serve for establishing the chopping frequency, possibly synchronized from a signal produced on the secondary side of the transformer. The appearance of these signals causes a particular disturbance which must be taken into account.

Furthermore, the architecture shown in FIG. 1, in which the secondary circuits have been voluntarily separated galvanically from the primary circuits, is such that the base control circuit may operate rapidly after switch-on, as will be explained further on, whereas the regulation circuit CI2 can only operate if the chopped power supply is operating; consequently, at the beginning, the base control circuit CI1 does not receive any regulation signals and this difficulty must be taken into account.

SUMMARY OF THE INVENTION

To try and overcome as well as possible all these different problems which relate to security against accidental disturbances in the operation of the power supply (the initial start up being more-over considered as a transitory disturbed operating phase), the present invention provides an improved chopped power supply control circuit which provides a function of gradual start-up power supply on switch on and a function of passing to a safety mode in the case of an operating defect such as a disappearance of appropriate regulation signals; the safety mode consists of a succession of periodic cycles at a very low frequency, each cycle consisting of a gradual start-up attempt during a first phase which is short in comparison with the period of the cycle and long compared with the chopping period of the chopped power supply, the first phase being followed by a pause until the end of the cycle, and periodic cycles succeeding each other until normal operation of the power supply is established or re-established; a very low frequency oscillator establishes these cycles when the power supply is not operating under normal conditions (start-up or operating defect); this oscillator is disabled should normal operation be ascertained; a high frequency oscillator generates a burst of chopping signals palliating the absence of regulation signals; these signals are transmitted solely during the first phase of each cycle; they are inhibited during a second phase.

According to a very important characteristic of the invention, the gradual start up operates not by limiting the duration of the square waves from the charging of a capacitor with a fixed time constant, but by limiting the current in the power transistor to a maximum value, this maximum value increasing progressively during the start up phase, over-shooting of this current value causing interruption in the conduction of the power transistor.

Thus, even in the case of a quasi short circuit, the value of the current in the transistor is limited, which was not the case in the gradual start up circuits of the prior art.

More precisely, the chopped power supply control circuit of the invention is intended to receive regulation control signals and to produce square waves for enabling a main switch of the power supply, the square waves having a variable width depending on the signals received, and this circuit comprises a current limiting circuit including a threshold comparator receiving at one input a signal representative of the current flowing through the switch and at another input a threshold signal, the comparator generating a signal for stopping the switch from conducting should over shooting of the threshold occur; furthermore, in order to ensure gradual start-up of the chopped power supply at the beginning of its operation and should this operation be disturbed, the control circuit comprises a means for producing a variable threshold signal for the comparator, this means being adapted for:

establishing a first fixed threshold value under normal operating conditions,

establishing a periodic threshold variation cycle outside normal operating conditions, this cycle consisting in:

causing the threshold to pass suddenly from the first value to a second value, at a time representing the beginning of the cycle, the second value corresponding to a lower current in the switch,

bringing the threshold gradually back from the second value to the first in a first part of the threshold variation cycle,

holding the threshold at the first value until the end of the current cycle,

beginning again a second threshold variation cycle at the end of the current cycle,

stopping the production of threshold variation cycles when normal operating conditions have again been established.

Normal operating conditions will in general be defined by the presence of appropriate regulation signals and by the absence of an over-current in the switch.

The periodic cycle is at very low frequency (for example 1 hz), and the duration of a first part of the cycle is preferably small with respect to the period of the cycle (for example a tenth of this period, followed by a pause during the nine remaining tenths); it is long with respect to the chopping period of the power supply.

In order to provide even more complete safety, a second threshold comparator is preferably provided receiving at one input a signal respresentative of the measurement of the current in the switch and at another input a third threshold value corresponding to a current greater than that of the first threshold value, the comparator delivering a signal for complete inhibition of the switching of the power switch should over-shooting of this third value occur, the inhibition only ceasing when the circuit, after having partially or completely ceased to be supplied with power, is again normally supplied.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the invention will be clear from reading the following detailed description made with reference to the accompanying drawings in which:

FIG. 1 shows a general chopped power supply diagram using two integrated circuits placed respectively on the primary side and on the secondary side of a transformer,

FIG. 2 shows a diagram of the integrated control circuit of the power transistor placed on the primary side,

FIGS. 3 to 6 show timing diagrams of signals at different points on the circuit, and

FIG. 7 shows a detail of a circuit for elaborating a variable threshold.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1 which shows a chopped power supply architecture given by way of example and well illustrating the utility of the invention, the electric mains line has been designated by the reference 10 (mains at 110 to 220 volts, 50 or 60 hertz). This line is connected through a filter 12 to the input of a rectifier bridge 40 whose output is connected on the one hand to a primary electric ground, represented everywhere by a downward pointing black triangle, and on the other hand to one end of the primary winding EP of the power supply transformer TA.

A filtering capacitor 16 is placed in parallel across the outputs of the rectifier bridge 14. The other end of the primary winding is connected to the collector of a switching transistor TP whose emitter is connected to the primary ground through a small current measuring resistor 18.

The transformer has several secondary windings which are preferably isolated galvanically from the mains and connected for example to a secondary electric ground isolated galvanically from the primary ground.

Here, each of the secondary windings has one end connected to the secondary ground. The other end feeds a respective low-pass filtering capacitor through a respective rectifier diode.

We will be concerned in what follows with a single secondary winding ES1, connected by a diode 20 to a capacitor 22. The DC output voltage of the chopped power supply is the voltage Vs at the terminals of the capacitor 22; but of course, other DC output voltages may be obtained at the terminals of the other filtering capacitors connected to the secondary windings. These output voltages form stabilized power supply voltages for user circuits not shown. By way of example, a secondary winding ES2 supplies a stabilized power supply voltage of a few volts for the integrated regulation circuit CI2 already mentioned. It can therefore be seen in this connection that this circuit is not supplied with power and cannot therefore supply signals as long as the chopped power supply is not operating.

The same goes a priori for the integrated circuit CI1 controlling the base of the power transistor TP, which circuit is supplied with a stabilized voltage delivered by a secondary winding ES3, a diode 24 and a capacitor 26 (it will be noted in passing that this winding, although being a secondary winding, is connected to the primary ground and not to the secondary ground, for the very simple reason that the integrated circuit CI1 is necessarily coupled galvanically to the primary).

However, since start up of the chopped power supply must be provided, the power supply terminal 28 of the integrated circuit CI1 is also connected directly to the mains through a high resistor 30 and a diode 32; this is possible since the integrated circuit CI1 is connected to the primary ground; it is not possible for the integrated circuit CI2 which must remain galvanically isolated from the mains. As soon as the chopped power supply is operating normally, the stabilized DC voltage from winding ES3 and diode 24 takes precedence over the voltage coming from the mains and from diode 32; this diode 32 is disabled and the direct supply by the mains only takes place after the initial start up phase.

The role of the integrated circuits CI1 and CI2 will now be described.

The regulation circuit CI2 receives from a divider bridge 34, placed at the terminals of capacitor 22, i.e. at the output of the stabilized power supply, information concerning the value of the voltage to be stabilized Vs.

This information is compared with a reference value and applied to a pulse width modulator which forms periodic square waves of variable width depending on the value of the output voltage Vs: the lower Vs the wider the square waves will be.

The square waves are established at the chopping frequency of the chopped power supply. This frequency is therefore established on the secondary side of the circuit; it is generated either inside the circuit CI2, or outside in a circuit not shown, in the form of a saw tooth voltage at the chosen chopping frequency. This saw tooth voltage is used in a way known per se for providing width modulation.

The variable width square waves, at the chopping frequency, are applied to a primary winding 36 of a small transformer TX whose secondary winding 38, isolated galvanically from the primary, delivers positive and negative pulses at the rising and falling fronts respectively of the variable width square waves.

It is these pulses, whose position and frequency are determined by the regulation circuits CI2, which form regulation signals applied to an input 40 of the base control circuit CI1.

The transformer TX is formed by a few turns wound on a ferrite rod, the turns of the primary and the turns of the secondary being sufficiently spaced apart from each other for complying with standards of galvanic isolation between primary circuits and secondary circuits of the chopped power supply.

The integrated base control circuit CI1 comprises different inputs among which have already been mentioned a power supply input 28 and a regulation signal input 40; a current measuring input 44 is connected to the current measuring resistor 18; an inhibition input for monitoring the magnetization condition of a transformer. Finally, inputs may be provided for connecting elements (resistors, capacities) which should form part of the integrated circuit itself but which for technological reasons (space limitation) or for practical reasons (possibilities of adjustment by the user) are mounted outside.

The integrated circuit CI1 finally comprises an output 46 which is intended to be connected by direct galvanic coupling to the base of the power transistor Tp. This output delivers square waves for enabling and disabling the transistor Tp.

FIG. 2 shows the general architecture of the integrated circuit CI1, limited to the elements which more especially concern the invention.

The output 46 of the circuit is the output of a push-pull amplification stage designated as a whole by the reference 48, this stage comprising preferably two separate amplifiers one of which receives enabling square waves and the other receives disabling signals formed by the inverted enabling signals delayed by a few microseconds. Such amplifiers are now well known.

The enabling signals are provided by a logic flip flop 50 having a set input 52 and a reset input 54. The set input causes enabling of the power transistor. The reset input causes disabling.

The set input 52 receives the pulses which pass through a logic AND gate 58, so that conduction only occurs if several conditions are satisfied simultaneously; one unsatisfied condition, will be sufficient to inhibit enabling of the conduction.

The reset input 54 receives the pulses which pass through a logic OR gate 60, so that stopping of the conduction (after enabling) will occur as soon as a stop signal is present at one of the inputs of this gate.

In the diagram of FIG. 2, the AND gate 58 has three inputs. One of these inputs receives periodic pulses from an output 62 of a high frequency oscillator 64; the other inputs serve for inhibiting the transmission of these pulses.

The oscillator defines the periodicity of the chopping of the power supply (20 kilohertz for example). Under normal operating conditions, the oscillator is synchronized by the regulation signals; under start-up conditions it is self-oscillating at a free frequency defined by the values of a resistor Ro and a capacitor Co external to the integrated circuit CI1 and connected respectively to an access terminal 66 and an access terminal 68. The free frequency fo is generally slightly lower than the normal chopping frequency.

Oscillator 64 is a relaxation oscillator which produces at an output 70 a saw tooth whose return to zero is caused by the appearance of a positive pulse at terminal 40. This is why oscillator 64 is shown with one input connected to an output 72 of a shaping and separation circuit 74 which receives the regulation signals from terminal 40 and shapes them while separating the positive pulses from the negative pulses. The shaping circuit. 74 has two outputs: 72 for the positive pulses, 76 for the negative pulses (the notation positive pulse and negative pulse will be kept for distinguishing the pulses causing conduction and the pulses stopping conduction even if the shaping circuit establishes pulses of the same sign at both its outputs 72 and 76).

The oscillator 64 has two outputs: one output 70 delivering a saw tooth and one output 62 delivering a short pulse during the zero return of the saw tooth.

A pulse width modulator 78 is connected on the one hand to the output 70 of the oscillator and on the other to a reference voltage adjustable by means of a resistor R1 external to the integrated circuit and connected to a terminal 80 giving access to the circuit. Modulator 78 supplies periodic square waves synchronized with the signals of the oscillator, these square waves defining a maximum conduction time Tmax beyond which the power transistor must be disabled in any case for safety's sake. These square waves of modulator 78 are applied to one input of the OR gate 60. The time Tmax is adjustable by means of the external resistor R1.

The elements which have just been described ensure the essential part of the operation under normal conditions of the integrated circuit CI1. The following elements are more specifically provided for controlling the abnormal operation or start-up of the power supply.

A very low frequency oscillator 82 is connected to an external capacitor C2 through an access terminal 86. This external capacitor allows the very low oscillation frequency to be adjusted. The frequency may be 1 hertz for example.

Oscillator 82 is a relaxation oscillator delivering a saw tooth. This saw tooth is applied on the one hand to a threshold comparator 88 which allows periodic square waves to be established synchronized with the very low frequency saw tooth of the oscillator. These square waves have a very short duration compared with the period of the saw tooth; this duration is set by the threshold of the comparator 88; it may for example be 10% of the period; it must be long compared with the free oscillation period of the high frequency oscillator 64 so that a burst of numerous pulses from the high frequency oscillator may be emitted and used during this 10% of this very low frequency period; this burst defines a start-up attempt during the first part of a start-up cycle; it is followed by a pause for the rest of the period, i.e. during the remaining 90%.

The oscillator only serves at start-up; it is inhibited when regulation signals appear at terminal 40 and indicate that the chopped power supply is operating. This is why an inhibition control of this oscillator has been shown connected to the output 72 of the shaping circuit 74 through a flip flop 89. This flip flop changes state under the action of the pulses appearing at output 72. It is brought back to its initial state by the output 62 of oscillator 64 when there are no longer any pulses at output 72.

The saw teeth of the very low frequency oscillator are further fed to a variable threshold elaboration circuit 90 whose purpose is to establish a threshold signal (current or voltage) having a first value Vsl under normal operating conditions, and a cyclically variable threshold between the first value and a second value under start-up conditions. The mode of variation of this threshold will be described further on, but it may already be noted that the variation is driven by the very low frequency saw tooth.

The threshold signal produced by circuit 90 is applied to one input of a comparator 92, another input of which is connected to the terminal 44 already mentioned, for receiving at this input a signal representative of the amplitude of the current flowing through the power switch. The output of comparator 92 is applied to an input of the OR gate 60. It operates then for causing the power transistor Tp to be disabled, after being enabled, disablement occurring as soon as overshooting of the threshold (fixed or variable) defined by circuit 9 has been detected.

Another threshold comparator 94 has one input connected to the current measuring terminal 44 whereas another input receives a signal representing a third threshold value Vs3. The third value Vs3 corresponds to a current in the switch higher than the first value Vsl defined by circuit 90. The output of comparator 94 is connected through a storage flip flop 96 to one input of the AND gate 58 so that, if the current in the power switch exceeds the third threshold value Vs3, transistor Tp is not disabled (such disablement is caused by comparator 92) but the transistor is inhibited from being enabled again. This inhibition lasts until the flip flop 96 is brought back to its initial state corresponding to normal operation.

In theory, such re-setting will only take place when the integrated circuit CI1 has ceased to be normally supplied with power and has again power applied thereto.

For example, re-setting of flip flop 96 takes place through a hysteresis threshold comparator 98 which compares a fraction of the supply voltage Vcc of the circuit (taken from terminal 28) with a reference value and which re-sets the flip flop the first time that Vcc passes above this reference after a drop of Vcc below another reference value lower than the first one (hysteresis). Finally, it should be mentioned that the output of the flip flop 89 (which detects the presence of regulation signals at terminal 40 so normal operation of the power supply), is connected to one input of an OR gate 100 which receives at another input the output of the comparator 88 so that the output of comparator 88 ceases to inhibit the re-enabling of transistor Tp (inhibition during 90% of the very low frequency cycles) as soon as the operation of the power supply has become normal.

OPERATION OF THE BASE CONTROL CIRCUIT

This operation will be described by illustrating it with voltage wave forms within the chopped power supply and within the integrated circuit CI1.

(a) Start-up on switching on

At the beginning the integrated circuit is not at all supplied with power.

The voltage at the power supply terminal 28 increases from 0 to a value Vaa which is not the nominal value Vcc but which is a lower value supplied by diode 32 and resistor 30 (compare FIG. 1) as long as the chopped power supply does not deliver its nominal output voltage Vcc at terminal 28. Vaa is a sufficient voltage for ensuring practically normal operation of all the elements of the circuit CI1. Vaa is also sufficient for reinitializing the flip flop 96 which, from then on, no longer inhibits the enabling of the power transistor Tp.

There are no regulation signals at the input 40. Consequently, the high frequency oscillator oscillates at its free frequency and the very low frequency oscillator also oscillates (it is not inhibited by the flip flop 89 since this latter does not receive any regulation signals from the output 72 of the shaping circuit 74).

The very low frequency oscillator 82 and the comparator 88 define periodic cycles of start-up attempts repeated at very low frequency.

Each cycle comprises a first part defined by the square waves of short duration at the output of the comparator 88, and a second part formed by the end of the very low frequency period; the first part is an effective attempt at start-up. The second part is a pause if the effective attempt has failed. The pause lasts much longer than the effective attempt so as to limit power consumption. During the first part of the cycle, passage of the enabling signals from the high frequency oscillator 64 is allowed through the AND gate 48. Then it is prohibited. Each pulse from the output 62 of the oscillator 64 triggers off the enabling of transistor Tp. There is then a burst of triggering pulses which is emitted for about 10% of the verylow frequency period.

During start up, the current intensities in the transistor tend to be high. It is essentially the comparator 92 which causes interruption of the conduction, after each enabling pulse supplied by oscillator 64, as soon as the current exceeds the threshold imposed by the variable threshold elaboration circuit 90. If the comparator 92 does not trigger off interruption of the conduction, the modulator 78 will do it in any case at the end of the duration Tmax.

The threshold elaboration circuit which supplies the comparator 90 with a first fixed threshold value Vs1 under normal operating conditions (i.e. when the very low frequency oscillator 82 is disabled by the flip flop 89), delivers a variable threshold as a function of the saw tooth of the very low frequency oscillator in the following way:

at the initial time of a start-up attempt cycle (start of the saw tooth or return to zero of the preceding saw tooth), the threshold passes suddenly from the first value Vs1 to a second value Vs2 corresponding to a smaller current than for the first value, then this threshold increases progressively (because driven by the very low frequency saw tooth) from the second value to the first one. The duration of the increase coincides preferably with the duration of a start-up attempt square wave (namely about 10% of the very low frequency period).

Then the threshold stabilizes at the first value Vs1 until the end of the period but, in any case, if the circuit has not started up at that time, the comparator 88 closes gate 58 through the OR gate 100 and inhibits any subsequent enabling of the power transistor for the rest of the very low frequency period (90%). It is in this case the second part of the start up attempt cycle which takes place: a pause during which the pulses of the oscillator 64 are not transmitted through the AND gate 58.

Thus the start up cycles act on two levels: on the one hand a burst of enabling pulses is emitted (10% of the time) then stopped (90% of the time) until the next cycle; on the other hand, during this burst, the current limitation threshold passes progressively from its second relatively low value to its normal higher value.

Consequently, if we observe the peak amplitude of the current in transistor Tp during the start-up bursts, it can be seen that it increases practically linearly from the second value to the first value. Therefore gradual start-up is obtained by a much more efficient action than that which consists simply for example in causing the time Tmax to increase from a low value to a nominal value. If start up is not successful, a new burst of enabling pulses is transmitted during the first part of the next cycle (it will be recalled that this cycle is repeated about once per second and that the burst may last 100 milliseconds).

If start-up is successful, regulation signals appear at terminal 40. These signals are shaped by circuit 74. They cause the very low frequency oscillator 82 to stop through the flip flop 89 which prevents the zero return of the saw tooth. Moreover, flip flop 89 sends through the OR gate 100 a signal for cancelling out the inhibition effect imposed by the comparator 88. Finally, as soon as start-up is successful, the regulation signals synchronize the high frequency oscillator 64.

FIG. 3 illustrates the high frequency signals during the start-up period:

line a: saw tooth at the output 70 of the oscillator 64 (free oscillation at frequency fo, period To),

line b: pulses for enabling the transistor Tp : these pulses coincide with the zero return of the saw tooth signal (output 62 of oscillator 64),

line c: output square waves from modulator 78 defining the maximum cyclic conduction time of the transistor,

line d: pulses delivered by the comparator 92 when the current in the switch exceeds the threshold (gradually increasing during start-up) defined by circuit 90.

Conduction of transistor Tp, after being triggered by a pulse from line b, is stopped either by square waves of line c if the current threshold is not exceeded, or by an output pulse from comparator 92.

FIG. 4 shows the very low frequency signals during the start up cycles. The diagrams are not to the same time scale as in FIG. 3 since it will be recalled that an example of the frequency of the high frequency oscillator 64 is 20 kilohertz whereas an example of the very low frequency of oscillator 82 is 1 hertz. The high frequency pulses have however been shown symbolically in FIG. 4, in a more limited number than in reality for facilitating the representation.

line e: saw tooth output of the very low frequency oscillator (frequency f2, period T2),

line f: output of the comparator 88 representing the first phase (start-up attempt by causing transistor Tp to be enabled) and the second phase (pause through inhibiting such enabling) during each very low frequency start-up cycle,

line g: pulses from the freely oscillating high frequency oscillator,

line h: bursts of enabling pulses at the output of the AND gate 58,

line i: diagram of the cyclic variation of the threshold elaborated by circuit 90 during the start up cycles: fixed value Vs1 in theory, sudden drop to Vs2 at the beginning of the very low frequency saw tooth, and gradual rise of Vs2 to Vs1, driven by the linear growth of the saw tooth, during the start-up burst.

(b) Operation of the power supply under normal established operating conditions

The very low frequency oscillator is not operating.

The high frequency oscillator is synchronized by the regulation signals.

The zero return of the high frequency saw tooth, coinciding with the positive pulse of the regulation signals, causes transistor Tp to be enabled (no inhibition by the AND gate under normal operating conditions). The negative pulses cause disablement, through the OR gate 64, unless such disablement has been caused:

either by an overshoot of the first current threshold value, detected by comparator 92,

or by the modulator 78 if the time interval between the positive pulse and the negative pulse which immediately follows it is greater than the maximum duration Tmax which is permitted.

FIG. 5 shows the high frequency signals under normal operating conditions.

line j: alternate positive and negative pulses received at the input 40 of the circuit (these are the regulation signals defining the times at which the power transistor Tp is enabled and disabled),

line k: shaped pulses at the output 72 of the separation and shaping circuit 74: they correspond to the positive pulses only of the regulation signals,

line l: saw tooth at the output 70 of oscillator 64; the saw tooth is synchronized with the regulation signals n so that its zero return coincides with the pulses of line k,

line m: pulses at the output 62 of oscillator 64; these pulses are emitted during zero returns of the saw tooth of line 1,

line n: output square waves of modulator 78, again defining the maximum duration of conduction of the power transistor,

line o: pulses coming from the output 70 of the separation and shaping circuit 74: these pulses correspond to the negative pulses of the regulation signals,

line p: as a reminder, pulses have been shown at the output of comparator 92 in the case where the current in the power transistor overshoots the threshold corresponding to Vs1.

Transistor Tp after being enabled by a pulse from line k is normally disabled by the pulse from line o which immediately follows it, or, more exceptionally by the pulses from line p if the threshold Vs1 has been exceeded before the appearance of the pulse from line o, or else, by the square waves of line n if the threshold has not been exceeded and if the pulse from line o appears after the beginning of a square wave of line n.

FIG. 6 shows the very low frequency signals at the time of going over from start-up conditions to normal operating conditions (same scale as in FIG. 4).

line q: regulation signals at the input 40; these signals are initially absent and appear at a certain moment,

line r: output of the flip flop 89 indicating the absence or the presence of regulation signals,

line s: very low frequency saw tooth which rises to its high level and does not drop again if the output of the flip flop 89 is at the high level (indicating the presence of regulation signals),

line t: output of the OR gate 100 showing initially a square wave of short duration, coming from comparator 88 and allowing a start-up burst (cf. FIG. 4), then blocking at the high level which prevents subsequent inhibition of the AND gate 58 by the comparator 88.

(c) Safety mode in the case of a malfunction

The safety mode consists in fact in establishing start-up cycles as for switching on.

These cycles are triggered off by starting up the very low frequency oscillator 82 when the regulation signals disappear at input 40.

The flip flop 89 goes back to an initial state when it no longer receives pulses from the output 72 of the separation and shaping circuits 74. Thus oscillator 82 will be able to oscillate again and the above described cycles are established.

(d) Serious malfunction: very high over current.

Whatever the operating conditions, normal or start-up, the over-currents in the transistor Tp are detected by the comparator 92 and cause interruption of the conduction.

But if there is for example a short circuit at the output of the power supply, an over-current may occur such that the current continues to increase before the conduction can be completely interrupted. In this case, it is provided for the threshold comparator 94 to supply an enabling inhibition order when the current in transistor Tp exceeds a third threshold value which is for example higher by 30% than the first value. This inhibition order is stored by the flip flop 96 which switches under the action of the comparator and disables the AND gate 58; the flip flop 96 can only come back to its initial state when the integrated circuit, after having partially or totally ceased to be supplied with power, is again normally supplied with power. For example, the power supply must be switched off and switched on again to again allow the passage of pulses for enabling the transistor Tp.

To finish this description, there has been shown in FIG. 7 an example of circuit 90 which elaborates a variable threshold for the comparator 92: the very low frequency saw tooth delivered by the oscillator is applied to a voltage/current converter 102 which produces a current increasing in saw tooth fashion from zero to a maximum value.

This current is applied to a series assembly of a voltage source 104 (value Vs2) and a resistor 106. A voltage clipper, shown by a Zener diode 108 (value of the conduction threshold: Vs1) is placed in parallel across the assembly 104, 106. The junction point between the output of the converter 102, the resistor 106 and the voltage clipper 108 forms the output of circuit 90 and is connected to the input of comparator 92. Thus, at zero return of the saw tooth, the output voltage of circuit 90 is Vs2. Then it increases as the current in resistor 106 increases (linearly). When the voltage at the terminals of resistor 106 reaches and exceeds the value Vs1-Vs2, the voltage clipper conducts and diverts the current surplus so that the output voltage remains limited to Vs1.

 

 

 

SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) Switch-mode power supply with burst mode standby operation:

In a switch mode power supply, a first switching transistor is coupled to a primary winding of a transformer for generating pulses of a switching current. A secondary winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a control signal in the capacitor. The control signal is applied to a mains coupled chopper second transistor for generating and regulating supply voltages in accordance with pulse width modulation of the control signal. During standby operation, the first and second transistors operate in a burst mode that is repetitive at a frequency of the AC mains supply voltage such as 50 Hz. In the burst mode operation, during intervals in which pulses of the switching current occur, the pulse width and peak amplitude of the switching current pulses progressively increase in accordance with the waveform of the mains supply voltage to provide a soft start operation in the standby mode of operation within each burst group.

Description:

The invention relates to switch-mode power supplies.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of a flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce DC output supply voltages such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver and a voltage that energizes a remote control unit.

During normal operation, the DC output supply voltages are regulated by the pulse width modulator in a negative feedback manner. During standby operation, the SMPS is required to generate the DC output supply voltage that energizes the remote control unit. However, most other stages of the television receiver are inoperative and do not draw supply currents. Consequently, the average value of the duty cycle of the chopper transistor may have to be substantially lower during standby than during normal operation.

Because of, for example, storage time limitation in the chopper transistor, it may not be possible to reduce the length of the conduction interval in a given cycle below a minimum level. Thus, in order to maintain the average value of the duty cycle low, it may be desirable to operate the chopper transistor in an intermittent or burst mode, during standby. During standby, a long dead time interval occurs between consecutively occurring burst mode operation intervals. Only during the burst mode operation interval switching operation occurs in the chopper transistor. The result is that each of the conduction intervals is of a sufficient length.

In accordance with an aspect of the invention, burst mode operation intervals are initiated and occur at a rate that is determined by a repetitive signal at the frequency of the AC mains supply voltage. For example, when the mains supply voltage is at 50 Hz, each burst mode operation interval, when switching cycles occur, may last 5 milliseconds and the dead time interval when no switching cycles occur, may last during the remainder portion or 15 milliseconds. Such arrangement that is triggered by a signal at the frequency of the mains supply voltage simplifies the design of the SMPS.

The burst mode operation intervals that occur in standby operation are synchronized to the 50 Hz signal. During each such interval, pulses of current are produced in transformers and inductances of the SMPS. The pulses of current occur in clusters that are repetitive at 50 Hz. The pulses of current occur at a frequency that is equal to the switching frequency of the chopper transistor within each burst mode operation interval. Such qurrent pulses might produce an objectionable sound during power-off or standby operation. The objectionable sound might be produced due to possible parasitic mechanical vibrations as a result of the pulse currents in, for example, the inductances and transformers of the SMPS.

In accordance with another aspect of the invention, the change in the AC mains supply voltage during each period causes the length of the conduction interval in consecutively occurring switching cycle during the burst mode operation interval to increase progressively. Such operation that occurs during each burst mode operation interval may be referred to as soft start operation. The soft start operation causes, for example, gradual charging of capacitors in the SMPS. Consequently, the parasitic mechanical vibrations are substantially reduced. Also, the frequency of the switching cycles within each burst mode operation interval is maintained above the audible range for further reducing the level of such audible noise during standby operation.

A switch mode power supply, embodying an aspect of the invention, for generating an output supply voltage during both a standby-mode of operation and during a run-mode of operation includes a source of AC mains input supply voltage. A control signal at a given frequency is generated. A switching arrangement energized by the input supply voltage and responsive to the first control signal produces a switching current during both the standby-mode of operation and the run-mode operation. The output supply voltage is generated from the switching current. An arrangement coupled to the switching arrangement and responsive to a standby-mode/run-mode control signal and to a signal at a frequency that is determined by a frequency of the AC mains input supply voltage controls the switching arrangement in a burst mode manner during the standby-mode of operation. During a burst interval, a plurality of switching cycles are performed and during an alternating dead time interval no switching cycles are performed. The two intervals alternate at a frequency that is determined by the frequency of the AC mains input supply voltage.



SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A)  TEA2028 COLOR TV SCANNING AND POWER SUPPLY PROCESSOR
 the TEA2028 combines 3
major functionsof a TV set as follows :
- Horizontal (line) and vertical (frame) time base
generation for spot deviation. The video signal is
used for the synchronization of both time bases.
- On-chip switching power supply controller synchronized
on line frequency.
This integrated circuit has been implemented in
bipolar I2L technology, and various functions are
digitally processed. In fact, resorting to logic functions
has the advantage of working with pure and
accurate signals while full benefit is drawn from
high integration of logic gates (approx. 110 gates
per mm2).
The main objective is to drive all functions using an
accurate time base generated by a master 500kHz
oscillator.
Also, horizontal and vertical time bases, are obtained
by binary division of reference frequency.
This has the advantage of eliminating the 2 adjustments
which were necessary in former devices.
One section of this integrated circuit is designed to
drive a switching power supply of recent implementation
called ”master-slave”. Switching takes place
on the primary side (i.e., directly on mains) of a
transformer. The device ensures SMPS Control,
Start-up and Protection functions.Control signals
go through a small pulse transformer thereby providing
full isolation from mains supply.
This new approach fully eliminates the bulky mains
transformersused in the past. In addition, it offers
optimized power consumption and reduction of TV
cost-price.

- MAIN FUNCTIONS
- Detection and extraction of line and frame synchronization
pulses from the composite video
signal.
- Horizontal scanning control and synchronization
by two phase-locked loop devices.
- Video identification.
- 50 or 60Hz standardrecognition for vertical scanning.
- Generation of a self-synchronized frame sawtooth
for 50/60Hz standards.
- Line time constant switching for VCR operation
through an input labeled ”VCR” (Video Cassette
Recorder).
- Control and regulation of a primary-connected
switching power supply by on-chip controller device
combining :
• an error amplifier
• a pulse width modulator synchronized on line
frequency
• a start-up and protection system
- Overall TV set protection input
- Frame blanking and super sandcastle output signals
- Frame blanking safety input for CRT protection in
case of vertical stage failure.

Internal Voltage and Current References
V.1.1 - 1.26V Voltage reference
For optimum operation of the device, an accurate
and temperature-stable voltage generator independent
from VCC variations is used (Band-gap
type generator).
The generated 1.26V is particularly used as reference
setting on input comparators.

Line Sync. Extraction
Horizontal and vertical time bases should be synchronized
with corresponding sync. pulses transmitted
inside the infra-black portion of video signal.
The duty of this stage is to extract these sync
pulses. The output signal, called composite sync,
contains the vertical sync which is transmitted by
simple inversion of line sync. pulses.
The vertical sync pulse is then extracted from this
composite signal.
The main advantage of this arrangement is its
ability to operate at video input signal levels falling
within 0.2V to 3V peak-to-peak range and at any
average value.
The operating principle is to lock the black level of
the input signal (Pin 27) onto internaly fixed voltage
(VN) and then memorize the average voltage of the
sync pulse by using an integrating capacitor connected
to Pin 26.
Finally, the composite sync signal is delivered by a
comparator the inputs of which are driven by V50%
and video signals.
The video signal is applied to Pin 27 through the
coupling capacitor ”C27”. Since the sync pulse
amplitudeisgenerallyequal to 1/3 ofVPP (i.e.66mV
to 1V) and in order to obtaina good precision of the
black level, the sync pulse should be amplified by
a coefficient of - 14 before being applied to the
comparator ”C1”.
This comparator will charge the ”C27” capacitoras
long as VS1 >VN V VS1 will stabilize at VN during the
line flyback interval ”Tr” if the average charge of
”C27” capacitor is nil for one TH period.
IC/ID is calculated such that the locking occurs at
the middle of the back porch.

- Memorizing the sync pulse 50% value
The objective is to memorize the voltage corresponding
to 50% of theline sync pulseVS1 byusing
an external capacitor connected to Pin 26 (see
Figure 9).
The overall arrangement comprises two comparators.
- Comparator C2 : delivers an output voltage ”V1”
by comparingVS1 +VD, V26 and the voltage drop
across two resistors.
- ComparatorC3 : which delivers a constant output
current thereby maintaining on capacitor ”C26”,
the voltage V50% corresponding to 50% of peak
to peak sync pulse.

Sync pulse detection
This function is fulfilled by comparing the inverted
video signal (VS1 + VD) whose black level is constant
at 2V, with the sync 50% voltage level on
Pin 26 (see Figure 10).
Comparator C4 will deliver the line sync pulse (LS)
which will be used for 3 functions :
- Horizontal scanning frequency locking : output to
j1 phase comparator.
- Frame sync extraction for vertical scanning synchronization.
- Detecting the presence of a video signal at circuit
input.
The LS signal in two latter functions is filtered for
noise by using combination of current generator I
and a zener diode equivalent to a capacitor.
Using this extraction technique at a very noisy
video signal yields remarkable display stability.

First Phase Locked-loop Stage ”j1”
This stage is commonly called the first Phase
Locked-Loop ”j1”.
Its duty is to lock the frequency and the phase of
the horizontal time base with respect to the line
sync signal.
In the absence of transmission (i.e. lack of line
sync), the horizontal scanning frequency is obtained
by dividing the output frequency of a VCO
device. This VCO oscillates at approximately
500kHz and uses a low frequency drift ceramic
resonator.This method eliminates the need of horizontal
frequency adjustment.

VCO centered on 500kHz
This is a voltage-controlled oscillator which generates
an output frequency proportional to the voltage
applied to its input.
This voltage is delivered by low-pass filter.

VCO (Voltage Controlled Oscillator)
Its function is to generatea frequency proportional
to a control voltage issued externally, by the lowpass
filter in our case.
The period of the output signal is used as timing
reference for various functions such as, horizontal
and vertical time bases. The frequency range must
be short and accurate :
- It must be short since the power dissipated within
the horizontal scanning block is inversely proportional
to the line frequency.
- The accuracy is required if the adjustment is to
be omitted.
The basic arrangement is to employ a ceramic
resonator (or ceramic filter) which has quite stable
characteristics as a function of frequency.
A filter whose resonating frequency is a multiple of
line frequency (15625Hz) is to be selected. An
example is 32 V 15625 = 500kHz.

Video identification stage
This stage will detect the coincidence between the
line sync pulse (if present) and a 2ms pulse issued
from the logic block. This 2ms pulse at line frequency
is positionned at the center of line sync
pulse when the first loop ”j1” is locked.
This sampled detection is stored by an external
capacitor connected to Pin 25. The video recognition
status is also available on Pin 24 so as to
enable Sound Muting during station search process
and the inhibition of Automatic FrequencyTuning.

- Line deflection stage
- Generates the saw-tooth current for line yoke
- Generates the high voltage required by picture
tube and other supply voltages
The line flyback information is provided by the
EHT transformer.

Line deflection stage
This chapter will cover a general description of the
”horizontal deflection stage” employed almost
commonly in all recent TV sets.
Deflection of electron beam is proportional to the
intensity of magnetic field induced by the line yoke.
This yoke is equivalent to an inductor. The deflection
is therefore proportional to the current through
inductor.
In order to obtain a linear deflection from left to right
as a function of time, a saw-tooth current must be
generated within the yoke.The approachis toapply
a switched DC voltage to the line yoke.

Vertical deflection driver stage
This stage must constantly drive the vertical spot
deflection.Such deflectionwill horizontallyscan the
screen from top to bottom thus generating the
displayed image. Similar to horizontal deflection,
the vertical deflection is obtained by magnetic field
variations of a coil mounted on the picture tube.
A saw-tooth current at frame frequency will go
through this coil commonly called ”frame yoke”.
Frame period is the time required for the entire
screen to be scanned vertically.
C.C.I.R.and N.T.S.C.TVstandardsrequirerespectively
50Hz and 60Hz Frame Scanning Frequencies.
Also, a full screen display is obtained by two
successivevertical scanningssuch that the second
scanning is delayed by a half line period with
respect to the first.
This method increases the number of images per
second (50 half images/s or 50 frames/s in 50Hz
standard). This scanning mode called ”Interlaced
Scanning” eliminates the fliker which would have
been otherwise produced by scanning 25 entire
images per second.
The circuit will generate a saw-tooth voltage which
is linear as a function of time and called ”frame
saw-tooth”. A power amplifier will deliver to the
”frame yoke” a current proportional to this sawtooth
voltage. It is thus clear that this saw-tooth
voltage reflects the function of the vertical spot
deflection; which must itself be synchronized with
the video signal. Synchronization signals are obtained
from an extraction stage which will extract
the useful signal during line pulse inversion of the
composite sync signal.
Synchronization occurs at the end of scanning, in
other words, when the saw-tooth voltage at Pin 5
is reset. This function is accomplished by the
”frame logic circuitry” of full digital implementation.


This processing method offers various advantages
:
- Accurate free-running scanning frequency
eliminates the frequencyadjustment required by
previous devices.
- Digital synchronization locked onto half line
frequency thereby yielding perfect interlaced display
andexcellent stabilitywith noisy videosignal.
- Automatic 50/60Hz standard recognition and
switching the corresponding display amplitude.
- Optimized synchronization in VCR mode.
- Generationof variousaccurate time intervals,
such as narrow ”sync windows” thus reducing
considerably the vertical image instability in case
of for instance,mainsinterference,superimposed
on frame sync pulse.
- Generation of vertical blanking signal for spot
flyback and to protect the picture tube in case
of scanning failure.

Vertical synchronization window -
Free-running period
In the absence of sync pulse various free-running
periods are specified. Since vertical scanningmust
be always active, these free-running periods must
be higher than those of 50 and 60Hz standards so
as to ensure synchronization.
An other window, allowing synchronization only at
the end of scanning, is also necessary. Upon synchronization,
this window will allow vertical flyback
only at the bottom of screen. This window should
be narrow for good noise immunity but also wide
enough to yield, upon synchronization, a capture
time unperceptible on screen.
In our case, as long as no standard identification
takes place the window will remain wide, and once
one of the standards has been identified, the window
will be considerably reduced.
InVCRmode, thiswindow will bealways wide since
frame frequenciesdelivered in high-speed search,
slow review and picture pause modes are very
much variable and must be taken into consideration.
In the absenceof transmission (Mute = 0), synchronization
is disabled (so as to avoid incorrect synchronization
due to noise) and the free-running
frequency is around 50Hz. This will eliminate the
occurrence of picture overlay at the end of trace at
a lower free-running frequency.

- Frame blanking safety (TEA2028 only,
for TEA2029 refer to section VII.5)
Its duty is to protect the phosphorcoating of picture
tube in case of any problem with vertical deflection
function such as scanning failure.
Asignal to monitor correct scanning is provided by
the frame yoke and applied to Pin 2.
In case of any failure, all frame blanking outputsare
disabled and go high thereby blanking the entire
screen.
During trace phase, the voltage across frame yoke
has a parabolicalshape due to the couplingcapacitor
in series with yoke. During frame flyback, the
current through frame yoke must be rapidly inverted.
Conventionally, a two-fold higher supply
voltage is applied across the yoke. This will produce
an overvoltage called ”flyback”.
The safety monitoring status is detected on the
falling-edge of flyback, i.e. at the beginning of
scanning. A differentiator network is used to transmit
only fast voltage variations.
Therequiredpulse is then compared to 1.26Vlevel.
Frame blanking goes high in the absence of negative
pulse (zero deflection current) or if the pulse
does not fall within the first 21 lines (exagerated
over-scanning).


SWITCHING POWER SUPPLY DRIVER STAGE
Switching takes place on the primary side (mains
side) of a transformer by using TEA2164 SMPS
Controller manufactured by SGS-THOMSON.
Required voltage values are obtained by rectifying
different voltage outputs delivered through secondary
windings. The horizontal deflection stage is
powered by one of these outputs delivering around
hundred volts.
This voltage source must be regulated since any
voltage fluctuation will yield variations of the horizontal
display amplitude.
The TE2028 monitors this voltage and transmits
the regulation signal to the primary controller circuitry
via a small pulse transformer. The characteristics
of this regulation signal are directly related
to the conduction period of switching transistor.

General operating principles
A fraction of the 135V output voltage to be regulated
is compared to the 1.26V reference voltage.
Resulting error signal is amplified and then applied
to phase modulator ”M1”, which will deliver a
square waveform at line frequency whose duty
cycle depends on the value of input voltage ”V9”.
A second phase modulator ”M2” will determine the
conduction period as a function of voltage on
Pin 15. This function is mandatory for system startup.
A 28ms window is used to limit the conduction
period of the primary-connected transistor.
Supply output (Pin 7) and line output (Pin 10) will
be disabled if any information indicating abnormal
operation is applied to safety input (Pin 28). Consequently,
all power stages are disabled and the
TV set is thus protected.

SMPS WAVEFORMS
For discontinous mode ”flyback” configuration
The primary-connected transistor is turned-off during
the line flyback.
All interference signals due to switching and susceptible
to affect the video signal will not therefore
be visible on screen.

Power supply soft-start
When theTVset is initially turned on,control pulses
are not yet available and consequently the controller
block on primary side will impose a low-power
transfer to the secondary winding. This power is
produced by an intermittent switching mode called
”Burst Mode”.
As soon as the VCC supply to TEA2028Bexceeds
6V level, line andSMPSoutputsareenabled.Since
the filtering capactitors on secondary side cannot
charge up instantaneously,the voltage to be regulated
would not yet be at its nominal value.Without
conduction period limitation upon start-up, the device
will set a maximum cycle of 28ms which will
result in a high current flow through the primary
winding and thus through the switching transistor
which will in turn activate the protection function
implemented on primary side.
Consequently, the primary controller block will be
inhibited and the set will not turn-on.

A start-up system has been implemented within
TEA2028B to overcome this problem.
This soft start system, will upon initial start-up, use
the image of the falling voltage on Pin 15 to increase
progressively the conduction cycle. The
phase modulator ”M2” compares this voltage with
line saw-tooth voltage and delivers the corresponding
limitation cycle.
During supply voltage rising cycle [VCC (Pin 8)
< 6V], the capacitor Pin 15 will charge up rapidly
while the voltage across it follows VCC.
At VCC . 6V, the capacitor is discharged via an
internal current generatorand the voltage across it
decays linearly.
At V15 3 3.5V (line saw-tooth peak-to-peak voltage),
phase comparator ”M2” delivers a low conduction
period which will gradually increase.
The conduction period (Pin 7) will rise until the
secondary voltage reaches the value set by potentiometer
”P”. When this occurs, the loop is activated.
The Pin 15 discharge current value is 100mA for a
duration of 2ms line frequency.

- Protection features
As soon asa safety signal (V 3 1.26V) is applied to
Pin 28, line and supply outputs (Pins 10 and 7) are
both disabled. Capacitor ”C15” begins charging up
until the voltage across it reaches 4V (K V VCC).
Outputs are again enabled and conduction period
gradually increases as it occurs upon initial startup.
The device will be definitively inhibited if the cycle
of events is repeated 3 times.
For the device to restart, the internal 3-bit register
should be reset which requiresthe VCC to fall below
4V (see Figure 68).
Pin 15 charging current : IC(AV) = - ID(AV) = - 3.1mA

TV Power supply in standby mode
V.7.6.1 - Regulationby primary controller circuit
This mode of regulation called ”Burst Mode” is
performedonly by the primary controller circuit and
is activated in the case of missing control pulses or
in the absence of power supply to TEA2028B.
In this mode, power available through secondary
winding is limited. Refer to TEA2164 Application
Note for further details.
Higher powers can be obtained by using the regulation
feature offered by TEA2028B. In this case,
the horizontal output (Pin 10) must be disabled.
V.7.6.2 - Regulation by TEA2028
In this case, all that is required is to disable the line
scanning function thus reducing the overall power
by 90%.
The device power supply regulation loop remains
active, for minimum conduction period to be 1.5ms
the power delivered through secondary must be
higher than 3W.
Line Output Inhibition
Two alternativesare possible :
- Grounding flip-flop Pin 1
- Apply a voltage higher than 3V to Pin 12.

Super sandcastle signal generator
This signal used in video stage, is available on
Pin 11.
It has 3 levels at specified time intervals :
- 2.5V level
Used for vertical blanking at each frame flyback.
Its duration is 21 lines and is generated by the
frame logic.
This level will be maintained if vertical scanning
failure is detected on Pin 2.
- 4.5V level
Used for horizontal blanking, its duration is determined
by comparing the line flyback signal on
Pin 12 to an internal voltage of 0.25V.
- 10V level
This signal is used by color decoding stage. Its
duration of 4ms is determined by line logic circuitry.
With respect to the video signal on Pin 27,
this level is positioned such that it is used to
sample the burst frequency transmitted just after
the sync pulse.

-------------------------------

TDA4555 Multistandard decoder.


GENERAL DESCRIPTION
The TDA4555 and TDA4556 are monolithic integrated

multistandard colour decoders for the PAL, SECAM,
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
and (R-Y).
Features
Chrominance part
· Gain controlled chrominance amplifier for PAL, SECAM
and NTSC
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
Demodulator part
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· De-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
stages (blanking)
Identification part
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
and crystals
· Two identification circuits for PAL/SECAM (H/2) and
NTSC
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch.


PHILIPS TDA4565 Colour transient improvement
circuit

GENERAL DESCRIPTION
The TDA4565 is a monolithic integrated circuit for colour transient improvement (CTI) and luminance delay line in gyrator
technique in colour television receivers.
Features
· Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and
switching stages resulting in high transients of colour difference output signals
· A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line
· Switchable delay time from 730 ns to 1000 ns in steps of 90 ns and additional fine adjustment of 50 ns
· Two Y output signals; one of 180 ns less delay.



PHILIPS TDA2556 QUASI-SPLIT-SOUND CIRCUIT WITH DUAL SOUND DEMODULATORS

GENERAL DESCRIPTION
The TDA2556 is a monolithic integrated circuit for quasi-split-sound processing, including two FM
demodulators, for two carrier stereo TV receivers and VTR.
Features
First IF (vision carrier plus sound carrier).
0 3 stage gain controlled IF amplifier
0 AGC circuit
0 Reference amplifier and limiter amplifier for vision carrier (V.C.) processing
0 Linear multiplier for quadrature demodulation
Second IF (two separate channels for both FM sound signals).
0 4-stage-limiting amplifier
0 Ouadrature demodulator
0 AF amplifier with de-emphasis
O Output buffer
0 Muting for one or both AF outputs




TEA2164 /2165 SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT



.POSITIVE AND NEGATIVE OUTPUT CURRENT
UP TO 1.2AAND – 1.7A .A TWO LEVEL COLLECTOR CURRENT LIMITATION
.COMPLETE TURN OFF AFTER LONG DURATION
OVERLOADS .UNDER AND OVER VOLTAGELOCK-OUT .SOFT START BY PROGRESSIVE CURRENT
LIMITATION .DOUBLE PULSE SUPPRESSION .BURST MODE OPERATION UNDER STANDBY
CONDITIONS
DESCRIPTION
In amaster slave architecture, the TEA2164control
IC achieves the slave function. Primarily designed
for TV receivers and monitors applications, this
circuit provides an easy synchronizationand smart
solution for low power stand by operation.
Located at the primary side the TEA2164 Control
IC ensures :
- the power supply start-up
- the power supply control under stand-by conditions
- the process of the regulation signals sent by the
master circuit located at the secondary side
- directbasedrive of the bipolarswitching transistor
- the protection of the transistor and the power
supply under abnormal conditions.

II. GENERAL DESCRIPTION
In a master slave architecture, the TEA2164 Control
IC, located at the primary side of an off line
power supply achievesthe slave function ;whereas
the master circuit is located at the secondary side.
The link between both circuits is realized by a small
pulse transformer

In the operation of the master-slave architecture,
four majors cases must be considered :
- normal operating
- stand-bymode
- power supply start-up
- abnormal conditions : off load, short circuit, ...
II.1. Normal Operating (master slave mode)
In this configuration, the master circuit generatesa
pulse widthmodulatedsignal issued from themonitoring
of the output voltage which needs the best
accuracy (in TV applications : the horizontal deflection
stagesupplyvoltage).Themaster circuit power
supply can be supplied by another output.
The PWM signal are sent towards the primary side
through small differentiating transformer. For the
TEA2164 positive pulses are transistor switchingon
commands ; and negative pulses are transistor
switching-offcommands (Figure 4). In this configuration,
only by synchronizing the master oscillator,
the switching transistor may be synchronized with
an external signal.
II.2. Stand-by Mode
In this configuration the master circuit no longer
sends PWM signals, the structure is not synchronized
; and the TEA2164 operates in burst mode.
The average power consumption at the secondary
side may be very low 1W 3 P 3 6W (as it is
consumed in TV set during stand by).
By action on the maximum duty cycle control, a
primary loop maintains a semi-regulation of the
output voltages.Voltage on feed-back is applied on
Pin 9.
Burst period is externally programmedby capacitor
C1.
II.3. Power Supply Start-up
After the mains have been switched-on, the VCC
storage capacitor of the TEA2164 is charged
through a high value resistor connected to the
rectified high voltage.When Vcc reaches VCC start
threshold (9V typ), the TEA2164 starts operatingin
burst mode. Since available output power is low in
burst mode the output power consumption must
remain low before complete setting-up of output
voltage. In TV application it can be achieved by
maintaining the TV in stand-by mode during startup.

Overvoltage Protection
When VCC exceeds VCC max, an internal flip-flop
stops output conduction signals. The circuit will
start again after the capacitor C1 discharge ; it
means : after loss of synchronization or after Vcc
stop crossing (Figure 7).
In flyback converters, this function protects the
power supply against output voltage runaway.



SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) TDA8442 I2C-bus interface for colour decoders

GENERAL DESCRIPTION
The TDA8442 provides control of four analogue functions
and has one high-current and two switching outputs.
Control of the IC is performed via the two-line, bidirectional
I2C-bus.
Features
· Four analogue control outputs
· One high-current output port (npn open emitter)
· Two switching output ports (npn collector with internal
pull-up resistor)
· I2C-bus slave receiver
· Power-down reset.

SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) SONY DST EHT FBT TRANSFORMER Bobbin structure for high voltage transformers EHT Output.A coil bobbin for a fly-back transformer or the like having a bobbin proper. A plurality of partition members or flanges are formed on the bobbin proper with a slot between adjacent ones. At least first and second coil units are formed in the bobbin proper, each having several slots, formed between the flanges, and first and second high voltage coils are wound on the first and second coil units in opposite directions, respectively. A rectifying means is connected in series to the first and second coil units, and a cut-off portion or recess is provided on each of the partition members. In this case, a wire lead of the coil units passes from one slot to an adjacent slot through the cut-off portion which is formed as a delta groove, and one side of the delta groove is corresponded to the tangent direction to the winding direction.


1. A fly-back transformer comprising a coil bobbin comprising a plurality of parallel spaced discs with a first adjacent plurality of said disc formed with delta shaped slots having first edges which extend tangentially to a first winding direction and a first winding wound on said first adjacent plurality of said discs in said first winding direction, a second adjacent plurality of said discs formed with delta shaped slots having first edges which extend tangentially to a second winding direction opposite said first winding direction and a second winding wound on said second adjacent plurality of said discs in said second winding direction, a third adjacent plurality of said discs formed with delta shaped slots having first edges which extend tangentially to said first winding direction and a third winding wound on said third adjacent plurality of said discs in said first winding direction and said second plurality of adjacent discs mounted between said first and third plurality of adjacent discs. 2. A fly-back transformer according to claim 1 wherein adjacent ones of said first adjacent plurality of discs are mounted such that their delta shaped slots are orientated 180 degrees relative to each other. 3. A fly-back transformer according to claim 2 including a first winding turning partition mounted between said first and second adjacent plurality of discs and formed with grooves and notches for changing winding direction between said first and second windings and a second winding turning partition mounted between said second and third adjacent plurality of discs and formed with grooves and notches for changing the winding direction between said second and third windings. 4. A fly-back transformer according to claim 3 wherein said first and second winding turning partitions are formed with winding guiding slots for guiding the winding between the first, second and third adjacent plurality of discs. 5. A fly-back transformer according to claim 2 including a first rectifying means connected between one end of said first winding and one end of said second winding, and a second rectifying means connected between the second end of said second winding and one end of said third winding. 6. A fly-back transformer according to claim 5 wherein the second end of said first winding is grounded and a third rectifying means connected between the second end of said third winding and an output terminal.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a bobbin structure for high voltage transformers, and is directed more particularly to a bobbin structure for high voltage transformer suitable for automatically winding coils thereon.
2. Description of the Prior Art
In the art, when a wire lead is reversely wound on a bobbin separately at every winding block, a boss is provided at every winding block and the wire lead is wound on one block, then one end of the wire lead is tied to the boss where it will be cut off. The end of the wire lead is tied to another boss, and then the wire lead is wound in the opposite direction. Therefore, the prior art winding method requires complicated procedures and the winding of the wire lead cannot be rapidly done and also the winding can not be performed automatically. Further, the goods made by the prior art method are rather unsatisfactory and have a low yield.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly an object of the invention is to provide a coil bobbin for a fly-back transformer or the like by which a wire lead can be automatically wound on winding blocks of the coil bobbin even though the winding direction is different among the different winding blocks.
Another object of the invention is to provide a coil bobbin for a fly-back transformer or the like in which a bridge member and an inverse engaging device for transferring a wire lead from one wiring block to an adjacent wiring block of the coil bobbin and wiring the wire lead in opposite wiring directions between adjacent wiring blocks, and a guide member for positively guiding the wire lead are provided.

According to an aspect of the present invention, a coil bobbin for a fly-back transformer or the like is provided which comprises a plurality of partition members forming a plurality of slots, a first coil unit having several slots on which a first high voltage coil is wound in one winding direction, a second coil unit having several slots on which a second high voltage coil is wound in the other direction, a rectifying means connected in series to the first and second coil units, and a cut-off portion provided on each of the partition members, a wire lead passing from one slot to an adjacent slot through the cut-off portions, each of the cut-off portions being formed as a delta groove, and one side of the delta groove corresponding to a tangent to the winding direction.
The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like reference numerals and letters designate the same elements and parts, respectively.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram showing the construction of a fly-back transformer;
FIG. 2 is a connection diagram showing an example of the electrical connection of the fly-back transformer shown in FIG. 1;
FIG. 3 is a schematic diagram showing an example of a device for automatically winding a wire lead of the fly-back transformer on its bobbin;
FIG. 4 is a perspective view showing an example of the coil bobbin according to the present invention;
FIG. 5 is a plan view of FIG. 4;
FIGS. 6 and 7 are views used for explaining recesses or cut-off portions shown in FIGS. 4 and 5; and FIGS. 8A and 8B cross-sectional views showing an example of the inverse engaging means according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
When the high voltage winding of a fly-back transformer used in a high voltage generating circuit of a television receiver is divided into plural ones and then wound on a bobbin, the divided windings (divided coils) are connected in series through a plurality of rectifying diodes.
When the winding is divided into, for example, three portions, such as divided coils La, Lb and Lc, they are wound on a bobbin proper 1 from, for example, left to right sequentially in this order as shown in FIG. 1. In this case, if the divided coils La and Lc are selected to have the same sense of turn and the middle coil Lb is selected to have the opposite sense of turn from the coils La and Lc, the distance between the terminal end of coil La and the start of coil Lb and the distance between the terminal end of coil Lb and the start of coil Lc can be got relatively long. Therefore, diodes Da and Db can be mounted by utilizing the space above the block on which the middle coil Lb is wound as shown in FIG. 1, so that it becomes useless to provide spaces for diodes between the divided coils La and Lb and between the divided coils Lb and Lc and hence the bobbin proper 1 can be made compact.
FIG. 2 is a connection diagram showing the connection of the above fly-back transformer. In FIG. 2, reference numeral 2 designates a primary winding (Primary coil) of the fly-back transformer, reference letter L designates its high voltage winding (secondary coil), including divided coils La, Lb and Lc, 3 an output terminal, and 4 a lead wire connected to the anode terminal of a cathode ray tube (not shown), respectively.
An example of the bobbin structure according to the invention, which is suitable to automatically wind coils, which are different in sense of turn in each winding block as shown in FIG. 1, on the bobbin, will be hereinafter described with reference to the drawings.
FIG. 3 is a diagram showing an automatic winding apparatus of a wire lead on a coil bobbin. If it is assumed that the wire lead is wound in the order of winding blocks A, B and C in FIG. 1 and the wire lead is wound on the block A with the bobbin proper 1 being rotated in the counter-clockwise direction as shown in FIG. 3, the relation between the bobbin proper 1 and the wire lead becomes as shown in FIG. 3. In this figure, reference numeral 6 designates a bobbin for feeding the wire lead.
Turning to FIG. 4, an example 10 of the bobbin structure or coil bobbin according to the present invention will be described now. In this example, the winding blocks A, B and C for the divided coils La, Lb and Lc are respectively divided into plural slots or sections by plural partition members or flanges 11, and a cut-off portion or recess 12 is formed on each of the flanges 11 through which the wire lead in one section is transferred to the following winding section.
As shown in FIG. 6, each recess 12 is so formed that its one side extends in the direction substantially coincident with the tangent to the circle of the bobbin proper 1 and its direction is selected in response to the sense of turn of the winding or wire lead. In this case, the direction of recess 12 means the direction of the opening of recess 12, and the direction of recess 12 is selected opposite to the sense of turn of the winding in the present invention.
Now, recesses 12A, which are formed in the winding block A, will be now described by way of example. The positions of recesses 12A formed on an even flange 11Ae and an odd flange 11A ₀ are different, for example, about 180° as shown in FIGS. 6A and 6B. Since the bobbin proper 1 is rotated in the counter-clockwise direction in the winding block A and hence the sense of turn of the wire lead is in the clockwise direction, the recess 12A is formed on the even flange 11Ae at the position shown in FIG. 6A. That is, the direction of recess 12A is inclined with respect to the rotating direction of bobbin proper 1 as shown in FIG. 6A. In this case, one side 13a of recess 12A is coincident with the tangent to the circle of bobbin proper 1, while the other side 13b of recess 12A is selected to have an oblique angle with respect to the side 13a so that the recess 12A has a predetermined opening angle.
The opening angle of recess 12A is important but the angle between the side 13a of recess 12A and the tangent to the circle of bobbin proper 1 is also important in the invention. When the wire lead is bridged or transferred from one section to the following section through the recess 12A, the wire lead in one section advances to the following section in contact with the side 13a of recess 12A since the bobbin proper 1 is rotated. In the invention, if the side 13a of recess 12A is selected to be extended in the direction coincident with the tangent to the circle of bobbin proper 1, the wire lead can smoothly advance from one section to the next section without being bent.
In the invention, since the middle divided coil Lb is wound opposite to the divided coil La, a recess 12B provided on each of flanges 11B of the winding block B is formed to have an opening opposite to that of recess 12A formed in the winding block A as shown in FIGS. 6C and 6D.
As shown in FIG. 5, terminal attaching recesses 14 are provided between the winding blocks A and B to which diodes are attached respectively. In the illustrated example of FIG. 5, a flange 15AB is formed between the flanges 11A ₀ and 11B ₀ of winding blocks A and B, and the recesses 14 are formed between the flanges 11A ₀ and 15AB and between 15AB and 11B ₀ at predetermined positions. Then, terminal plates 16, shown in FIG. 4, are inserted into the recesses 14 and then fixed there to, respectively. The terminal plates 16 are not shown in FIG. 5. Between the winding blocks B and C and between the blocks A and B, similar terminal attaching recesses 14 are formed, and terminal plates 16 are also inserted thereinto and then fixed thereto.
As described above, since the divided coil Lb is wound opposite to the divided coils La and Lc, it is necessary that the winding direction of the wire lead be changed when the wire lead goes from the block A to block B and also from the block B to block C, respectively.
Turning to FIG. 7, an example of the winding or wire lead guide means according to the present invention will be now described. In FIG. 7, there are mainly shown a bridge member for the wire lead and an inverse member or means for the wire lead which are provided between the winding blocks A and B. At first, a bridge means 20 and its guide means 21, which form the bridge member, will be described. The bridge means 20 is provided by forming a cut-out portion or recess in the middle flange 15AB located between the winding blocks A and B. In close relation to the bridge means or recess 20, the guide means 21 is provided on a bridge section X _A at the side of block A. This guide means 21 is formed as a guide piece which connects an edge portion 20a of recess 20 at the winding direction side to the flange 11A ₀ of block A in the oblique direction along the winding direction through the section X _A .
Next, an inverse engaging means 22 will be now described with reference to FIGS. 7 and 8. If the flange 11B ₀ of FIG. 7 is viewed from the right side, the inverse engaging means 22 can be shown in FIG. 8A. In this case, the tip end of one side 13a of recess 12B ₁ is formed as a projection which is extended outwards somewhat beyond the outer diameter of flange 11B ₀ . The inverse engaging means 22 may take any configuration but it is necessary that when the rotating direction of the bobbin proper 1 is changed to the clockwise direction, the wire lead can be engaged with the recess 12B ₁ or projection of one side 13a and then suitably transferred to the next station.
Another guide means 23 is provided on a bridge section X _B at the side of winding block B in close relation to the inverse engaging means 22. The guide means 23 is formed as a guide surface which is a projected surface from the bottom surface of section X _B and extended obliquely in the winding direction. This guide means or guide surface 23 is inclinded low into the means 22 and has an edge 23a which is continuously formed between the middle flange 15AB and the flange 11B ₀ .
In this case, it is possible that the guide means 21 and guide surface 23 are formed to be the same in construction. That is, both the guide means 21 and 23 can be made of either the guide piece, which crosses the winding section or guide surface projected upwards from the bottom surface of the winding section. It is sufficient if the guide means 21 and 23 are formed to smoothly transfer the wire lead from one section to the next section under the bobbin proper 1 being rotated.
Although not shown, in connection with the middle flange 15BC between the winding blocks B and C, there are provided similar bridge means 20, guide means 21, inverse engaging means 22 and another guide means 23, respectively. In this case, since the winding direction of the wire lead is reversed, the forming directions of the means are reverse but their construction is substantially the same as that of the former means. Therefore, their detailed description will be omitted.
According to the bobbin structure of the invention with the construction set forth above, the wire lead, which is transferred from the block A to the section X _A by the rotation of bobbin proper 1, is wound on the section X _B from the section X _A after being guided by the guide piece 21 to the recess 20 provided on the middle flange 15AB, and then transferred to the recess 22 provided on the flange 11B ₀ guide surface 23, bridged once to the first section of winding block B through the recess 22 (refer to dotted lines b in FIG. 7). Then, if the rotating direction of the bobbin proper 1 is reversed, the wire lead is engaged with the bottom of recess 22 (refer to solid lines b in FIG. 7). Thus, if the above reverse rotation of bobbin proper 1 is maintained, the wire lead is wound on the block B in the direction reverse to that of block A. When the wire lead is transferred from the block B to block C, the same effect as that above is achieved. Therefore, according to the present invention, the wire lead can be automatically and continuously wound on the bobbin proper 1.
After the single wire lead is continuously wound on blocks A, B and C of bobbin proper 1 as set forth above, the wire lead is cut at the substantially center of each of its bridging portions. Then, the cut ends of the wire lead are connected through diodes Da, Db and Dc at the terminal plates 16, respectively by solder.
In the present invention, the projection piece, which has the diameter greater than that of the flange 11B, is provided in the bridge recess 12 to form the inverse engaging means 22 as described above, so that when the winding direction is changed, the wire lead engages with the inverse engaging means 22 without errors when reversing the winding direction of the wire lead.
If the diameter of the projection piece of means 22 is selected, for example, to be the same as that of the flange 11B, it will not be certain that the wire lead engages with the means 22 because it depends upon the extra length of the wire lead and hence errors in winding cannot be positively avoided.
Further, in this invention, the bridge means is provided on the flange positioned at the bridging portion of the bobbin which has a number of dividing blocks separated by flanges, and the inverse engaging means is provided and also the guide means is provided at the former winding section to cooperate with the inverse engaging means. Therefore, the wire lead can be positively fed to the bridge means, and the transfer of the wire lead to the following winding section can be carried out smoothly.
Further, in this invention since one side of the recess 12 is selected coincident with the tangent of the outer circle of the bobbin proper 1 and also with the winding direction, the wire lead can be smoothly bridged to the following section. Due to the fact that the direction of recess 12 is changed in response to the winding direction, even if there is a block on which the wire lead is wound in the opposite direction to that of the other block, the wire lead can be continuously and automatically wound through the respective blocks.
The above description is given for the case where the present invention is applied to the coil bobbin for the high voltage winding of a fly-back transformer, but it will be clear that the present invention can be applied to other coil bobbins which require divided windings thereon with the same effects.
It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the present invention, so that the spirits or scope of the invention should be determined by the appended claims only.



SONY KV-X25TA  CHASSIS   AE1 (SCC-B16-EA) Television receiver which can indicate the numeral of a channel SONY On Screen Display TECHNOLOGY.

A television receiver having a CPU (central processing unit), a ROM (read only memory) in which a program and a font data are written, and a RAM (random access memory) for work area and a shift register. The font data to be indicated as a channel numeral is loaded to the shift register by an interrupt procedure and the output from the shift register is supplied to the video signal system whereby to indicate the channel numeral after the channel is changed.



1. A television receiver for receiving a video signal that includes a synchronizing signal, said receiver comprising:
a central processing unit having an interrupt function;
bus means connected to said central processing unit;
read only memory means connected to said central processing unit through said bus means and containing a control program to be executed by said central processing unit;
random access memory means connected to said central processing unit through said bus means and used as a work area of said central processing unit;
channel selecting means connected to said central processing unit through said bus means for selecting one of a plurality of channels;
control signal receiving circuit means connected to said central processing unit through said bus means for receiving a control signal and controlling said channel selecting means;
shift register means connected to said central processing unit through said bus means;
clock pulse generating means for supplying a clock pulse to said shift register means synchronized with the synchronizing signal of said video signal and generating a serial signal representing a character pattern from said shift register means; and
mixing means for mixing said video signal and said serial signal;
said control program in said read only memory means containing font data to be displayed, a main program for decoding said control signal and controlling said channel selecting means, and an interrupt program for loading the font data from said read only memory means into said shift register means.
2. A television receiver according to claim 1; further comprising an integrated circuit chip, said central processing unit, said bus means, said read only memory means, said random access memory means and said shift register means being formed on said chip. 3. A television receiver according to claim 1; wherein said synchronizing signal includes a horizontal synchronizing pulse, said central processing unit is interrupted by said horizontal synchronizing pulse, and said interrupt program is started by said horizontal synchronizing pulse. 4. A television receiver according to claim 3; wherein a horizontal trace period follows said synchronizing signal and said font data from said read only memory means is loaded into said shift register means during a first portion of the horizontal trace period and said serial signal is generated during a second portion of the horizontal trace period.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a television receiver and more particularly is directed to a television receiver which can indicate the numeral of a channel after the channel is changed.
2. Description of the Prior Art
There is proposed a television receiver in which when a channel is changed, the numeral indicative of the channel after the channel is changed is indicated on the screen of a cathode ray tube during a predetermined period. Such previously proposed television receiver is disclosed in U.S. Pat. No. 3,748,645, U.S. Pat. No. 3,812,285 and so on. A conventional channel indicator used in such television receiver requires a special LSI (large scale integration) chip to indicate the numeral of the channel. However, such LSI chip requires a substantial investment in time and money from its designing to the completion, and when the designing thereof is changed midway, it is quite difficult to cope with such change.
Moreover, it is difficult to give an individuality to the character pattern of the numeral indicating the channel. Furthermore, the number of ICs (integrated circuits) is increased and hence the manufacturing cost is inevitably raised.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved television receiver which is free from the problem inherent to the prior art.
It is another object of the present invention to provide a television receiver which can indicate the numeral of a channel after the channel is changed by employing a microcomputer.
It is still another object of the present invention to provide a television receiver in which an individuality can easily be given to the character pattern of the numeral of a channel to be indicated.
It is further object of the present invention to provide a television receiver which can reduce the number of integrated circuits.
According to one aspect of the present invention, there is provided a television receiver comprising:
(a) a central processing unit having an interrupt function;
(b) a bus means connected to said central processing unit;
(c) a read only memory means connected to said central processing unit through said bus means and containing a control program to be executed by said central processing unit;
(d) a random access memory means connected to said central processing unit through said bus means and used as a work area of said central processing unit;
(e) a channel selecting means connected to said central processing unit through said bus means for selecting one of a plurality of channels and producing a video signal; and
(f) a control signal receiving circuit means connected to said central processing unit through said bus means for receiving a control signal and controlling said channel selecting means;
characterized in that said television receiver comprises:
(g) a shift register means connected to said central processing unit through said bus means;
(h) a clock pulse generating means for supplying a clock pulse to said shift register means synchronized with the synchronizing signal of said video signal and generating a serial signal representing a character pattern from said shift register;
(i) a mixing means for mixing said video signal and said serial signal; and
(j) an interrupt means for interrupting an operation of said central processing unit synchronized with a synchronizing pulse of the video signal, said control program in said read only memory means containing a font data to be displayed, a main program for decoding said control signal and controlling said channel selecting means, and an interrupt program for loading the font data from said read only memory means to said shift register means.
The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like references designate the same elements and parts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of an embodiment of a television receiver according to the present invention;
FIG. 2 is a table showing a 16-bit font data used in the present invention;
FIG. 3 is a diagram showing a screen of the television receiver of the present invention on which a numeral of channel is indicated and waveforms of pulses used in explanation thereof;
FIG. 4 is a diagram showing the format of a remote control signal used in the present invention; and
FIGS. 5 to 8 are respectively flow charts used to explain the operation of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Now, an embodiment of a television receiver according to the present invention will hereinafter be described with reference to the attached drawings.
In FIG. 1 showing an example of the present invention, reference numeral 10 generally designates a video signal system, 11 a tuner, 12 a video intermediate frequency (VIF) amplifier, 13 a video detecting circuit, 14 a video amplifier and 15 a cathode ray tube, respectively. In this case, the tuner 11 is formed as an electronic tuning system which can receive the video signal of a desired channel by changing a value of a tuning voltage Ec supplied thereto.
Reference numeral 20 generally designates a microcomputer, 21 a 4-bit parallel CPU (central processing unit), 22 a ROM (read only memory) in which a program and a font data for indicating a numeral of a channel are written or stored, 23 a RAM (random access memory) for a work area and 31 to 36 input/output ports. These circuits 22 to 36 are connected through a bus 24 to the CPU 21.
Reference numeral 37 designates a 16-bit serial/parallel input and serial output shift register. This shift register 37 is used to generate a signal Sn which indicates the numeral of the channel. To the shift register 37 loaded line by line in parallel is a 16-bit font data indicating the numeral of a channel as, for example, shown in FIG. 2 from the port 32. The font data loaded to the shift register 37 is delievered therefrom in series from MSB (most significant bit) as the signal Sn. At that time, the serial input terminal of the shift register 37 is made at "0" level.
The signal Sn derived from the shift register 37 is supplied to the video amplifier 14 in which the signal Sn is composed on or mixed with the video signal.
The microcomputer 20 together with this shift register 37 is formed as one chip IC (integrated circuit).
Reference numeral 41 designates a D/A (digital-to-analog) converter. The output from the port 31 is supplied to this D/A converter 41 from which the tuning voltage Ec is derived. This tuning voltage Ec is supplied to the tuner 11.
Reference numeral 42 designates a receiving element which receives a remote control signal and 43 its receiving circuit connected thereto. When the remote control signal is, for example, an infrared remote control signal, the receiving element 42 is formed as an infrared ray receiving element and the receiving circuit 43 generates a remote control signal Sr. This remote control signal Sr is the signal which corresponds to an output from a remote control signal transmitter (not shown) and has a format as, for example, shown in FIG. 4. Namely, in this remote control signal, a guide pulse having a pulse width of 2400 μsec exists in the beginning and code pulses of 16 bits from b ₀ to b ₁₅ follow the guide pulse with an interval of 600 μsec. In this case the code pulses b ₀ to b ₁₅ indicate "0" or "1" in respose to the content of the remote control. When "0", the pulse width is selected as 600 μsec, while when "1", the pulse width is selected as 1200 μsec. This remote control signal Sr is supplied to the port 33.
Reference numeral 44 designates a non-volatile memory which is connected to the port 34 and in which a digital value of the tuning voltage Ec at each channel is stored. Reference numeral 45 designates an input key which is used to change the channel, the sound volume and so on, in which the dynamic scan is carried out by the output from the port 35, and the switching output from which is inputted to the port 36 to detect which key is operated.
Reference numeral 51 designates a synchronizing (sync) separating circuit to which the video signal from the video detector circuit 13 is supplied and from which a vertical synchronizing pulse Pv and a horizontal synchronizing pulse Ph are derived respectively. These pulses Pv and Ph are supplied to the CPU 21 as interrputing signals H-INT and V-INT. The pulse Ph is supplied to a monostable multivibrator 52 which generates a pulse P ₅₂ which becomes "1" from a falling down or trailing edge time point t ₁ of the pulse Ph to a start time point t ₂ of the display period of the numeral of the channel as shown in FIG. 3 (in which reference numeral 151 designates the screen of the cathode ray tube). This pulse P ₅₂ is supplied to a gated oscillating circuit 53 as its oscillating control signal so that from the gated oscillating circuit 53 is derived an oscillating pulse P ₅₃ during the period from t ₂ to t ₄ in which the pulse P ₅₂ is "0" as shown in FIG. 3. This pulse P ₅₃ is supplied to the shift register 37 as the clock. At that time, the frequency of the pulse P ₅₃ is selected as a value corresponding to a dot pitch in the lateral direction of the numeral of the channel to be indicated.
Accordingly, since the font data on, for example, the first line in FIG. 2 is loaded to the shift register 37 during the first half period from t ₁ to t ₂ of the 45th horizontal trace period, this font data is extracted from the shift register 37 as the serial signal Sn in response to the pulse P ₅₃ during the second half period from t ₂ to t ₃ of the above horizontal trace period and then supplied to the video amplifier 14, the numeral of the channel on the first line is indicated on the screen 151 in the interval corresponding to the period from t ₂ to t ₃ of the 45th line. Although during the period from t ₃ to t ₄ the pulse P ₅₃ is supplied to the shift register 37, the serial input terminal of the shift register 37 is at "0" level and this "0" level is derived from the shift register 37 during the period from t ₃ to t ₄ so that no numeral of the channel is indicated on the screen 151 in the interval corresponding to the period from t ₃ to t ₄ .
When such operation is performed for the 45th to 51st horizontal lines by employing the font data on the 1st to 7th lines shown in FIG. 2, the channel numeral corresponding to the font data in FIG. 2 is displayed as shown in FIG. 3. If the data of all "0" is loaded to the shift register 37 as the font data, the channel numeral is not indicated.
FIGS. 5 to 8 respectively show flow charts of the programs written in the ROM 22 and FIG. 5 shows the main routine thereof.
This main routine shown in FIG. 5 starts from a step 501 and in a step 502 the initializing is carried out. Thus, a flag FLG, a buffer BUFF and counters CHCNT, HCNT and WCNT are set in, for example, the RAM 23 and these are all reset (cleared) to "0".
A step 503 is such a step in which the existence or not of the remote control signal Sr is judged by the existence or not of the guide pulse, namely, by detecting whether the "1" level of the signal Sr lasts 2400 μsec or not. A step 504 is such a step which judges whether or not there is the input to the key 45, and a step 531 is such a step which judges whether the counter CHCNT is "0" or not. Consequently, when powered, CHCNT=0 is established in the step 502 so that the loop of step 503➝step 504➝step 531➝step 503 is repeated to thereby poll the input of the remote control signal Sr and the input from the key 45. In this case, the counter CHCNT serves as a flag indicative of the existence or not of the request for changing the channel and a timer for setting the displaying period of the channel numeral.
When the remote control signal Sr exists, the bits b ₀ to b ₁₅ of the signal Sr are latched in a step 800 and the step is moved to a step 511. Also when an input exists in the step 504, the step 504 moves to the step 511, too. In the step 511, it is judged whether the remote control input in the step 800 and the key input in the step 504 are the commands for changing the channel or not.
When the above inputs are the command for changing the channel, the counter CHCNT is set to "1" in a next step 512. Subsequently, in a step 513, on the basis of the channel data indicated by the remote control signal Sr inputted at the step 800 and the key input in the step 504, a digital tuning voltage data E _D for tuning to the channel is read out from the non-volatile memory 44 (see FIG. 1). This digital tuning voltage data E _D is outputted to the port 31 in a step 514. Thus, by the analog tuning voltage Ec from the D/A converter 41, the television receiver is set in the receiving state of the channel inputted in the step 800 or 504, thereafter.
In a step 515, from the ROM 22, a font data (data as, for example, shown in FIG. 2) displayed as a numeral of a new channel after the channel is changed is loaded to the buffer BUFF. Although the detail will be described later, the font data in the buffer BUFF is sequentially loaded line by line to the shift register 37 during the 45th to 51st horizontal trace period t ₁ to t ₂ of each field in accordance with a subroutine 700 shown in FIG. 7. As a result, the channel numeral after the channel is changed is indicated on the screen 151.
When the channel numeral is indicated on the screen 151, the procedure step is returned to the step 503. At that time, since CHCNT=1 is established in the step 512, the procedure step is moved in the order of the step 503➝the step 504➝the step 531➝a step 532. In this step 532, the counter CHCNT is incremented by "1" and in a next step 533, whether the count CHCNT reaches a predetermined value MAX or not is checked where the value MAX is the value corresponding to the period during which the channel numeral is displayed upon changing the channel.
And, if CHCNT
When CHCNT=MAX is esbalished, the buffer BUFF is cleared to "0" in a step 541. Therefore, since "0" is loaded through the buffer BUFF to the shift register 37 as the font data, Sn="0" is established thereafter so that the channel numeral is not indicated any more.
In a next step 542, the counter CHCNT is reset to "0" and the procedure step is returned to the step 503.
As described above, when the channel change data is inputted, the channel is changed and the channel numeral after the channel is changed is indicated during a constant period.
When the inputs in the steps 800 and 504 are not the commands for changing the channel but the commands for changing, for example, the sound volume, in a step 521 the counter CHCNT is reset to "0" and then in a step 522, the operation based on the commands inputted in the steps 800 and 504 is carried out. The circuitry for executing the procedure except for changing the channel can be made the same as in the prior art and hence it is omitted to show the same in FIG. 1.
On the other hand, FIGS. 6 and 7 respectively show subroutines in which the font data in the buffer BUFF is loaded to the shift register 37. The subroutine 600 shown in FIG. 6 is the interrupt subroutine which is executed when the interrupt procedure is executed by the vertical synchronizing pulse Pv. When the vertical synchronizing pulse Pv is supplied to the CPU 21, this subroutine 600 starts from a step 601 and in a step 602, the counter HCNT is reset to "0". In a step 603, the subroutine 600 is ended and returned to the original main routine.
Accordingly, by this subroutine 600, the counter HCNT is reset to "0" at every start point of each field.
The subroutine 700 shows in FIG. 7 is the interrupt subroutine which is executed when the interrupt procedure is executed by the horizontal synchronizing pulse Ph. When the horizontal synchronizing pulse Ph is supplied to the CPU 21, the subroutine 700 starts from a step 701 and in a step 702, a flag FLG indicative of whether the subroutine 700 is executed or not is set to "1". Then, in a step 703, the counter HCNT is incremented by "1". In this case, since the counter HCNT is reset to "0" by the subroutine 600 at every start point of each field and the subroutine 700 is executed at each horizontal syncronizing pulse Ph, the counter HCNT indicates the line number of the horizontal line at each field period.
In a next step 704, the magnitude of the counter HCNT is checked. When 45≤HCNT≤51, in a step 711, the font data in the buffer BUFF (the data as, for example, shown in FIG. 2) is loaded line by line to the shift register 37 from the buffer BUFF each time when the counter HCNT is incremented by "1" each (at every horizontal lines). On the other hand, when 45≤HCNT≤51 is not established, in a step 721, all "0" is loaded to the shift register 37. Then, the subroutine 700 is ended at a next step 712 and returned to the original main routine.
If necessary, the subroutine 700 is provided with a timer routine by which the duration of time necessary for completing the subroutine 700 is set as 40 μsec (the period shorter than the period from t ₁ to t ₂ ).
Consequently, during the period from t ₁ to t ₂ in the 45th to 51st horizontal trace periods, by the subroutine 700 the data in the buffer BUFF is loaded to the shift register 37. Then, if the data loaded to the shift register 37 is the font data, the channel numeral is indicated during the period from t ₂ to t ₃ . While during the period from t ₁ to t ₂ in other horizontal trace period, the data indicative of all "0" is loaded to the shift register 37 from the buffer BUFF so that the channel numeral during the period t ₂ to t ₃ is not displayed.
Upon changing the channel, during the predetermined period, the font data regarding the channel numeral after the channel is changed is loaded to the buffer BUFF in the step 515. After that, since the data indicative of all "0" is loaded to the buffer BUFF in the step 541, in accordance with the subroutine 700, during the predetermined period from the change of the channle, the channel numeral after the channel is changed is indicated on the screen 151 as shown in FIG. 3. After the predetermined period elapses, the display is not carried out any more.
FIG. 8 shows a subroutine 800 which is used to read the remote control signal Sr. This subroutine 800 starts from a step 801. In a next step 802, a pointer i is reset to "0" and in a succeeding step 811, a delay corresponding to the "0" level period of 600 μsec between the trailing edge of the guide pulse and the rising edge of the bit b ₀ (see FIG. 4) is carried out. Further, in a next step 821, the counter WCNT is reset to "0". In this case, the pointer i indicates a particular bit of the bits b ₀ to b ₁₅ of the remote control signal Sr and i=0 to 15. Also, the counter WCNT is used to check the respective pulse widths of the bits b ₀ to b ₁₅ .
After the delay of 70 μsec is performed in a succeeding step 822, whether the flag FLG is "0" or "1" is checked in a next step 823. When FLG=0, namely, the interrupt procedure is not executed, the counter WCNT is incremented by "1" in a following step 824. When FLG=1, namely, the interrupt procedure is executed, the counter WCNT is incremented by "2" in a step 825 and the processing time due to the interrupt procedure is corrected. Thereafter, the flag FLG is reset to "0" in a next step 826. Then, in a step 827, it is checked whether the level of ith bit of the remote control signal Sr reaches the "0" level or not, namely, whether ith bit is ended or not. When ith bit is not ended, the step 827 returns to the step 822, while when ended, the step 827 advances to a step 831.
Accordingly, during the period in which the level of ith bit of the signal Sr is at the "1" level, the loop from the steps 822 to 827 is repeated. Upon repeating the loop from the steps 822 to 827, if the interrupt subroutine 700 is not executed at all, the FLG=0. Therefore, in the steps 822 and 824, the counter WCNT is incremented by "1" each at every 40 μsec. Thus, at the time when the above loop is ended, if ith bit is "0" (namely, the pulse width is 600 μsec), WCNT=15, while if ith bit is "1" (namely, the pulse width is 1200 μsec), WCNT=30 (the processing time necessary for other steps is neglected for simplicity).
Upon repeating this loop from the steps 822 to 827, if the interrupt subroutine 700 is executed, 40 μsec is consumed to execute such subroutine. This is the same as that necessary for executing the step 822 once. Also, at that time, since FLG=1 (step 702), the counter WCNT is incremented by "2" in the step 825. As a result, at the time when this loop is ended, if ith bit is "0", WCNT=15, while if ith bit is "1", WCNT=30.
After the above loop is ended, the counter WCNT is checked in the step 831. If WCNT≤15, the level "0" of ith bit is set in the RAM 23 in a step 832, while if WCNT>15, the level "1" of ith bit is set in the RAM 23 in a step 833. In a next step 834, whether the above procedure is executed for all the bits of the remote control signal Sr or not is checked by the pointer i. When the above procedure is not yet executed for all the bits, the pointer i is incremented by "1" in a step 835 and then the step 835 returns to the step 811. On the contrary, when the above procedure is executed for all the bits, the step 834 advances to a step 841.
In the step 841, the remote control signal Sr is judged on the basis of the data in the steps 832 and 833. And, in a step 842, this subroutine 800 is ended and returned to the original main routine.
As set forth above, according to the present invention, it is possible to perform the change of the channel and to indicate the channel numeral at that time. In this case, particularly in accordance with the present invention, the change of the channel and the indication of the channel numeral after the channel is changed are carried out by the use of the ordinary microcomputer 20 so that the time and cost necessary from designing to completing can be reduced extremely. Moreover, when the designing is changed in the midway thereof, the designing can be changed with ease.
Further, the individuality can be given to the character pattern of the numeral of the channel to be indicated with ease. Also, since the number of the ICs can be reduced, this is advantageous for reducing the manufacturing cost and for increasing reliablity.
In addition, in the above description, it is possible to provide the steps 531 to 542 in the subroutine 600.
The above description is given on a single preferred embodiment of the invention, but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the invention, so that the scope of the invention should be determined by the appended claims only.

 

SONY AE1 - AE1A - AE1B - AE1C chassis

CHASSIS - TV - MODEL FAULT / REPAIR LIST:

Model: AE1, AE1A, AE1B, KV-211XML, KV-211XMTL, ...

Subject: NO PICTURE OR DARK PICTURE.(D803,R807)

Symptom: No picture or dark picture

Cause: R 807 is open

Remedy: Change R807 (1K,1 W) and change D803 by another one(RGP02-17)

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: SET GOES IN STAND-BY AFTER A WHILE.(C025,C026)

Symptom: Set goes in stand-by after a while

Cause: Bad reset

Remedy: Change C025 and C026 (4,7 µF)

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: REPROGRAMMING OF PRESETS DOESN'T WORK ANYMORE.(L80

Symptom: Reprogramming of presets doesn't work anymore.

Cause: -30V at pin 2 of IC003 is missing. L807 is open.(-30V is made by FBT)

Remedy: Change L807 The tension you normally messure having this problem is -15V

Model: AE1, AE1A, AE1B, KV-211XML, KV-211XMTL, ...

Subject: NO PICTURE.(C327)

Symptom: No picture

Cause: C327 is defekt on the chroma board.

Remedy: Change C327(0.01µF)

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: DARK PICTURE.(TDA6600)

Symptom: Dark picture

Cause: TDA6600 on the KS board is defekt.

Remedy: Change TDA6600 Perhaps due to overvoltage

Model: AE1, AE1A, AE1B, AE1C, KV-211XML, ...

Subject: INTERMITTENT NO POWER.(CF501)

Symptom: Intermittent no power

Cause: CF501 is unstabel and causes the set to stop running after a while, or sometimes no power up at all.

Remedy: Change CF501.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: No power.(C025,C026)

Symptom: No power.(bad reset)

Cause: C025 is short and hence the reset circuit doesn't work anymore.

Remedy: Change this capacitor.Change preventifly also C026. Sometimes the set starts and stops after a while.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: NO POWER OR NO SOUND.(IC251)

Symptom: No power or no sound. Due to shortage of IC251 the set doesn't power up.

Cause: 251 (. Due to shortage of IC251 the set doesn't power up.)

Remedy: Change power amp. Both symtoms can occur: No sound, or complete shortage causes no power

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: SIZE OF PICTURE CHANGES INTERMITTENT.(D501)

Symptom: Size of picture changes intermittent.

Cause: D501

Remedy: Change this diode.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: INTERMITTENT NO COLOUR.(X332)

Symptom: Intermittent no colour.

Cause: X 332

Remedy: Change X 332 Normally the variabel capacitor of a AE1 chassis is not in cause. (white capacitor)

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: NO PICTURE, NO OSD,TXT AND SOUND OK.(R812)

Symptom: No picture, no OSD, TXT and sound OK.

Cause: R 812 (68 K)

Remedy: Change R812. Normally R 812 is open.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: RATTLE NOISE, ALSO IN STAND-BY.

Symptom: Rattle noise, also in stand-by.

Cause: Bad contacts on audio heathsink.

Remedy: Resolder.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: NO POWER, WHISTLING NOISE.(FBT)

Symptom: No power, whistling noise.

Cause: Flyback transformer.

Remedy: Change FBT.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: NO POWER, SET GOES IN PROTECTION.(C517)

Symptom: No power, set goes in protection.

Cause: C 517 value has changed.

Remedy: Change C 517.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: NO POWER, SET STOPS RUNNING AFTER A WHILE.(R614)

Symptom: No power, or set stops running after a while.

Cause: R 614 has a bad contact.

Remedy: Change R 614. If the damage to the D-board is to big, please check SB TV01392.

Model: AE1, AE1A, AE1B, AE1C, KV-211XML, ...

Subject: NO POWER.(D611)

Symptom: No power.

Cause: Lightening. D 611 is short.

Remedy: Change D611

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: PICTURE IS VERTICAL UNSTABEL.(C592)

Symptom: Picture is vertical unstabel.

Cause: C 592.

Remedy: Change C 592. Symptom is more visabel with high brigtness level!

Model: AE1, AE1A, AE1B, KV-211XML, KV-211XMTL, ...

Subject: NO PICTURE, SOUND OK.(D803,R807)

Symptom: No picture, sound OK.

Cause: D 803 is defect and hence R 807 goes defect.

Remedy: Change D 803 by improved type of diode RGP02-17. Check SB TV02190.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: INTERMITTENT NO PICTURE, SOMETIMES NEGATIVE PICTUR

Symptom: Intermittent no picture, sometimes negative picture.

Cause: Bad contact T 101, T102, T103.

Remedy: Resolder these coils.

Model: AE1, AE1A, AE1B, AE1C, KV-211XML, ...

Subject: PIN DISTORTION.(C815,L806)

Symptom: Pin distortion.

Cause: C 815 is defect and hence L 806 burns.

Remedy: Change both components. Defect is visable when coil L806 has burned.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: BLANKING LINES ON THE PICTURE.(R544)

Symptom: Blanking lines on the picture.

Cause: R 544 value has changed.

Remedy: Change this resistor.

Model: AE1, AE1A, AE1B, AE1C, KV-211XML, ...

Subject: NO PICTURE, ONLY HORIZONTAL LINE.(IC502,R530)

Symptom: No picture, only horizontal line.

Cause: IC 502 is defect.

Remedy: Change IC 502 and check also R 530. Change also C531 and C532.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: SET GOES OFF IN STAND-BY (D607,R623)

Symptom: Set goes off in stand-by.

Cause: D 607 and R 623 are defect.

Remedy: Change both components.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: FLICKERING OR NEGATIVE PICTURE DURING START- UP.

Symptom: Flickering picture.

Cause: C 625 is defect and hence 12V output is not correct.

Remedy: Change this capacitor.

Model: AE1, AE1A, AE1B, AE1C, KV-211XML, ...

Subject: POOR VERTICAL LINEARITY.(C531,C532)

Symptom: Poor vertical linearity.

Cause: C 531 :Top of the picture. C 532 :Bottom of the picture.

Remedy: Change both capacitors.

Model: AE1, AE1A, AE1B, AE1C, KV-211XML, ...

Subject: BLANKING LINES ON THE PICTURE.(R722)

Symptom: Blanking lines on the picture.

Cause: R 722 value has changed.

Remedy: Change this resistor.

Model: AE1, AE1A, AE1B, AE1C, KV-211XML, ...

Subject: PURITY ERROR.(POSITION DEFLECTION YOKE)

Symptom: Purity error.

Cause: Deflection Yoke has changed position backwards.

Remedy: Complete readjustement of purity and linearity as explained in the service manual. Fix scew of the DY securely

and put locking compound to prevent repositio

Model: AE1, AE1A, AE1B, AE1C, KV-211XML, ...

Subject: NO POWER(D 606)

Symptom: No power

Cause: D 606 is leaking.

Remedy: Change this diode.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: NO POWER.(D632)

Symptom: No power.

Cause: D 632 is defect.

Remedy: Change this diode.

Model: AE1, KV-211XML, KV-211XMTL, KV-211XMTU, KV-211XMU, ...

Subject: SET SWITCHES IN STAND-BY.(C612)

Symptom: Set switches in stand-by.

Cause: C 612 has bad contact.

Remedy: Resolder C 612.

Model: AE1

Subject: V LINEARITY FAULT

Symptom: V LINEARITY FAULT

Cause: FAILURE OF C531

Remedy: REPLACE C531 (1-124-190-00) WITH A 680 µF±10%, 25V CAPACITOR (1-107-866-51)

Model: AE1

Subject: Intermittent no power

Symptom: Intermittent no power

Cause: CF501 is unstabel and causes the set to stop running after a while, or sometimes doesn't start at all.

Remedy: Change CF501. Part(s): 1-567-888-11 (CF501)

Model: AE1

Subject: No picture, sound OK.

Symptom: No picture, sound OK.

Cause: D 803 is defect and hence R 807 goes defect.

Remedy: Change D 803 by improved type of diode RGP02-17. Part(s): 8-719-976-64 (D 803)

Model: AE1

Subject: No picture, sound OK.

Symptom: No picture, sound OK.

Cause: D 803 is defect and hence R 807 goes defect.

Remedy: Change D 803 by improved type of diode RGP02-17. Part(s): 8-719-976-64 (D 803)

Model: AE1

Subject: Intermittent no picture, sometimes negative pictur

Symptom: Intermittent no picture, sometimes negative picture.

Cause: Bad contact T 101, T102, T103.

Remedy: Resolder these coils. Part(s): (T101)

Model: AE1

Subject: Set goes in stand-by after a while

Symptom: Set goes in stand-by after a while

Cause: Bad reset

Remedy: Change C025 and C026 (4,7 µF) Part(s): 1 102 125 00 (C025) 1 102 125 00 (C026

Model: AE1

Subject: Pin distortion.

Symptom: Pin distortion.

Cause: C 815 is defect and hence L 806 burns.

Remedy: Change both components. Part(s): Check SM (L806) Check SM (C815

Model: AE1

Subject: Blanking lines op the picture.

Symptom: Blanking lines op the picture.

Cause: R 544 value has changed.

Remedy: Change this resistor. Part(s): 1-247-745-11 (R 544)

Model: AE1

Subject: No picture, only horizontal line.

Symptom: No picture, only horizontal line.

Cause: IC 502 is defect.

Remedy: Change IC 502 and check also R 530. Change also C531 and C532. Part(s): 8-759-944-57 (C502) 1-249-448-11

(R530

Model: AE1

Subject: Reprogramming of presets doesn't work anymore.

Symptom: Reprogramming of presets doesn't work anymore.

Cause: -30V at pin 2 of IC003 is missing. L807 is open.(-30V is made by FBT)

Remedy: Change L807 Part(s): 1-408-242-00 (L 807)

Model: AE1

Subject: No picture

Symptom: No picture

Cause: C327 is defekt on the chroma board.

Remedy: Change C327(0.01µF) Part(s): 1-101-104-00 (C 327)

Model: AE1

Subject: Dark picture

Symptom: Dark picture

Cause: TDA6600 on the KS board is defekt.

Remedy: Change TDA6600 Part(s): 8-759-013-17 (IC 201)

Model: AE1

Subject: No power.(bad reset)

Symptom: No power.(bad reset)

Cause: C025 is short and hence the reset circuit doesn't work anymore.

Remedy: Change this capacitor.Change preventifly also C026. Part(s): 1-102-125-00 (C025) 1-102-125-00 (C026

Model: AE1

Subject: No power or no sound.

Symptom: No power or no sound.

Cause: IC 251

Remedy: Change power amp. Part(s): 8-759-803-31 (IC 251) 8-759-803-31 (IC251

Model: AE1

Subject: Size of picture changes intermittent.

Symptom: Size of picture changes intermittent.

Cause: D501

Remedy: Change this diode. Part(s): 8-719-911-19 (D501)

Model: AE1

Subject: Intermittent no colour.

Symptom: Intermittent no colour.

Cause: X 332

Remedy: Change X 332 Part(s): 1-567-131-11 (X 332)

Model: AE1

Subject: No picture, no OSD, TXT and sound OK.

Symptom: No picture, no OSD, TXT and sound OK.

Cause: R 812 (68 K)

Remedy: Change R812. Part(s): 1-244-917-00 (R 812)

Model: AE1

Subject: Rattle noise, also in stand-by.

Symptom: Rattle noise, also in stand-by.

Cause: Bad contacts on audio heathsink.

Remedy: Resolder. Part(s): (IC 601)

Model: AE1

Subject: No power, whistling noise.

Symptom: No power, whistling noise.

Cause: Flyback transformer.

Remedy: Change FBT. Part(s): Check SM (FBT)

Model: AE1

Subject: No power, set goes in protection.

Symptom: No power, set goes in protection.

Cause: C 517 value has changed.

Remedy: Change C 517. Part(s): 1-124-252-00 (C 517)

Model: AE1

Subject: No power, set goes in protection.

Symptom: No power, set goes in protection.

Cause: C 517 value has changed.

Remedy: Change C 517. Part(s): 1-124-252-00 (C 517)

Model: AE1

Subject: No power, or set stops running after a while.

Symptom: No power, or set stops running after a while.

Cause: R 614 has a bad contact.

Remedy: Change R 614. Part(s): 1-205-919-11 (R614)

Model: AE1

Subject: No power.

Symptom: No power.

Cause: Lightening. D 611 is short.

Remedy: Change D611 Part(s): Check SM (D 611)

Model: AE1

Subject: Picture is vertical unstabel.

Symptom: Picture is vertical unstabel.

Cause: C 592.

Remedy: Change C 592. Part(s): 1-124-122-11 (C592)

Model: AE1

Subject: Set goes off in stand-by.

Symptom: Set goes off in stand-by.

Cause: D 607 and R 623 are defect.

Remedy: Change both components. Part(s): 8-719-300-33 (D607) 1-249-385-00 (R623

Model: AE1

Subject: Flickering picture.

Symptom: Flickering picture.

Cause: C 625 is defect and hence 12V output is not correct.

Remedy: Change this capacitor. Part(s): 1-124-360-00 (C 625)

Model: AE1

Subject: Poor vertical linearity.

Symptom: Poor vertical linearity.

Cause: C 531 :Top of the picture. C 532 :Bottom of the picture.

Remedy: Change both capacitors. Part(s): 1-128-576-11 (C 532) 1-126-231-11 (C 531

Model: AE1

Subject: Blanking lines on the picture.

Symptom: Blanking lines on the picture.

Cause: R 722 value has changed.

Remedy: Change this resistor. Part(s): 1-244-941-00 (R 722)

Model: AE1

Subject: Purity error.

Symptom: Purity error.

Cause: Deflection Yoke has changed position backwards.

Remedy: Complete readjustement of purity and linearity as explained in the service manual. Part(s): (DY)

Model: AE1

Subject: No power

Symptom: No power

Cause: D 606 is leaking.

Remedy: Change this diode. Part(s): 8-719-300-33 (D 606)

Model: AE1

Subject: No power.

Symptom: No power.

Cause: D 632 is defect.

Remedy: Change this diode. Part(s): 8-719-110-16 (D 632)

Model: AE1

Subject: Set switches in stand-by.

Symptom: Set switches in stand-by.

Cause: C 612 has bad contact.

Remedy: Resolder C 612. Part(s): (C 612)

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: NO COLOUR, OR INTERMITTENT NO COLOUR.(CT302,CT332)

Symptom: No colour, or intermittenly no colour

Cause: Value of CT302 or CT332 changes, due to a bad contact internally

Remedy: Change variable capacitor by a fix one with a value of 15pF Check SB TV01500!!!!!!!

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: POWER SUPPLY POWERS UP, BUT STOPS AFTER 4 X.(C605,

Symptom: Power supply tryes to start up, but stops after 4 times

Cause: Values of C605 and C617 have changed, and due to this the load of the chassis is to high to start the set.

Remedy: Change C605 and C617. Warming up the capacitors can sometim

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: SOMETIMES NO POWER.(C504)

Symptom: TV doesn't start intermittenly, +B is 100V .

Cause: C 504 is defekt.

Remedy: Change C 504

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: SET CHANGES INTERMITTENT PRESELECTION.(IC005)

Symptom: Set changes intermittent his preselection.

Cause: Heating causes IC005 to become unstabel.(SDA 2546)

Remedy: Change this IC and reinitialate this new IC. Reinitialation: Start the set by pressing prog+ and prog-, and the

power switch at

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: PLOP NOISE.

Symptom: Plop-noise in speakers

Cause: 1)bad connections at IC251,IC261. 2)IC251 and IC261 are defect. 3)bad contacts at IC604 (5V stabilisor)

Remedy: 1)resoldering 2)change both ic's. 3)resolder IC604

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: NO PICTURE.(Q332)

Symptom: No picture

Cause: Q332 is short on B or B1 board.(chroma board)

Remedy: Change this Q332.

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: NO POWER.(C518, Q804)

Symptom: No power. (PSU is OK, but set doesn't start.

Cause: C518 value has changed and hence Q804 has become short. Sometimes even IC501 can be defect.

Remedy: Controle and change these components.

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: INTERMITTENT NO POWER ON OR CYCLIC POWER ON/OFF.(C604)

Symptom: Cyclic power ON/OFF (constantly)

Cause: Value off C604 has changed and hence the set doesn't power up any more.

Remedy: Change C604

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: PIN DISTORTION.(IC1501,D1506)

Symptom: Pin distortion.

Cause: IC 1501 and D 1506 are defect.

Remedy: Change both components.

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: FAULTY VERTICAL DEFLECTION.(R570)

Symptom: Faulty vertical deflection.

Cause: R 570 value has changed.

Remedy: Change this resistor.

Model: AE1A, AE1B, AE1C, KV2951A, KV-A2110B, ...

Subject: GREENISH PICTURE.(C339)

Symptom: Greenish picture.

Cause: C339 is defect.

Remedy: Change this capacitor.

Model: AE1A

Subject: V LINEARITY FAULT

Symptom: V LINEARITY FAULT

Cause: FAILURE OF C531

Remedy: REPLACE C531 (1-124-190-00) WITH A 680 µF±10%, 25V CAPACITOR (1-107-866-51)

Model: AE1A

Subject: Plop-noise in speakers

Symptom: Plop-noise in speakers

Cause: 1)bad connections at IC251,IC261. 2)IC251 and IC261 are defect. 3)bad contacts at IC604 (5V stabilisor)

Remedy: 1)resoldering 2)change both ic's. 3)resolder IC604 Part(s): 8-759-988-94 (IC251) 8-759-988-

Model: AE1A

Subject: No picture

Symptom: No picture

Cause: Q332 is short on B or B1 board.(chroma board)

Remedy: Change this Q332. Part(s): 8-729-216-22 (Q332)

Model: AE1A

Subject: No power. (PSU is OK, but set doesn't start.

Symptom: No power. (PSU is OK, but set doesn't start.

Cause: C518 value has changed and hence Q804 has become short. Sometimes even IC501 can be defect.

Remedy: Controle and change these components. Part(s): 1-124-902-00 (C 518) 8-729-304-50

Model: AE1A

Subject: No colour, or intermittenly no colour

Symptom: No colour, or intermittenly no colour

Cause: Value of CT302 or CT332 changes, due to a bad contact internally

Remedy: Change variable capacitor by a fix one with a value of 15pF. Part(s): 1 102 316 00 (CT 332)

Model: AE1A

Subject: No picture or dark picture

Symptom: No picture or dark picture

Cause: R 807 is open

Remedy: Change R807 (1K,1 W) and change D803 by another one(RGP02-17) Part(s): 871997664 (D 803) 121777811 (R

807

Model: AE1A

Subject: Power supply tryes to start up, but stops after 4

Symptom: Power supply tryes to start up, but stops after 4 times

Cause: Values of C605 and C617 have changed, and due to this the load of the chassis is to high to start the set.

Remedy: Change C605 and C617. Part(s): 1-124-484-11 (C 605) 1-124-1

Model: AE1A

Subject: TV doesn't start intermittenly, +B is 100V .

Symptom: TV doesn't start intermittenly, +B is 100V .

Cause: C 504 is defekt.

Remedy: Change C 504 Part(s): 1-163-121-00 (C 504)

Model: AE1A

Subject: Cyclic power ON/OFF (constantly)

Symptom: Cyclic power ON/OFF (constantly)

Cause: Value off C604 has changed and hence the set doesn't power up any more.

Remedy: Change C604 Part(s): 1-124-484-11 (C604)

Model: AE1A

Subject: Pin distortion.

Symptom: Pin distortion.

Cause: IC 1501 and D 1506 are defect.

Remedy: Change both components. Part(s): 8-759-942-16 (IC1501) 8-719-931-66 (D 1506

Model: AE1A

Subject: Vertical folding picture.

Symptom: Vertical folding picture.

Cause: R 570 value has changed.

Remedy: Change this resistor. Part(s): 1-216-045-00 (R 570)

Model: AE1A

Subject: Greenish picture.

Symptom: Greenish picture.

Cause: C339 is defect.

Remedy: Change this capacitor. Part(s): 1-106-220-00 (C339)

Model: AE1B, AE1C, KV2951A, KV-A2110B, KV-A2111A, ...

Subject: DARK PICTURE.(Q608)

Symptom: Picture is very dark.

Cause: Q608 is leaking

Remedy: Change Q608

Model: AE1B, AE1C, KV2951A, KV-A2110B, KV-A2111A, ...

Subject: NO POWER.(C611,Q602)

Symptom: No power

Cause: Q 602 is short.

Remedy: Change Q 602, but change also C611. This capacitor has maybe changed value and hence Q 602 goes short.

Control also R600 and R643 before powering on the set.

Model: AE1B, AE1C, KV2951A, KV-A2110B, KV-A2111A, ...

Subject: NO POWER.(D1504)

Symptom: No power

Cause: The TDA 2028 gives no H-pulses at the start up. When we measure at pin 12 , we have 5V DC. In fact D1504 is

leaking. (D1504 you can find on the J board.)

Remedy: Change D 1504.

Model: AE1B

Subject: V LINEARITY FAULT

Symptom: V LINEARITY FAULT

Cause: FAILURE OF C531

Remedy: REPLACE C531 (1-124-190-00) WITH A 680 µF±10%, 25V CAPACITOR (1-107-866-51)

Model: AE1B

Subject: INTERMITTENTLY NO SOUND, OR A CRACKING NOISE IS AU

Symptom: INTERMITTENTLY NO SOUND, OR A CRACKING NOISE IS AUDIBLE, ESPECIALLY WHEN SUBJECT TO

MECHANICAL SHOCKS

Cause: HE PROBLEM IS CAUSED BY THE POOR SOLDERING OF THE PINS OF IC 261 TDA 2052 (AUDIO OUT, R-CH)

ON THE D-BOARD. MOSTLY PINS 2,4 A

Model: AE1B

Subject: Picture is very dark.

Symptom: Picture is very dark.

Cause: Q608 is leaking

Remedy: Change Q608 Part(s): 8-729-120-28 (Q 608)

Model: AE1B

Subject: No power

Symptom: No power

Cause: Q 602 is short.

Remedy: Change Q 602, but change also C611. This capacitor has maybe changed value and hence Q 602 goes short.

Part(s): 8-729-209-02 (Q602) 1-124-910-11 (C611

Model: AE1B

Subject: Picture is deformed on the lower part.

Symptom: Picture is deformed on the lower part.

Cause: Value of C531 has changed.

Remedy: Change C531 with same value(680 µF)but use a capacitor of 105° Part(s): 1 111 123 11 (C531)

Model: AE1B

Subject: No power

Symptom: No power

Cause: The TDA 2028 gives no H-pulses at the start up. When we measure at pin 12 , we have 5V DC. In fact D1504 is

leaking. (D1504 you can find on the J board.)

Remedy: Change D 1504. Part(s): 8-719-911-19 (D 1504)

Model: AE1C, KV2951A, KV-A2110B, KV-A2111A, KV-A2111B, ...

Subject: NO PICTURE OR INTERMITTENT NO PICTURE.(Q608)

Symptom: No picture or intermittent no picture

Cause: Q 608 is leaking and changes SCP.

Remedy: Change Q608

Model: AE1C, KV2951A, KV-A2110B, KV-A2111A, KV-A2111B, ...

Subject: UNSTABEL IMAGE AND LOSS OF COLOUR.(IC310, SET WITH DIG. COMB FILTER)

Symptom: Unstabel image and los of colour.

Cause: IC310 (CXD2011Q)has bad contacts.

Remedy: Resolder IC 310

Model: AE1C, KV2951A, KV-A2110B, KV-A2111A, KV-A2111B, ...

Subject: CYCLIC POWER ON/OFF.(C605,C617)

Symptom: Cyclic power ON/OFF(3 or 4 times)

Cause: Values off C605 and C617 have changed.

Remedy: Change both capacitors This phenomen can also be caused by IC 601

Model: AE1C, KV2951A, KV-A2110B, KV-A2111A, KV-A2111B, ...

Subject: INTERMITTENT NO PICTURE.(IC02)

Symptom: Intermitent no picture

Cause: IC02 on the V-board is defekt(SAA5246P/E).

Remedy: Change this IC02 An easy way to know if V-board is in cause, is to pull out this board and to make the connection

TXT-CUT at the componentside of the D-boar

Model: AE1C, KV2951A, KV-A2110B, KV-A2111A, KV-A2111B, ...

Subject: MOZAIK NOISE.(IC310)

Symptom: Mosa< noise>Cause: IC310 (CXD2011Q) is defect.

Remedy: Change IC310

Model: AE1C, KV2951A, KV-A2110B, KV-A2111A, KV-A2111B, ...

Subject: LOSS OF COLOUR AND SYNC WHEN EDITING VIDEOTAPES.

Symptom: Loss of colour and sync by editing videotapes.

Remedy: Put a capacitor of 33 microF between pin 9 and ground. Only for Models equipped with a digital comb filter.

Model: AE1C, KV2951A, KV-A2110B, KV-A2111A, KV-A2111B, ...

Subject: NO PICTURE.(Q330)

Symptom: No picture

Cause: Q330 is defect.

Remedy: Change this transistor

Model: AE1C

Subject: V LINEARITY FAULT

Symptom: V LINEARITY FAULT

Cause: FAILURE OF C531

Remedy: REPLACE C531 (1-124-190-00) WITH A 680 µF±10%, 25V CAPACITOR (1-107-866-51)

Model: AE1C

Subject: AFTER SWITCHING INTO STANDBY MODE IT'S IMPOSSIBLE

Symptom: AFTER SWITCHING INTO STANDBY MODE IT'S IMPOSSIBLE TO SWITCH THE SET ON AGAIN

Cause: +B VOLTAGE TOO LOW (<130V) WHICH PREVENTS SWITCHING ON THE TV-SET FROM STANDBY

Remedy: ADJUST RV601 (STANDBY +B VOLTAGE ADJ.) FOR CORRECT +B VOLTAGE

Model: AE1C

Subject: V-SIZE TOO LOW

Symptom: V-SIZE TOO LOW

Cause: THE VALUE OF R522 CHANGED WHICH RESULTS IN A TOO HIGH +B VOLTAGE (±160V)

Remedy: REPLACE R522

Model: AE1C

Subject: BLACK HORIZONTAL STRIPES OVER THE ENTIRE PICTURE

Symptom: BLACK HORIZONTAL STRIPES OVER THE ENTIRE PICTURE

Cause: VALUE OF R544 CHANGED

Remedy: REPLACE R544

Model: AE1C

Subject: TOP PART OF PICTURE EXPANDED, BOTTOM PART COMPRESS

Symptom: TOP PART OF PICTURE EXPANDED, BOTTOM PART COMPRESSED

Cause: CAPACITOR C521 DEFECT

Remedy: REPLACE C521

Model: AE1C

Subject: VERTICAL LINES CURVED IN THE CORNERS OF THE SCREEN

Symptom: VERTICAL LINES CURVED IN THE CORNERS OF THE SCREEN

Cause: C1514 DEFECT

Remedy: REPLACE C1514

Model: AE1C

Subject: INTERMITTENTLY NO SOUND, OR A CRACKING NOISE IS AU

Symptom: INTERMITTENTLY NO SOUND, OR A CRACKING NOISE IS AUDIBLE, ESPECIALLY WHEN SUBJECT TO

MECHANICAL SHOCKS

Cause: HE PROBLEM IS CAUSED BY THE POOR SOLDERING OF THE PINS OF IC 261 TDA 2052 (AUDIO OUT, R-CH)

ON THE D-BOARD. MOSTLY PINS 2,4 A

Model: AE1C

Subject: INTERFERENCE (BEAT) IN THE PICTURE OF MODELS EQUIP

Symptom: INTERFERENCE (BEAT) IN THE PICTURE OF MODELS EQUIPPED WITH THE TUNER BTP-EC401.

Cause: STRONG UHF SIGNALS CAUSE INTERFERENCE ON THE VHF SIGNALS.

Remedy: REPLACE THE TUNER WITH THE IMPROVED TYPE WITH PART NUMBER 1-465-611-23. NOTE TH

Model: AE1C

Subject: No picture or intermittent no picture

Symptom: No picture or intermittent no picture

Cause: Q 608 is leaking and changes SCP.

Remedy: Change Q608 Part(s): 8-729-120-28 (Q 608)

Model: AE1C

Subject: Unstabel image and los of colour.

Symptom: Unstabel image and los of colour.

Cause: IC310 (CXD2011Q)has bad contacts.

Remedy: Resolder IC 310 Part(s): 8-752-337-07 (IC310)

Model: AE1C

Subject: Set changes intermittent his preselection.

Symptom: Set changes intermittent his preselection.

Cause: Heating causes IC005 to become unstabel.(SDA 2546)

Remedy: Change this IC and reinitialate this new IC. Reinitialation: Start the set by pressing prog+ and prog-, and the

power switch at the

Model: AE1C

Subject: Cyclic power ON/OFF(3 or 4 times)

Symptom: Cyclic power ON/OFF(3 or 4 times)

Cause: Values off C605 and C617 have changed.

Remedy: Change both capacitors Part(s): 1-124-484-11 (C 605) 1-124-122-11 (C 617) 8-759-988-95 (IC 601)

Model: AE1C

Subject: Intermitent no picture

Symptom: Intermitent no picture

Cause: IC02 on the V-board is defekt(SAA5246P/E).

Remedy: Change this IC02 Part(s): 8-759-510-46 (IC02)

Model: AE1C

Subject: Mosaïc noise

Symptom: Mosaïc noise

Cause: IC310 (CXD2011Q) is defect.

Remedy: Change IC310 Part(s): 8-752-337-07 (IC310)

Model: AE1C

Subject: Loss of colour and sync by editing videotapes.

Symptom: Loss of colour and sync by editing videotapes.

Remedy: Put a capacitor of 33 microF between pin 9 and ground. Part(s): (C ...)

Model: AE1C

Subject: No picture

Symptom: No picture

Cause: Q330 is defect.

Remedy: Change this transistor Part(s): 8-729-216-22 (Q 330)

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AE-1A Sony KVE2511

AE-1A Sony KV-E2512

AE-1A Sony KVE2911

AE1B SONY KVC2121

AE1B SONY KVC2121D

AE1B SONY KVC2160B

AE1B SONY KVC2161B

AE1B SONY KVC2521D

AE1B SONY KVC2523D

AE1B SONY KVC2523E

AE1B SONY KVC2531D

AE1B SONY KVC2533D

AE1B SONY KVC2560B

AE1B SONY KVC2920B

AE1B SONY KVC2921B

AE1B SONY KVC2930B

AE1B SONY KVC2931

AE1B SONY KVC2931B

AE1B SONY KVC2931D

AE1B SONY KVC2960B

AE1B SONY KVX2130

AE1B SONY KVX2132

AE1B SONY KVX2132U

AE1B SONY KVX2531D

AE1B SONY KVX2532

AE1B SONY KVX2532U

AE1B SONY KVX2930B

AE1B SONY KVX2931D

AE1B SONY KVX2932U

AE1B SONY KVC2520B

AE1B SONY KVC2521K

AE1B SONY KVC2523D

AE1B SONY KVC2530B

AE1B SONY KVC2531D

AE1B SONY KVC2533D

AE1B SONY KVC2921K

AE1B SONY KVC2923E

AE1B SONY KVC2930B

AE1B Sony KVC2931D

AE1B SONY KVC2931D

AE1B SONY KVC2933E

AE1B SONY KVX2130B

AE1B Sony KVX2131

AE1B SONY KVX2131D

AE1B Sony KVX2132

AE1B SONY KVX2132U

AE1B Sony KVX2133

AE1B SONY KVX2133D

AE1B SONY KVX2530B

AE1B Sony KVX2531

AE1B SONY KVX2531K

AE1B Sony KVX2532

AE1B SONY KVX2532U

AE1B SONY KVX2533E

AE1B SONY KVX2930B

AE1B SONY KVX2931D

AE1B Sony KVX2932

AE1B SONY KVX2932U

AE1B SONY KVX2933E

AE-1B Sony KVC2521

AE-1B Sony KVC2523

AE-1B Sony KVC2531

AE-1B Sony KVC2533

AE-1B Sony KVC2921

AE-1B Sony KVC2923

AE-1B Sony KVC2931

AE-1B Sony KVC2933

AE-1B Sony KV-X2533

AE-1B Sony KVX2931

AE-1B Sony KVX2933

AE1C SONY KV2921D

AE1C SONY KVA2110B

AE1C SONY KVA2111

AE1C SONY KVA2111B

AE1C SONY KVA2111D

AE1C SONY KVA2112

AE1C SONY KVA2112U

AE1C SONY KVA2120B

AE1C SONY KVA2121A

AE1C SONY KVA2121B

AE1C SONY KVA2121D

AE1C SONY KVA2122U

AE1C SONY KVA2510B

AE1C SONY KVA2511

AE1C SONY KVA2511B

AE1C SONY KVA2511D

AE1C SONY KVA2512

AE1C SONY KVA2512U

AE1C SONY KVA252

AE1C SONY KVA2520B

AE1C SONY KVA2521A

AE1C SONY KVA2521B

AE1C SONY KVA2521D

AE1C SONY KVA2522U

AE1C SONY KVA2910B

AE1C SONY KVA2911D

AE1C SONY KVA2912U

AE1C SONY KVA2920B

AE1C SONY KVA2921A

AE1C SONY KVA2921B

AE1C SONY KVA2921D

AE1C SONY KVA2922U

AE1C SONY KVC2120B

AE1C SONY KVC2121B

AE1C SONY KVC2122U

AE1C SONY KVC2161C

AE1C SONY KVC2161D

AE1C SONY KVC2163E

AE1C SONY KVC2520

AE1C SONY KVC2520B

AE1C SONY KVC2521DMKII

AE1C SONY KVC2522U

AE1C SONY KVC2530B

AE1C SONY KVC2531DMKII

AE1C SONY KVC2551D

AE1C SONY KVC2551DMK2

AE1C SONY KVC2561D

AE1C SONY KVC2563E

AE1C SONY KVC2569D

AE1C SONY KVC2571D

AE1C SONY KVC2921

AE1C SONY KVC2921D

AE1C SONY KVC2921DMKII

AE1C SONY KVC2923E

AE1C SONY KVC2931DMKII

AE1C SONY KVC2941D

AE1C SONY KVC2949D

AE1C SONY KVC2951D

AE1C SONY KVC2961D

AE1C SONY KVC2963E

AE1C SONY KVC2969D

AE1C SONY KVC2971D

AE1C SONY KVE2521

AE1C SONY KVE2521B

AE1C SONY KVE2521D

AE1C SONY KVE2522U

AE1C SONY KVE2912

AE1C SONY KVE2921B

AE1C SONY KVE2921D

AE1C SONY KVE2922

AE1C SONY KVE2922U

AE1C SONY KVE2925U

AE1C SONY KVE2931D

AE1C SONY KVE3431D

AE1C SONY KVH2511D

AE1C SONY KVM1212U

AE1C SONY KVM2521D

AE1C SONY KVM2521U

AE1C SONY KVM2531D

AE1C SONY KVM2531U

AE1C SONY KVX2130B

AE1C SONY KVX2131

AE1C SONY KVX2131D

AE1C SONY KVX2131DMKII

AE1C SONY KVX2141D

AE1C SONY KVX2142U

AE1C SONY KVX2151D

AE1C SONY KVX2151U

AE1C SONY KVX2152U

AE1C SONY KVX2530B

AE1C SONY KVX2531

AE1C SONY KVX2541D

AE1C SONY KVX2542U

AE1C SONY KVX2545U

AE1C SONY KVX2545U3D

AE1C SONY KVX2550B

AE1C SONY KVX2551D

AE1C SONY KVX2552U

AE1C SONY KVX2931

AE1C SONY KVX2931DMKII

AE1C SONY KVX2941D

AE1C SONY KVX2942U

AE1C SONY KVX2950B

AE1C SONY KVX2951D

AE1C SONY KVX2952U

AE1C SONY KCC2570B

AE1C SONY KVA2110B

AE1C SONY KVA2111D

AE1C Sony KVA2112

AE1C SONY KVA2112U

AE1C SONY KVA2113E

AE1C SONY KVA2120B

AE1C SONY KVA2121D

AE1C SONY KVA2122U

AE1C SONY KVA2123E

AE1C SONY KVA2510B

AE1C SONY KVA2511D

AE1C Sony KVA2512

AE1C SONY KVA2512U

AE1C SONY KVA2513B

AE1C SONY KVA2520B

AE1C SONY KVA2521K

AE1C Sony KVA2522

AE1C SONY KVA2522U

AE1C SONY KVA2523E

AE1C SONY KVA2910B

AE1C SONY KVA2911D

AE1C Sony KVA2912

AE1C SONY KVA2912U

AE1C Sony KVA2913

AE1C SONY KVA2913E

AE1C SONY KVA2920B

AE1C SONY KVA2921K

AE1C Sony KVA2922

AE1C SONY KVA2922U

AE1C SONY KVA2923E

AE1C SONY KVC2120B

AE1C SONY KVC2121D

AE1C Sony KVC2122

AE1C SONY KVC2122U

AE1C SONY KVC2123E

AE1C SONY KVC2160B

AE1C SONY KVC2161D

AE1C SONY KVC2163E

AE1C Sony KVC2522

AE1C SONY KVC2522U

AE1C SONY KVC2540B

AE1C SONY KVC2543E

AE1C SONY KVC2550B

AE1C SONY KVC2551D

AE1C SONY KVC2560B

AE1C SONY KVC2561D

AE1C SONY KVC2563E

AE1C SONY KVC2569D

AE1C SONY KVC2571D

AE1C SONY KVC2573E

AE1C SONY KVC2941D

AE1C SONY KVC2949D

AE1C SONY KVC2950B

AE1C SONY KVC2951D

AE1C SONY KVC2953E

AE1C SONY KVC2960B

AE1C SONY KVC2961D

AE1C SONY KVC2963E

AE1C SONY KVC2969D

AE1C SONY KVC2970B

AE1C SONY KVC2971D

AE1C SONY KVC2973E

AE1C SONY KVD2531A

AE1C SONY KVD2533E

AE1C SONY KVD2931A

AE1C SONY KVD2933E

AE1C SONY KVE2521D

AE1C Sony KVE2522

AE1C SONY KVE2522U

AE1C SONY KVE2523E

AE1C Sony KVE2921D

AE1C Sony KVE2921D

AE1C SONY KVE2921D

AE1C Sony KVE2922U

AE1C SONY KVE2922U

AE1C SONY KVE2923E

AE1C Sony KVE2925

AE1C SONY KVE2925U

AE1C SONY KVM2520K

AE1C Sony KVM2521

AE1C SONY KVM2521K

AE1C SONY KVM2530K

AE1C Sony KVM2531

AE1C Sony KVM2531K

AE1C SONY KVM2531K

AE1C SONY KVM2901E

AE1C SONY KVX2140B

AE1C SONY KVX2141D

AE1C Sony KVX2142

AE1C SONY KVX2142U

AE1C SONY KVX2150B

AE1C SONY KVX2151D

AE1C Sony KVX2152

AE1C SONY KVX2152U

AE1C SONY KVX2153E

AE1C Sony KVX2521

AE1C SONY KVX2539B

AE1C SONY KVX2540B

AE1C SONY KVX2541K

AE1C Sony KVX2542

AE1C SONY KVX2542U

AE1C Sony KVX2545

AE1C SONY KVX2545U

AE1C SONY KVX2550B

AE1C SONY KVX2551K

AE1C Sony KVX2552

AE1C SONY KVX2552U

AE1C SONY KVX2553E

AE1C SONY KVX2931K

AE1C SONY KVX2940B

AE1C SONY KVX2941D

AE1C Sony KVX2942

AE1C SONY KVX2942U

AE1C SONY KVX2950B

AE1C SONY KVX2951K

AE1C Sony KVX2952

AE1C SONY KVX2952U

AE1C SONY KVX2953E

AE-1C Sony KVA2111

AE-1C Sony KVA2523

AE-1C Sony KVA2923

AE-1C Sony KVC2121

AE-1C Sony KVC2123

AE-1C Sony KVC2163

AE-1C Sony KVC2561

AE-1C Sony KVC2563

AE-1C Sony KVC2573

AE-1C Sony KVC2951

AE-1C Sony KVC2953

AE-1C Sony KVC2963

AE-1C Sony KVC2973

AE-1C Sony KVE2521

AE-1C Sony KVE2523

AE-1C Sony KVE2921

AE-1C Sony KVE2922

AE-1C Sony KVE2923

AE-1C Sony KVH2513

AE-1C Sony KVX2153

AE-1C Sony KVX2163

AE-1C Sony KV-X2553

AE1-C Sony KVA2123

AE1-C Sony KVA2511

AE1-C Sony KVA2513