SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) CIRCUITS DESCRIPTIONS:
SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) Synchronized switch-mode power supply:
In a switch mode power supply, a first switching transistor is coupled to a primary winding of an isolation transformer. A second switching transistor periodically applies a low impedance across a second winding of the transformer that is coupled to an oscillator for synchronizing the oscillator to the horizontal frequency. A third winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a DC control voltage in the capacitor that varies in accordance with a supply voltage B+. The control voltage is applied via the transformer to a pulse width modulator that is responsive to the oscillator output signal for producing a pulse-width modulated control signal. The control signal is applied to a mains coupled chopper transistor for generating and regulating the supply voltage B+ in accordance with the pulse width modulation of the control signal.
The invention relates to switch-mode power supplies.
Some television receivers have signal terminals for receiving, for example, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR or a teletext decoder.
To simplify the coupling of signals between the external devices and the television receiver, the common conductors of the receiver and of the external devices are connected together so that all are at the same potential. The signal lines of each external device are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as of the television receiver, may be held "floating", or conductively isolated, relative to the corresponding AC mains supply source that energizes the device. When the common conductor is held floating, a user touching a terminal that is at the potential of the common conductor will not suffer an electrical shock.
Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials of the terminals of the AC mains supply source that provide power to the television receiver. Such isolation is typically achieved by a transformer. The isolated common conductor is sometimes referred to as a "cold" ground conductor.
r supply (SMPS) of a television receiver the AC mains supply voltage is coupled, for example, directly, and without using transformer coupling, to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced that is, for example, referenced to a common conductor, referred to as "hot" ground, and that is conductively isolated from the cold ground conductor. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of an isolating flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce a DC output supply voltage such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver. The primary winding of the flyback transformer is, for example, conductively coupled to the hot ground conductor. The secondary winding of the flyback transformer and voltage B+ may be conductively isolated from the hot ground conductor by the hot-cold barrier formed by the transformer.
It may be desirable to synchronize the operation of the chopper transistor to horizontal scanning frequency for preventing the occurrence of an objectionable visual pattern in an image displayed in a display of the television receiver.
It may be further desirable to couple a horizontal synchronizing signal that is referenced to the cold ground to the pulse-width modulator that is referenced to the hot ground such that isolation is maintained.
A synchronized switch mode power supply, embodying an aspect of the invention, includes a transfromer having first and second windings. A first switching arrangement is coupled to the first winding for generating a first switching current in the first winding to periodically energize the second winding. A source of a synchronizing input signal at a frequency that is related to a deflection frequency is provided. A second switching arrangement responsive to the input signal and coupled to the second winding periodically applies a low impedance across the energized second winding that by transformer action produces a substantial increase in the first switching current. A periodic first control signal is generated. The increase in the first switching current is sensed to synchronize the first control signal to the input signal. An output supply voltage is generated from an input supply voltage in accordance with the first control signal.
SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) Switch-mode power supply with burst mode standby operation:
In a switch mode power supply, a first switching transistor is coupled to a primary winding of a transformer for generating pulses of a switching current. A secondary winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a control signal in the capacitor. The control signal is applied to a mains coupled chopper second transistor for generating and regulating supply voltages in accordance with pulse width modulation of the control signal. During standby operation, the first and second transistors operate in a burst mode that is repetitive at a frequency of the AC mains supply voltage such as 50 Hz. In the burst mode operation, during intervals in which pulses of the switching current occur, the pulse width and peak amplitude of the switching current pulses progressively increase in accordance with the waveform of the mains supply voltage to provide a soft start operation in the standby mode of operation within each burst group.
The invention relates to switch-mode power supplies.
In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of a flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce DC output supply voltages such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver and a voltage that energizes a remote control unit.
During normal operation, the DC output supply voltages are regulated by the pulse width modulator in a negative feedback manner. During standby operation, the SMPS is required to generate the DC output supply voltage that energizes the remote control unit. However, most other stages of the television receiver are inoperative and do not draw supply currents. Consequently, the average value of the duty cycle of the chopper transistor may have to be substantially lower during standby than during normal operation.
Because of, for example, storage time limitation in the chopper transistor, it may not be possible to reduce the length of the conduction interval in a given cycle below a minimum level. Thus, in order to maintain the average value of the duty cycle low, it may be desirable to operate the chopper transistor in an intermittent or burst mode, during standby. During standby, a long dead time interval occurs between consecutively occurring burst mode operation intervals. Only during the burst mode operation interval switching operation occurs in the chopper transistor. The result is that each of the conduction intervals is of a sufficient length.
In accordance with an aspect of the invention, burst mode operation intervals are initiated and occur at a rate that is determined by a repetitive signal at the frequency of the AC mains supply voltage. For example, when the mains supply voltage is at 50 Hz, each burst mode operation interval, when switching cycles occur, may last 5 milliseconds and the dead time interval when no switching cycles occur, may last during the remainder portion or 15 milliseconds. Such arrangement that is triggered by a signal at the frequency of the mains supply voltage simplifies the design of the SMPS.
The burst mode operation intervals that occur in standby operation are synchronized to the 50 Hz signal. During each such interval, pulses of current are produced in transformers and inductances of the SMPS. The pulses of current occur in clusters that are repetitive at 50 Hz. The pulses of current occur at a frequency that is equal to the switching frequency of the chopper transistor within each burst mode operation interval. Such qurrent pulses might produce an objectionable sound during power-off or standby operation. The objectionable sound might be produced due to possible parasitic mechanical vibrations as a result of the pulse currents in, for example, the inductances and transformers of the SMPS.
In accordance with another aspect of the invention, the change in the AC mains supply voltage during each period causes the length of the conduction interval in consecutively occurring switching cycle during the burst mode operation interval to increase progressively. Such operation that occurs during each burst mode operation interval may be referred to as soft start operation. The soft start operation causes, for example, gradual charging of capacitors in the SMPS. Consequently, the parasitic mechanical vibrations are substantially reduced. Also, the frequency of the switching cycles within each burst mode operation interval is maintained above the audible range for further reducing the level of such audible noise during standby operation.
A switch mode power supply, embodying an aspect of the invention, for generating an output supply voltage during both a standby-mode of operation and during a run-mode of operation includes a source of AC mains input supply voltage. A control signal at a given frequency is generated. A switching arrangement energized by the input supply voltage and responsive to the first control signal produces a switching current during both the standby-mode of operation and the run-mode operation. The output supply voltage is generated from the switching current. An arrangement coupled to the switching arrangement and responsive to a standby-mode/run-mode control signal and to a signal at a frequency that is determined by a frequency of the AC mains input supply voltage controls the switching arrangement in a burst mode manner during the standby-mode of operation. During a burst interval, a plurality of switching cycles are performed and during an alternating dead time interval no switching cycles are performed. The two intervals alternate at a frequency that is determined by the frequency of the AC mains input supply voltage.
SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) TEA2028 COLOR TV SCANNING AND POWER SUPPLY PROCESSOR
the TEA2028 combines 3
major functionsof a TV set as follows :
- Horizontal (line) and vertical (frame) time base
generation for spot deviation. The video signal is
used for the synchronization of both time bases.
- On-chip switching power supply controller synchronized
on line frequency.
This integrated circuit has been implemented in
bipolar I2L technology, and various functions are
digitally processed. In fact, resorting to logic functions
has the advantage of working with pure and
accurate signals while full benefit is drawn from
high integration of logic gates (approx. 110 gates
The main objective is to drive all functions using an
accurate time base generated by a master 500kHz
Also, horizontal and vertical time bases, are obtained
by binary division of reference frequency.
This has the advantage of eliminating the 2 adjustments
which were necessary in former devices.
One section of this integrated circuit is designed to
drive a switching power supply of recent implementation
called ”master-slave”. Switching takes place
on the primary side (i.e., directly on mains) of a
transformer. The device ensures SMPS Control,
Start-up and Protection functions.Control signals
go through a small pulse transformer thereby providing
full isolation from mains supply.
This new approach fully eliminates the bulky mains
transformersused in the past. In addition, it offers
optimized power consumption and reduction of TV
- MAIN FUNCTIONS
- Detection and extraction of line and frame synchronization
pulses from the composite video
- Horizontal scanning control and synchronization
by two phase-locked loop devices.
- Video identification.
- 50 or 60Hz standardrecognition for vertical scanning.
- Generation of a self-synchronized frame sawtooth
for 50/60Hz standards.
- Line time constant switching for VCR operation
through an input labeled ”VCR” (Video Cassette
- Control and regulation of a primary-connected
switching power supply by on-chip controller device
• an error amplifier
• a pulse width modulator synchronized on line
• a start-up and protection system
- Overall TV set protection input
- Frame blanking and super sandcastle output signals
- Frame blanking safety input for CRT protection in
case of vertical stage failure.
Internal Voltage and Current References
V.1.1 - 1.26V Voltage reference
For optimum operation of the device, an accurate
and temperature-stable voltage generator independent
from VCC variations is used (Band-gap
The generated 1.26V is particularly used as reference
setting on input comparators.
Line Sync. Extraction
Horizontal and vertical time bases should be synchronized
with corresponding sync. pulses transmitted
inside the infra-black portion of video signal.
The duty of this stage is to extract these sync
pulses. The output signal, called composite sync,
contains the vertical sync which is transmitted by
simple inversion of line sync. pulses.
The vertical sync pulse is then extracted from this
The main advantage of this arrangement is its
ability to operate at video input signal levels falling
within 0.2V to 3V peak-to-peak range and at any
The operating principle is to lock the black level of
the input signal (Pin 27) onto internaly fixed voltage
(VN) and then memorize the average voltage of the
sync pulse by using an integrating capacitor connected
to Pin 26.
Finally, the composite sync signal is delivered by a
comparator the inputs of which are driven by V50%
and video signals.
The video signal is applied to Pin 27 through the
coupling capacitor ”C27”. Since the sync pulse
amplitudeisgenerallyequal to 1/3 ofVPP (i.e.66mV
to 1V) and in order to obtaina good precision of the
black level, the sync pulse should be amplified by
a coefficient of - 14 before being applied to the
This comparator will charge the ”C27” capacitoras
long as VS1 >VN V VS1 will stabilize at VN during the
line flyback interval ”Tr” if the average charge of
”C27” capacitor is nil for one TH period.
IC/ID is calculated such that the locking occurs at
the middle of the back porch.
- Memorizing the sync pulse 50% value
The objective is to memorize the voltage corresponding
to 50% of theline sync pulseVS1 byusing
an external capacitor connected to Pin 26 (see
The overall arrangement comprises two comparators.
- Comparator C2 : delivers an output voltage ”V1”
by comparingVS1 +VD, V26 and the voltage drop
across two resistors.
- ComparatorC3 : which delivers a constant output
current thereby maintaining on capacitor ”C26”,
the voltage V50% corresponding to 50% of peak
to peak sync pulse.
Sync pulse detection
This function is fulfilled by comparing the inverted
video signal (VS1 + VD) whose black level is constant
at 2V, with the sync 50% voltage level on
Pin 26 (see Figure 10).
Comparator C4 will deliver the line sync pulse (LS)
which will be used for 3 functions :
- Horizontal scanning frequency locking : output to
j1 phase comparator.
- Frame sync extraction for vertical scanning synchronization.
- Detecting the presence of a video signal at circuit
The LS signal in two latter functions is filtered for
noise by using combination of current generator I
and a zener diode equivalent to a capacitor.
Using this extraction technique at a very noisy
video signal yields remarkable display stability.
First Phase Locked-loop Stage ”j1”
This stage is commonly called the first Phase
Its duty is to lock the frequency and the phase of
the horizontal time base with respect to the line
In the absence of transmission (i.e. lack of line
sync), the horizontal scanning frequency is obtained
by dividing the output frequency of a VCO
device. This VCO oscillates at approximately
500kHz and uses a low frequency drift ceramic
resonator.This method eliminates the need of horizontal
VCO centered on 500kHz
This is a voltage-controlled oscillator which generates
an output frequency proportional to the voltage
applied to its input.
This voltage is delivered by low-pass filter.
VCO (Voltage Controlled Oscillator)
Its function is to generatea frequency proportional
to a control voltage issued externally, by the lowpass
filter in our case.
The period of the output signal is used as timing
reference for various functions such as, horizontal
and vertical time bases. The frequency range must
be short and accurate :
- It must be short since the power dissipated within
the horizontal scanning block is inversely proportional
to the line frequency.
- The accuracy is required if the adjustment is to
The basic arrangement is to employ a ceramic
resonator (or ceramic filter) which has quite stable
characteristics as a function of frequency.
A filter whose resonating frequency is a multiple of
line frequency (15625Hz) is to be selected. An
example is 32 V 15625 = 500kHz.
Video identification stage
This stage will detect the coincidence between the
line sync pulse (if present) and a 2ms pulse issued
from the logic block. This 2ms pulse at line frequency
is positionned at the center of line sync
pulse when the first loop ”j1” is locked.
This sampled detection is stored by an external
capacitor connected to Pin 25. The video recognition
status is also available on Pin 24 so as to
enable Sound Muting during station search process
and the inhibition of Automatic FrequencyTuning.
- Line deflection stage
- Generates the saw-tooth current for line yoke
- Generates the high voltage required by picture
tube and other supply voltages
The line flyback information is provided by the
Line deflection stage
This chapter will cover a general description of the
”horizontal deflection stage” employed almost
commonly in all recent TV sets.
Deflection of electron beam is proportional to the
intensity of magnetic field induced by the line yoke.
This yoke is equivalent to an inductor. The deflection
is therefore proportional to the current through
In order to obtain a linear deflection from left to right
as a function of time, a saw-tooth current must be
generated within the yoke.The approachis toapply
a switched DC voltage to the line yoke.
Vertical deflection driver stage
This stage must constantly drive the vertical spot
deflection.Such deflectionwill horizontallyscan the
screen from top to bottom thus generating the
displayed image. Similar to horizontal deflection,
the vertical deflection is obtained by magnetic field
variations of a coil mounted on the picture tube.
A saw-tooth current at frame frequency will go
through this coil commonly called ”frame yoke”.
Frame period is the time required for the entire
screen to be scanned vertically.
50Hz and 60Hz Frame Scanning Frequencies.
Also, a full screen display is obtained by two
successivevertical scanningssuch that the second
scanning is delayed by a half line period with
respect to the first.
This method increases the number of images per
second (50 half images/s or 50 frames/s in 50Hz
standard). This scanning mode called ”Interlaced
Scanning” eliminates the fliker which would have
been otherwise produced by scanning 25 entire
images per second.
The circuit will generate a saw-tooth voltage which
is linear as a function of time and called ”frame
saw-tooth”. A power amplifier will deliver to the
”frame yoke” a current proportional to this sawtooth
voltage. It is thus clear that this saw-tooth
voltage reflects the function of the vertical spot
deflection; which must itself be synchronized with
the video signal. Synchronization signals are obtained
from an extraction stage which will extract
the useful signal during line pulse inversion of the
composite sync signal.
Synchronization occurs at the end of scanning, in
other words, when the saw-tooth voltage at Pin 5
is reset. This function is accomplished by the
”frame logic circuitry” of full digital implementation.
This processing method offers various advantages
- Accurate free-running scanning frequency
eliminates the frequencyadjustment required by
- Digital synchronization locked onto half line
frequency thereby yielding perfect interlaced display
andexcellent stabilitywith noisy videosignal.
- Automatic 50/60Hz standard recognition and
switching the corresponding display amplitude.
- Optimized synchronization in VCR mode.
- Generationof variousaccurate time intervals,
such as narrow ”sync windows” thus reducing
considerably the vertical image instability in case
of for instance,mainsinterference,superimposed
on frame sync pulse.
- Generation of vertical blanking signal for spot
flyback and to protect the picture tube in case
of scanning failure.
Vertical synchronization window -
In the absence of sync pulse various free-running
periods are specified. Since vertical scanningmust
be always active, these free-running periods must
be higher than those of 50 and 60Hz standards so
as to ensure synchronization.
An other window, allowing synchronization only at
the end of scanning, is also necessary. Upon synchronization,
this window will allow vertical flyback
only at the bottom of screen. This window should
be narrow for good noise immunity but also wide
enough to yield, upon synchronization, a capture
time unperceptible on screen.
In our case, as long as no standard identification
takes place the window will remain wide, and once
one of the standards has been identified, the window
will be considerably reduced.
InVCRmode, thiswindow will bealways wide since
frame frequenciesdelivered in high-speed search,
slow review and picture pause modes are very
much variable and must be taken into consideration.
In the absenceof transmission (Mute = 0), synchronization
is disabled (so as to avoid incorrect synchronization
due to noise) and the free-running
frequency is around 50Hz. This will eliminate the
occurrence of picture overlay at the end of trace at
a lower free-running frequency.
- Frame blanking safety (TEA2028 only,
for TEA2029 refer to section VII.5)
Its duty is to protect the phosphorcoating of picture
tube in case of any problem with vertical deflection
function such as scanning failure.
Asignal to monitor correct scanning is provided by
the frame yoke and applied to Pin 2.
In case of any failure, all frame blanking outputsare
disabled and go high thereby blanking the entire
During trace phase, the voltage across frame yoke
has a parabolicalshape due to the couplingcapacitor
in series with yoke. During frame flyback, the
current through frame yoke must be rapidly inverted.
Conventionally, a two-fold higher supply
voltage is applied across the yoke. This will produce
an overvoltage called ”flyback”.
The safety monitoring status is detected on the
falling-edge of flyback, i.e. at the beginning of
scanning. A differentiator network is used to transmit
only fast voltage variations.
Therequiredpulse is then compared to 1.26Vlevel.
Frame blanking goes high in the absence of negative
pulse (zero deflection current) or if the pulse
does not fall within the first 21 lines (exagerated
SWITCHING POWER SUPPLY DRIVER STAGE
Switching takes place on the primary side (mains
side) of a transformer by using TEA2164 SMPS
Controller manufactured by SGS-THOMSON.
Required voltage values are obtained by rectifying
different voltage outputs delivered through secondary
windings. The horizontal deflection stage is
powered by one of these outputs delivering around
This voltage source must be regulated since any
voltage fluctuation will yield variations of the horizontal
The TE2028 monitors this voltage and transmits
the regulation signal to the primary controller circuitry
via a small pulse transformer. The characteristics
of this regulation signal are directly related
to the conduction period of switching transistor.
General operating principles
A fraction of the 135V output voltage to be regulated
is compared to the 1.26V reference voltage.
Resulting error signal is amplified and then applied
to phase modulator ”M1”, which will deliver a
square waveform at line frequency whose duty
cycle depends on the value of input voltage ”V9”.
A second phase modulator ”M2” will determine the
conduction period as a function of voltage on
Pin 15. This function is mandatory for system startup.
A 28ms window is used to limit the conduction
period of the primary-connected transistor.
Supply output (Pin 7) and line output (Pin 10) will
be disabled if any information indicating abnormal
operation is applied to safety input (Pin 28). Consequently,
all power stages are disabled and the
TV set is thus protected.
For discontinous mode ”flyback” configuration
The primary-connected transistor is turned-off during
the line flyback.
All interference signals due to switching and susceptible
to affect the video signal will not therefore
be visible on screen.
Power supply soft-start
When theTVset is initially turned on,control pulses
are not yet available and consequently the controller
block on primary side will impose a low-power
transfer to the secondary winding. This power is
produced by an intermittent switching mode called
As soon as the VCC supply to TEA2028Bexceeds
6V level, line andSMPSoutputsareenabled.Since
the filtering capactitors on secondary side cannot
charge up instantaneously,the voltage to be regulated
would not yet be at its nominal value.Without
conduction period limitation upon start-up, the device
will set a maximum cycle of 28ms which will
result in a high current flow through the primary
winding and thus through the switching transistor
which will in turn activate the protection function
implemented on primary side.
Consequently, the primary controller block will be
inhibited and the set will not turn-on.
A start-up system has been implemented within
TEA2028B to overcome this problem.
This soft start system, will upon initial start-up, use
the image of the falling voltage on Pin 15 to increase
progressively the conduction cycle. The
phase modulator ”M2” compares this voltage with
line saw-tooth voltage and delivers the corresponding
During supply voltage rising cycle [VCC (Pin 8)
< 6V], the capacitor Pin 15 will charge up rapidly
while the voltage across it follows VCC.
At VCC . 6V, the capacitor is discharged via an
internal current generatorand the voltage across it
At V15 3 3.5V (line saw-tooth peak-to-peak voltage),
phase comparator ”M2” delivers a low conduction
period which will gradually increase.
The conduction period (Pin 7) will rise until the
secondary voltage reaches the value set by potentiometer
”P”. When this occurs, the loop is activated.
The Pin 15 discharge current value is 100mA for a
duration of 2ms line frequency.
- Protection features
As soon asa safety signal (V 3 1.26V) is applied to
Pin 28, line and supply outputs (Pins 10 and 7) are
both disabled. Capacitor ”C15” begins charging up
until the voltage across it reaches 4V (K V VCC).
Outputs are again enabled and conduction period
gradually increases as it occurs upon initial startup.
The device will be definitively inhibited if the cycle
of events is repeated 3 times.
For the device to restart, the internal 3-bit register
should be reset which requiresthe VCC to fall below
4V (see Figure 68).
Pin 15 charging current : IC(AV) = - ID(AV) = - 3.1mA
TV Power supply in standby mode
V.7.6.1 - Regulationby primary controller circuit
This mode of regulation called ”Burst Mode” is
performedonly by the primary controller circuit and
is activated in the case of missing control pulses or
in the absence of power supply to TEA2028B.
In this mode, power available through secondary
winding is limited. Refer to TEA2164 Application
Note for further details.
Higher powers can be obtained by using the regulation
feature offered by TEA2028B. In this case,
the horizontal output (Pin 10) must be disabled.
V.7.6.2 - Regulation by TEA2028
In this case, all that is required is to disable the line
scanning function thus reducing the overall power
The device power supply regulation loop remains
active, for minimum conduction period to be 1.5ms
the power delivered through secondary must be
higher than 3W.
Line Output Inhibition
Two alternativesare possible :
- Grounding flip-flop Pin 1
- Apply a voltage higher than 3V to Pin 12.
Super sandcastle signal generator
This signal used in video stage, is available on
It has 3 levels at specified time intervals :
- 2.5V level
Used for vertical blanking at each frame flyback.
Its duration is 21 lines and is generated by the
This level will be maintained if vertical scanning
failure is detected on Pin 2.
- 4.5V level
Used for horizontal blanking, its duration is determined
by comparing the line flyback signal on
Pin 12 to an internal voltage of 0.25V.
- 10V level
This signal is used by color decoding stage. Its
duration of 4ms is determined by line logic circuitry.
With respect to the video signal on Pin 27,
this level is positioned such that it is used to
sample the burst frequency transmitted just after
the sync pulse.
TDA4555 Multistandard decoder.
The TDA4555 and TDA4556 are monolithic integrated
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
· Gain controlled chrominance amplifier for PAL, SECAM
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· De-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
· Two identification circuits for PAL/SECAM (H/2) and
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch.
PHILIPS TDA4565 Colour transient improvement
The TDA4565 is a monolithic integrated circuit for colour transient improvement (CTI) and luminance delay line in gyrator
technique in colour television receivers.
· Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and
switching stages resulting in high transients of colour difference output signals
· A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line
· Switchable delay time from 730 ns to 1000 ns in steps of 90 ns and additional fine adjustment of 50 ns
· Two Y output signals; one of 180 ns less delay.
PHILIPS TDA2556 QUASI-SPLIT-SOUND CIRCUIT WITH DUAL SOUND DEMODULATORS
The TDA2556 is a monolithic integrated circuit for quasi-split-sound processing, including two FM
demodulators, for two carrier stereo TV receivers and VTR.
First IF (vision carrier plus sound carrier).
0 3 stage gain controlled IF amplifier
0 AGC circuit
0 Reference amplifier and limiter amplifier for vision carrier (V.C.) processing
0 Linear multiplier for quadrature demodulation
Second IF (two separate channels for both FM sound signals).
0 4-stage-limiting amplifier
0 Ouadrature demodulator
0 AF amplifier with de-emphasis
O Output buffer
0 Muting for one or both AF outputs
TEA2164 /2165 SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT
.POSITIVE AND NEGATIVE OUTPUT CURRENT
UP TO 1.2AAND – 1.7A .A TWO LEVEL COLLECTOR CURRENT LIMITATION
.COMPLETE TURN OFF AFTER LONG DURATION
OVERLOADS .UNDER AND OVER VOLTAGELOCK-OUT .SOFT START BY PROGRESSIVE CURRENT
LIMITATION .DOUBLE PULSE SUPPRESSION .BURST MODE OPERATION UNDER STANDBY
In amaster slave architecture, the TEA2164control
IC achieves the slave function. Primarily designed
for TV receivers and monitors applications, this
circuit provides an easy synchronizationand smart
solution for low power stand by operation.
Located at the primary side the TEA2164 Control
IC ensures :
- the power supply start-up
- the power supply control under stand-by conditions
- the process of the regulation signals sent by the
master circuit located at the secondary side
- directbasedrive of the bipolarswitching transistor
- the protection of the transistor and the power
supply under abnormal conditions.
II. GENERAL DESCRIPTION
In a master slave architecture, the TEA2164 Control
IC, located at the primary side of an off line
power supply achievesthe slave function ;whereas
the master circuit is located at the secondary side.
The link between both circuits is realized by a small
In the operation of the master-slave architecture,
four majors cases must be considered :
- normal operating
- power supply start-up
- abnormal conditions : off load, short circuit, ...
II.1. Normal Operating (master slave mode)
In this configuration, the master circuit generatesa
pulse widthmodulatedsignal issued from themonitoring
of the output voltage which needs the best
accuracy (in TV applications : the horizontal deflection
stagesupplyvoltage).Themaster circuit power
supply can be supplied by another output.
The PWM signal are sent towards the primary side
through small differentiating transformer. For the
TEA2164 positive pulses are transistor switchingon
commands ; and negative pulses are transistor
switching-offcommands (Figure 4). In this configuration,
only by synchronizing the master oscillator,
the switching transistor may be synchronized with
an external signal.
II.2. Stand-by Mode
In this configuration the master circuit no longer
sends PWM signals, the structure is not synchronized
; and the TEA2164 operates in burst mode.
The average power consumption at the secondary
side may be very low 1W 3 P 3 6W (as it is
consumed in TV set during stand by).
By action on the maximum duty cycle control, a
primary loop maintains a semi-regulation of the
output voltages.Voltage on feed-back is applied on
Burst period is externally programmedby capacitor
II.3. Power Supply Start-up
After the mains have been switched-on, the VCC
storage capacitor of the TEA2164 is charged
through a high value resistor connected to the
rectified high voltage.When Vcc reaches VCC start
threshold (9V typ), the TEA2164 starts operatingin
burst mode. Since available output power is low in
burst mode the output power consumption must
remain low before complete setting-up of output
voltage. In TV application it can be achieved by
maintaining the TV in stand-by mode during startup.
When VCC exceeds VCC max, an internal flip-flop
stops output conduction signals. The circuit will
start again after the capacitor C1 discharge ; it
means : after loss of synchronization or after Vcc
stop crossing (Figure 7).
In flyback converters, this function protects the
power supply against output voltage runaway.
SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) TDA8442 I2C-bus interface for colour decoders
The TDA8442 provides control of four analogue functions
and has one high-current and two switching outputs.
Control of the IC is performed via the two-line, bidirectional
· Four analogue control outputs
· One high-current output port (npn open emitter)
· Two switching output ports (npn collector with internal
· I2C-bus slave receiver
· Power-down reset.
SONY KV-M2511A (AE-1) CHASSIS AE-1 (SCC-B16P-A) SONY DST EHT FBT TRANSFORMER Bobbin structure for high voltage transformers EHT Output.A coil bobbin for a fly-back transformer or the like having a bobbin proper. A plurality of partition members or flanges are formed on the bobbin proper with a slot between adjacent ones. At least first and second coil units are formed in the bobbin proper, each having several slots, formed between the flanges, and first and second high voltage coils are wound on the first and second coil units in opposite directions, respectively. A rectifying means is connected in series to the first and second coil units, and a cut-off portion or recess is provided on each of the partition members. In this case, a wire lead of the coil units passes from one slot to an adjacent slot through the cut-off portion which is formed as a delta groove, and one side of the delta groove is corresponded to the tangent direction to the winding direction.
1. A fly-back transformer comprising a coil bobbin comprising a plurality of parallel spaced discs with a first adjacent plurality of said disc formed with delta shaped slots having first edges which extend tangentially to a first winding direction and a first winding wound on said first adjacent plurality of said discs in said first winding direction, a second adjacent plurality of said discs formed with delta shaped slots having first edges which extend tangentially to a second winding direction opposite said first winding direction and a second winding wound on said second adjacent plurality of said discs in said second winding direction, a third adjacent plurality of said discs formed with delta shaped slots having first edges which extend tangentially to said first winding direction and a third winding wound on said third adjacent plurality of said discs in said first winding direction and said second plurality of adjacent discs mounted between said first and third plurality of adjacent discs. 2. A fly-back transformer according to claim 1 wherein adjacent ones of said first adjacent plurality of discs are mounted such that their delta shaped slots are orientated 180 degrees relative to each other. 3. A fly-back transformer according to claim 2 including a first winding turning partition mounted between said first and second adjacent plurality of discs and formed with grooves and notches for changing winding direction between said first and second windings and a second winding turning partition mounted between said second and third adjacent plurality of discs and formed with grooves and notches for changing the winding direction between said second and third windings. 4. A fly-back transformer according to claim 3 wherein said first and second winding turning partitions are formed with winding guiding slots for guiding the winding between the first, second and third adjacent plurality of discs. 5. A fly-back transformer according to claim 2 including a first rectifying means connected between one end of said first winding and one end of said second winding, and a second rectifying means connected between the second end of said second winding and one end of said third winding. 6. A fly-back transformer according to claim 5 wherein the second end of said first winding is grounded and a third rectifying means connected between the second end of said third winding and an output terminal.
1. Field of the Invention
The present invention relates generally to a bobbin structure for high voltage transformers, and is directed more particularly to a bobbin structure for high voltage transformer suitable for automatically winding coils thereon.
2. Description of the Prior Art
In the art, when a wire lead is reversely wound on a bobbin separately at every winding block, a boss is provided at every winding block and the wire lead is wound on one block, then one end of the wire lead is tied to the boss where it will be cut off. The end of the wire lead is tied to another boss, and then the wire lead is wound in the opposite direction. Therefore, the prior art winding method requires complicated procedures and the winding of the wire lead cannot be rapidly done and also the winding can not be performed automatically. Further, the goods made by the prior art method are rather unsatisfactory and have a low yield.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly an object of the invention is to provide a coil bobbin for a fly-back transformer or the like by which a wire lead can be automatically wound on winding blocks of the coil bobbin even though the winding direction is different among the different winding blocks.
Another object of the invention is to provide a coil bobbin for a fly-back transformer or the like in which a bridge member and an inverse engaging device for transferring a wire lead from one wiring block to an adjacent wiring block of the coil bobbin and wiring the wire lead in opposite wiring directions between adjacent wiring blocks, and a guide member for positively guiding the wire lead are provided.
The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like reference numerals and letters designate the same elements and parts, respectively.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram showing the construction of a fly-back transformer;
FIG. 2 is a connection diagram showing an example of the electrical connection of the fly-back transformer shown in FIG. 1;
FIG. 3 is a schematic diagram showing an example of a device for automatically winding a wire lead of the fly-back transformer on its bobbin;
FIG. 4 is a perspective view showing an example of the coil bobbin according to the present invention;
FIG. 5 is a plan view of FIG. 4;
FIGS. 6 and 7 are views used for explaining recesses or cut-off portions shown in FIGS. 4 and 5; and FIGS. 8A and 8B cross-sectional views showing an example of the inverse engaging means according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
When the high voltage winding of a fly-back transformer used in a high voltage generating circuit of a television receiver is divided into plural ones and then wound on a bobbin, the divided windings (divided coils) are connected in series through a plurality of rectifying diodes.
When the winding is divided into, for example, three portions, such as divided coils La, Lb and Lc, they are wound on a bobbin proper 1 from, for example, left to right sequentially in this order as shown in FIG. 1. In this case, if the divided coils La and Lc are selected to have the same sense of turn and the middle coil Lb is selected to have the opposite sense of turn from the coils La and Lc, the distance between the terminal end of coil La and the start of coil Lb and the distance between the terminal end of coil Lb and the start of coil Lc can be got relatively long. Therefore, diodes Da and Db can be mounted by utilizing the space above the block on which the middle coil Lb is wound as shown in FIG. 1, so that it becomes useless to provide spaces for diodes between the divided coils La and Lb and between the divided coils Lb and Lc and hence the bobbin proper 1 can be made compact.
FIG. 2 is a connection diagram showing the connection of the above fly-back transformer. In FIG. 2, reference numeral 2 designates a primary winding (Primary coil) of the fly-back transformer, reference letter L designates its high voltage winding (secondary coil), including divided coils La, Lb and Lc, 3 an output terminal, and 4 a lead wire connected to the anode terminal of a cathode ray tube (not shown), respectively.
An example of the bobbin structure according to the invention, which is suitable to automatically wind coils, which are different in sense of turn in each winding block as shown in FIG. 1, on the bobbin, will be hereinafter described with reference to the drawings.
FIG. 3 is a diagram showing an automatic winding apparatus of a wire lead on a coil bobbin. If it is assumed that the wire lead is wound in the order of winding blocks A, B and C in FIG. 1 and the wire lead is wound on the block A with the bobbin proper 1 being rotated in the counter-clockwise direction as shown in FIG. 3, the relation between the bobbin proper 1 and the wire lead becomes as shown in FIG. 3. In this figure, reference numeral 6 designates a bobbin for feeding the wire lead.
Turning to FIG. 4, an example 10 of the bobbin structure or coil bobbin according to the present invention will be described now. In this example, the winding blocks A, B and C for the divided coils La, Lb and Lc are respectively divided into plural slots or sections by plural partition members or flanges 11, and a cut-off portion or recess 12 is formed on each of the flanges 11 through which the wire lead in one section is transferred to the following winding section.
As shown in FIG. 6, each recess 12 is so formed that its one side extends in the direction substantially coincident with the tangent to the circle of the bobbin proper 1 and its direction is selected in response to the sense of turn of the winding or wire lead. In this case, the direction of recess 12 means the direction of the opening of recess 12, and the direction of recess 12 is selected opposite to the sense of turn of the winding in the present invention.
Now, recesses 12A, which are formed in the winding block A, will be now described by way of example. The positions of recesses 12A formed on an even flange 11Ae and an odd flange 11A 0 are different, for example, about 180° as shown in FIGS. 6A and 6B. Since the bobbin proper 1 is rotated in the counter-clockwise direction in the winding block A and hence the sense of turn of the wire lead is in the clockwise direction, the recess 12A is formed on the even flange 11Ae at the position shown in FIG. 6A. That is, the direction of recess 12A is inclined with respect to the rotating direction of bobbin proper 1 as shown in FIG. 6A. In this case, one side 13a of recess 12A is coincident with the tangent to the circle of bobbin proper 1, while the other side 13b of recess 12A is selected to have an oblique angle with respect to the side 13a so that the recess 12A has a predetermined opening angle.
The opening angle of recess 12A is important but the angle between the side 13a of recess 12A and the tangent to the circle of bobbin proper 1 is also important in the invention. When the wire lead is bridged or transferred from one section to the following section through the recess 12A, the wire lead in one section advances to the following section in contact with the side 13a of recess 12A since the bobbin proper 1 is rotated. In the invention, if the side 13a of recess 12A is selected to be extended in the direction coincident with the tangent to the circle of bobbin proper 1, the wire lead can smoothly advance from one section to the next section without being bent.
In the invention, since the middle divided coil Lb is wound opposite to the divided coil La, a recess 12B provided on each of flanges 11B of the winding block B is formed to have an opening opposite to that of recess 12A formed in the winding block A as shown in FIGS. 6C and 6D.
As shown in FIG. 5, terminal attaching recesses 14 are provided between the winding blocks A and B to which diodes are attached respectively. In the illustrated example of FIG. 5, a flange 15AB is formed between the flanges 11A 0 and 11B 0 of winding blocks A and B, and the recesses 14 are formed between the flanges 11A 0 and 15AB and between 15AB and 11B 0 at predetermined positions. Then, terminal plates 16, shown in FIG. 4, are inserted into the recesses 14 and then fixed there to, respectively. The terminal plates 16 are not shown in FIG. 5. Between the winding blocks B and C and between the blocks A and B, similar terminal attaching recesses 14 are formed, and terminal plates 16 are also inserted thereinto and then fixed thereto.
As described above, since the divided coil Lb is wound opposite to the divided coils La and Lc, it is necessary that the winding direction of the wire lead be changed when the wire lead goes from the block A to block B and also from the block B to block C, respectively.
Turning to FIG. 7, an example of the winding or wire lead guide means according to the present invention will be now described. In FIG. 7, there are mainly shown a bridge member for the wire lead and an inverse member or means for the wire lead which are provided between the winding blocks A and B. At first, a bridge means 20 and its guide means 21, which form the bridge member, will be described. The bridge means 20 is provided by forming a cut-out portion or recess in the middle flange 15AB located between the winding blocks A and B. In close relation to the bridge means or recess 20, the guide means 21 is provided on a bridge section X A at the side of block A. This guide means 21 is formed as a guide piece which connects an edge portion 20a of recess 20 at the winding direction side to the flange 11A 0 of block A in the oblique direction along the winding direction through the section X A .
Next, an inverse engaging means 22 will be now described with reference to FIGS. 7 and 8. If the flange 11B 0 of FIG. 7 is viewed from the right side, the inverse engaging means 22 can be shown in FIG. 8A. In this case, the tip end of one side 13a of recess 12B 1 is formed as a projection which is extended outwards somewhat beyond the outer diameter of flange 11B 0 . The inverse engaging means 22 may take any configuration but it is necessary that when the rotating direction of the bobbin proper 1 is changed to the clockwise direction, the wire lead can be engaged with the recess 12B 1 or projection of one side 13a and then suitably transferred to the next station.
Another guide means 23 is provided on a bridge section X B at the side of winding block B in close relation to the inverse engaging means 22. The guide means 23 is formed as a guide surface which is a projected surface from the bottom surface of section X B and extended obliquely in the winding direction. This guide means or guide surface 23 is inclinded low into the means 22 and has an edge 23a which is continuously formed between the middle flange 15AB and the flange 11B 0 .
In this case, it is possible that the guide means 21 and guide surface 23 are formed to be the same in construction. That is, both the guide means 21 and 23 can be made of either the guide piece, which crosses the winding section or guide surface projected upwards from the bottom surface of the winding section. It is sufficient if the guide means 21 and 23 are formed to smoothly transfer the wire lead from one section to the next section under the bobbin proper 1 being rotated.
Although not shown, in connection with the middle flange 15BC between the winding blocks B and C, there are provided similar bridge means 20, guide means 21, inverse engaging means 22 and another guide means 23, respectively. In this case, since the winding direction of the wire lead is reversed, the forming directions of the means are reverse but their construction is substantially the same as that of the former means. Therefore, their detailed description will be omitted.
According to the bobbin structure of the invention with the construction set forth above, the wire lead, which is transferred from the block A to the section X A by the rotation of bobbin proper 1, is wound on the section X B from the section X A after being guided by the guide piece 21 to the recess 20 provided on the middle flange 15AB, and then transferred to the recess 22 provided on the flange 11B 0 guide surface 23, bridged once to the first section of winding block B through the recess 22 (refer to dotted lines b in FIG. 7). Then, if the rotating direction of the bobbin proper 1 is reversed, the wire lead is engaged with the bottom of recess 22 (refer to solid lines b in FIG. 7). Thus, if the above reverse rotation of bobbin proper 1 is maintained, the wire lead is wound on the block B in the direction reverse to that of block A. When the wire lead is transferred from the block B to block C, the same effect as that above is achieved. Therefore, according to the present invention, the wire lead can be automatically and continuously wound on the bobbin proper 1.
After the single wire lead is continuously wound on blocks A, B and C of bobbin proper 1 as set forth above, the wire lead is cut at the substantially center of each of its bridging portions. Then, the cut ends of the wire lead are connected through diodes Da, Db and Dc at the terminal plates 16, respectively by solder.
In the present invention, the projection piece, which has the diameter greater than that of the flange 11B, is provided in the bridge recess 12 to form the inverse engaging means 22 as described above, so that when the winding direction is changed, the wire lead engages with the inverse engaging means 22 without errors when reversing the winding direction of the wire lead.
If the diameter of the projection piece of means 22 is selected, for example, to be the same as that of the flange 11B, it will not be certain that the wire lead engages with the means 22 because it depends upon the extra length of the wire lead and hence errors in winding cannot be positively avoided.
Further, in this invention, the bridge means is provided on the flange positioned at the bridging portion of the bobbin which has a number of dividing blocks separated by flanges, and the inverse engaging means is provided and also the guide means is provided at the former winding section to cooperate with the inverse engaging means. Therefore, the wire lead can be positively fed to the bridge means, and the transfer of the wire lead to the following winding section can be carried out smoothly.
Further, in this invention since one side of the recess 12 is selected coincident with the tangent of the outer circle of the bobbin proper 1 and also with the winding direction, the wire lead can be smoothly bridged to the following section. Due to the fact that the direction of recess 12 is changed in response to the winding direction, even if there is a block on which the wire lead is wound in the opposite direction to that of the other block, the wire lead can be continuously and automatically wound through the respective blocks.
The above description is given for the case where the present invention is applied to the coil bobbin for the high voltage winding of a fly-back transformer, but it will be clear that the present invention can be applied to other coil bobbins which require divided windings thereon with the same effects.
It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the present invention, so that the spirits or scope of the invention should be determined by the appended claims only.
SONY KV-X25TA CHASSIS AE1 (SCC-B16-EA) Television receiver which can indicate the numeral of a channel SONY On Screen Display TECHNOLOGY.
A television receiver having a CPU (central processing unit), a ROM (read only memory) in which a program and a font data are written, and a RAM (random access memory) for work area and a shift register. The font data to be indicated as a channel numeral is loaded to the shift register by an interrupt procedure and the output from the shift register is supplied to the video signal system whereby to indicate the channel numeral after the channel is changed.
1. A television receiver for receiving a video signal that includes a synchronizing signal, said receiver comprising:
a central processing unit having an interrupt function;
bus means connected to said central processing unit;
read only memory means connected to said central processing unit through said bus means and containing a control program to be executed by said central processing unit;
random access memory means connected to said central processing unit through said bus means and used as a work area of said central processing unit;
channel selecting means connected to said central processing unit through said bus means for selecting one of a plurality of channels;
control signal receiving circuit means connected to said central processing unit through said bus means for receiving a control signal and controlling said channel selecting means;
shift register means connected to said central processing unit through said bus means;
clock pulse generating means for supplying a clock pulse to said shift register means synchronized with the synchronizing signal of said video signal and generating a serial signal representing a character pattern from said shift register means; and
mixing means for mixing said video signal and said serial signal;
said control program in said read only memory means containing font data to be displayed, a main program for decoding said control signal and controlling said channel selecting means, and an interrupt program for loading the font data from said read only memory means into said shift register means.
2. A television receiver according to claim 1; further comprising an integrated circuit chip, said central processing unit, said bus means, said read only memory means, said random access memory means and said shift register means being formed on said chip. 3. A television receiver according to claim 1; wherein said synchronizing signal includes a horizontal synchronizing pulse, said central processing unit is interrupted by said horizontal synchronizing pulse, and said interrupt program is started by said horizontal synchronizing pulse. 4. A television receiver according to claim 3; wherein a horizontal trace period follows said synchronizing signal and said font data from said read only memory means is loaded into said shift register means during a first portion of the horizontal trace period and said serial signal is generated during a second portion of the horizontal trace period.
1. Field of the Invention
The present invention relates generally to a television receiver and more particularly is directed to a television receiver which can indicate the numeral of a channel after the channel is changed.
2. Description of the Prior Art
There is proposed a television receiver in which when a channel is changed, the numeral indicative of the channel after the channel is changed is indicated on the screen of a cathode ray tube during a predetermined period. Such previously proposed television receiver is disclosed in U.S. Pat. No. 3,748,645, U.S. Pat. No. 3,812,285 and so on. A conventional channel indicator used in such television receiver requires a special LSI (large scale integration) chip to indicate the numeral of the channel. However, such LSI chip requires a substantial investment in time and money from its designing to the completion, and when the designing thereof is changed midway, it is quite difficult to cope with such change.
Moreover, it is difficult to give an individuality to the character pattern of the numeral indicating the channel. Furthermore, the number of ICs (integrated circuits) is increased and hence the manufacturing cost is inevitably raised.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved television receiver which is free from the problem inherent to the prior art.
It is another object of the present invention to provide a television receiver which can indicate the numeral of a channel after the channel is changed by employing a microcomputer.
It is still another object of the present invention to provide a television receiver in which an individuality can easily be given to the character pattern of the numeral of a channel to be indicated.
It is further object of the present invention to provide a television receiver which can reduce the number of integrated circuits.
According to one aspect of the present invention, there is provided a television receiver comprising:
(a) a central processing unit having an interrupt function;
(b) a bus means connected to said central processing unit;
(c) a read only memory means connected to said central processing unit through said bus means and containing a control program to be executed by said central processing unit;
(d) a random access memory means connected to said central processing unit through said bus means and used as a work area of said central processing unit;
(e) a channel selecting means connected to said central processing unit through said bus means for selecting one of a plurality of channels and producing a video signal; and
(f) a control signal receiving circuit means connected to said central processing unit through said bus means for receiving a control signal and controlling said channel selecting means;
characterized in that said television receiver comprises:
(g) a shift register means connected to said central processing unit through said bus means;
(h) a clock pulse generating means for supplying a clock pulse to said shift register means synchronized with the synchronizing signal of said video signal and generating a serial signal representing a character pattern from said shift register;
(i) a mixing means for mixing said video signal and said serial signal; and
(j) an interrupt means for interrupting an operation of said central processing unit synchronized with a synchronizing pulse of the video signal, said control program in said read only memory means containing a font data to be displayed, a main program for decoding said control signal and controlling said channel selecting means, and an interrupt program for loading the font data from said read only memory means to said shift register means.
The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like references designate the same elements and parts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of an embodiment of a television receiver according to the present invention;
FIG. 2 is a table showing a 16-bit font data used in the present invention;
FIG. 3 is a diagram showing a screen of the television receiver of the present invention on which a numeral of channel is indicated and waveforms of pulses used in explanation thereof;
FIG. 4 is a diagram showing the format of a remote control signal used in the present invention; and
FIGS. 5 to 8 are respectively flow charts used to explain the operation of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Now, an embodiment of a television receiver according to the present invention will hereinafter be described with reference to the attached drawings.
In FIG. 1 showing an example of the present invention, reference numeral 10 generally designates a video signal system, 11 a tuner, 12 a video intermediate frequency (VIF) amplifier, 13 a video detecting circuit, 14 a video amplifier and 15 a cathode ray tube, respectively. In this case, the tuner 11 is formed as an electronic tuning system which can receive the video signal of a desired channel by changing a value of a tuning voltage Ec supplied thereto.
Reference numeral 20 generally designates a microcomputer, 21 a 4-bit parallel CPU (central processing unit), 22 a ROM (read only memory) in which a program and a font data for indicating a numeral of a channel are written or stored, 23 a RAM (random access memory) for a work area and 31 to 36 input/output ports. These circuits 22 to 36 are connected through a bus 24 to the CPU 21.
Reference numeral 37 designates a 16-bit serial/parallel input and serial output shift register. This shift register 37 is used to generate a signal Sn which indicates the numeral of the channel. To the shift register 37 loaded line by line in parallel is a 16-bit font data indicating the numeral of a channel as, for example, shown in FIG. 2 from the port 32. The font data loaded to the shift register 37 is delievered therefrom in series from MSB (most significant bit) as the signal Sn. At that time, the serial input terminal of the shift register 37 is made at "0" level.
The signal Sn derived from the shift register 37 is supplied to the video amplifier 14 in which the signal Sn is composed on or mixed with the video signal.
The microcomputer 20 together with this shift register 37 is formed as one chip IC (integrated circuit).
Reference numeral 41 designates a D/A (digital-to-analog) converter. The output from the port 31 is supplied to this D/A converter 41 from which the tuning voltage Ec is derived. This tuning voltage Ec is supplied to the tuner 11.
Reference numeral 42 designates a receiving element which receives a remote control signal and 43 its receiving circuit connected thereto. When the remote control signal is, for example, an infrared remote control signal, the receiving element 42 is formed as an infrared ray receiving element and the receiving circuit 43 generates a remote control signal Sr. This remote control signal Sr is the signal which corresponds to an output from a remote control signal transmitter (not shown) and has a format as, for example, shown in FIG. 4. Namely, in this remote control signal, a guide pulse having a pulse width of 2400 μsec exists in the beginning and code pulses of 16 bits from b 0 to b 15 follow the guide pulse with an interval of 600 μsec. In this case the code pulses b 0 to b 15 indicate "0" or "1" in respose to the content of the remote control. When "0", the pulse width is selected as 600 μsec, while when "1", the pulse width is selected as 1200 μsec. This remote control signal Sr is supplied to the port 33.
Reference numeral 44 designates a non-volatile memory which is connected to the port 34 and in which a digital value of the tuning voltage Ec at each channel is stored. Reference numeral 45 designates an input key which is used to change the channel, the sound volume and so on, in which the dynamic scan is carried out by the output from the port 35, and the switching output from which is inputted to the port 36 to detect which key is operated.
Reference numeral 51 designates a synchronizing (sync) separating circuit to which the video signal from the video detector circuit 13 is supplied and from which a vertical synchronizing pulse Pv and a horizontal synchronizing pulse Ph are derived respectively. These pulses Pv and Ph are supplied to the CPU 21 as interrputing signals H-INT and V-INT. The pulse Ph is supplied to a monostable multivibrator 52 which generates a pulse P 52 which becomes "1" from a falling down or trailing edge time point t 1 of the pulse Ph to a start time point t 2 of the display period of the numeral of the channel as shown in FIG. 3 (in which reference numeral 151 designates the screen of the cathode ray tube). This pulse P 52 is supplied to a gated oscillating circuit 53 as its oscillating control signal so that from the gated oscillating circuit 53 is derived an oscillating pulse P 53 during the period from t 2 to t 4 in which the pulse P 52 is "0" as shown in FIG. 3. This pulse P 53 is supplied to the shift register 37 as the clock. At that time, the frequency of the pulse P 53 is selected as a value corresponding to a dot pitch in the lateral direction of the numeral of the channel to be indicated.
Accordingly, since the font data on, for example, the first line in FIG. 2 is loaded to the shift register 37 during the first half period from t 1 to t 2 of the 45th horizontal trace period, this font data is extracted from the shift register 37 as the serial signal Sn in response to the pulse P 53 during the second half period from t 2 to t 3 of the above horizontal trace period and then supplied to the video amplifier 14, the numeral of the channel on the first line is indicated on the screen 151 in the interval corresponding to the period from t 2 to t 3 of the 45th line. Although during the period from t 3 to t 4 the pulse P 53 is supplied to the shift register 37, the serial input terminal of the shift register 37 is at "0" level and this "0" level is derived from the shift register 37 during the period from t 3 to t 4 so that no numeral of the channel is indicated on the screen 151 in the interval corresponding to the period from t 3 to t 4 .
When such operation is performed for the 45th to 51st horizontal lines by employing the font data on the 1st to 7th lines shown in FIG. 2, the channel numeral corresponding to the font data in FIG. 2 is displayed as shown in FIG. 3. If the data of all "0" is loaded to the shift register 37 as the font data, the channel numeral is not indicated.
FIGS. 5 to 8 respectively show flow charts of the programs written in the ROM 22 and FIG. 5 shows the main routine thereof.
This main routine shown in FIG. 5 starts from a step 501 and in a step 502 the initializing is carried out. Thus, a flag FLG, a buffer BUFF and counters CHCNT, HCNT and WCNT are set in, for example, the RAM 23 and these are all reset (cleared) to "0".
A step 503 is such a step in which the existence or not of the remote control signal Sr is judged by the existence or not of the guide pulse, namely, by detecting whether the "1" level of the signal Sr lasts 2400 μsec or not. A step 504 is such a step which judges whether or not there is the input to the key 45, and a step 531 is such a step which judges whether the counter CHCNT is "0" or not. Consequently, when powered, CHCNT=0 is established in the step 502 so that the loop of step 503➝step 504➝step 531➝step 503 is repeated to thereby poll the input of the remote control signal Sr and the input from the key 45. In this case, the counter CHCNT serves as a flag indicative of the existence or not of the request for changing the channel and a timer for setting the displaying period of the channel numeral.
When the remote control signal Sr exists, the bits b 0 to b 15 of the signal Sr are latched in a step 800 and the step is moved to a step 511. Also when an input exists in the step 504, the step 504 moves to the step 511, too. In the step 511, it is judged whether the remote control input in the step 800 and the key input in the step 504 are the commands for changing the channel or not.
When the above inputs are the command for changing the channel, the counter CHCNT is set to "1" in a next step 512. Subsequently, in a step 513, on the basis of the channel data indicated by the remote control signal Sr inputted at the step 800 and the key input in the step 504, a digital tuning voltage data E D for tuning to the channel is read out from the non-volatile memory 44 (see FIG. 1). This digital tuning voltage data E D is outputted to the port 31 in a step 514. Thus, by the analog tuning voltage Ec from the D/A converter 41, the television receiver is set in the receiving state of the channel inputted in the step 800 or 504, thereafter.
In a step 515, from the ROM 22, a font data (data as, for example, shown in FIG. 2) displayed as a numeral of a new channel after the channel is changed is loaded to the buffer BUFF. Although the detail will be described later, the font data in the buffer BUFF is sequentially loaded line by line to the shift register 37 during the 45th to 51st horizontal trace period t 1 to t 2 of each field in accordance with a subroutine 700 shown in FIG. 7. As a result, the channel numeral after the channel is changed is indicated on the screen 151.
When the channel numeral is indicated on the screen 151, the procedure step is returned to the step 503. At that time, since CHCNT=1 is established in the step 512, the procedure step is moved in the order of the step 503➝the step 504➝the step 531➝a step 532. In this step 532, the counter CHCNT is incremented by "1" and in a next step 533, whether the count CHCNT reaches a predetermined value MAX or not is checked where the value MAX is the value corresponding to the period during which the channel numeral is displayed upon changing the channel.
And, if CHCNT
When CHCNT=MAX is esbalished, the buffer BUFF is cleared to "0" in a step 541. Therefore, since "0" is loaded through the buffer BUFF to the shift register 37 as the font data, Sn="0" is established thereafter so that the channel numeral is not indicated any more.
In a next step 542, the counter CHCNT is reset to "0" and the procedure step is returned to the step 503.
As described above, when the channel change data is inputted, the channel is changed and the channel numeral after the channel is changed is indicated during a constant period.
When the inputs in the steps 800 and 504 are not the commands for changing the channel but the commands for changing, for example, the sound volume, in a step 521 the counter CHCNT is reset to "0" and then in a step 522, the operation based on the commands inputted in the steps 800 and 504 is carried out. The circuitry for executing the procedure except for changing the channel can be made the same as in the prior art and hence it is omitted to show the same in FIG. 1.
On the other hand, FIGS. 6 and 7 respectively show subroutines in which the font data in the buffer BUFF is loaded to the shift register 37. The subroutine 600 shown in FIG. 6 is the interrupt subroutine which is executed when the interrupt procedure is executed by the vertical synchronizing pulse Pv. When the vertical synchronizing pulse Pv is supplied to the CPU 21, this subroutine 600 starts from a step 601 and in a step 602, the counter HCNT is reset to "0". In a step 603, the subroutine 600 is ended and returned to the original main routine.
Accordingly, by this subroutine 600, the counter HCNT is reset to "0" at every start point of each field.
The subroutine 700 shows in FIG. 7 is the interrupt subroutine which is executed when the interrupt procedure is executed by the horizontal synchronizing pulse Ph. When the horizontal synchronizing pulse Ph is supplied to the CPU 21, the subroutine 700 starts from a step 701 and in a step 702, a flag FLG indicative of whether the subroutine 700 is executed or not is set to "1". Then, in a step 703, the counter HCNT is incremented by "1". In this case, since the counter HCNT is reset to "0" by the subroutine 600 at every start point of each field and the subroutine 700 is executed at each horizontal syncronizing pulse Ph, the counter HCNT indicates the line number of the horizontal line at each field period.
In a next step 704, the magnitude of the counter HCNT is checked. When 45≤HCNT≤51, in a step 711, the font data in the buffer BUFF (the data as, for example, shown in FIG. 2) is loaded line by line to the shift register 37 from the buffer BUFF each time when the counter HCNT is incremented by "1" each (at every horizontal lines). On the other hand, when 45≤HCNT≤51 is not established, in a step 721, all "0" is loaded to the shift register 37. Then, the subroutine 700 is ended at a next step 712 and returned to the original main routine.
If necessary, the subroutine 700 is provided with a timer routine by which the duration of time necessary for completing the subroutine 700 is set as 40 μsec (the period shorter than the period from t 1 to t 2 ).
Consequently, during the period from t 1 to t 2 in the 45th to 51st horizontal trace periods, by the subroutine 700 the data in the buffer BUFF is loaded to the shift register 37. Then, if the data loaded to the shift register 37 is the font data, the channel numeral is indicated during the period from t 2 to t 3 . While during the period from t 1 to t 2 in other horizontal trace period, the data indicative of all "0" is loaded to the shift register 37 from the buffer BUFF so that the channel numeral during the period t 2 to t 3 is not displayed.
Upon changing the channel, during the predetermined period, the font data regarding the channel numeral after the channel is changed is loaded to the buffer BUFF in the step 515. After that, since the data indicative of all "0" is loaded to the buffer BUFF in the step 541, in accordance with the subroutine 700, during the predetermined period from the change of the channle, the channel numeral after the channel is changed is indicated on the screen 151 as shown in FIG. 3. After the predetermined period elapses, the display is not carried out any more.
FIG. 8 shows a subroutine 800 which is used to read the remote control signal Sr. This subroutine 800 starts from a step 801. In a next step 802, a pointer i is reset to "0" and in a succeeding step 811, a delay corresponding to the "0" level period of 600 μsec between the trailing edge of the guide pulse and the rising edge of the bit b 0 (see FIG. 4) is carried out. Further, in a next step 821, the counter WCNT is reset to "0". In this case, the pointer i indicates a particular bit of the bits b 0 to b 15 of the remote control signal Sr and i=0 to 15. Also, the counter WCNT is used to check the respective pulse widths of the bits b 0 to b 15 .
After the delay of 70 μsec is performed in a succeeding step 822, whether the flag FLG is "0" or "1" is checked in a next step 823. When FLG=0, namely, the interrupt procedure is not executed, the counter WCNT is incremented by "1" in a following step 824. When FLG=1, namely, the interrupt procedure is executed, the counter WCNT is incremented by "2" in a step 825 and the processing time due to the interrupt procedure is corrected. Thereafter, the flag FLG is reset to "0" in a next step 826. Then, in a step 827, it is checked whether the level of ith bit of the remote control signal Sr reaches the "0" level or not, namely, whether ith bit is ended or not. When ith bit is not ended, the step 827 returns to the step 822, while when ended, the step 827 advances to a step 831.
Accordingly, during the period in which the level of ith bit of the signal Sr is at the "1" level, the loop from the steps 822 to 827 is repeated. Upon repeating the loop from the steps 822 to 827, if the interrupt subroutine 700 is not executed at all, the FLG=0. Therefore, in the steps 822 and 824, the counter WCNT is incremented by "1" each at every 40 μsec. Thus, at the time when the above loop is ended, if ith bit is "0" (namely, the pulse width is 600 μsec), WCNT=15, while if ith bit is "1" (namely, the pulse width is 1200 μsec), WCNT=30 (the processing time necessary for other steps is neglected for simplicity).
Upon repeating this loop from the steps 822 to 827, if the interrupt subroutine 700 is executed, 40 μsec is consumed to execute such subroutine. This is the same as that necessary for executing the step 822 once. Also, at that time, since FLG=1 (step 702), the counter WCNT is incremented by "2" in the step 825. As a result, at the time when this loop is ended, if ith bit is "0", WCNT=15, while if ith bit is "1", WCNT=30.
After the above loop is ended, the counter WCNT is checked in the step 831. If WCNT≤15, the level "0" of ith bit is set in the RAM 23 in a step 832, while if WCNT>15, the level "1" of ith bit is set in the RAM 23 in a step 833. In a next step 834, whether the above procedure is executed for all the bits of the remote control signal Sr or not is checked by the pointer i. When the above procedure is not yet executed for all the bits, the pointer i is incremented by "1" in a step 835 and then the step 835 returns to the step 811. On the contrary, when the above procedure is executed for all the bits, the step 834 advances to a step 841.
In the step 841, the remote control signal Sr is judged on the basis of the data in the steps 832 and 833. And, in a step 842, this subroutine 800 is ended and returned to the original main routine.
As set forth above, according to the present invention, it is possible to perform the change of the channel and to indicate the channel numeral at that time. In this case, particularly in accordance with the present invention, the change of the channel and the indication of the channel numeral after the channel is changed are carried out by the use of the ordinary microcomputer 20 so that the time and cost necessary from designing to completing can be reduced extremely. Moreover, when the designing is changed in the midway thereof, the designing can be changed with ease.
Further, the individuality can be given to the character pattern of the numeral of the channel to be indicated with ease. Also, since the number of the ICs can be reduced, this is advantageous for reducing the manufacturing cost and for increasing reliablity.
In addition, in the above description, it is possible to provide the steps 531 to 542 in the subroutine 600.
The above description is given on a single preferred embodiment of the invention, but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the invention, so that the scope of the invention should be determined by the appended claims only.