JVC AV-32WP2EN CHASSIS MB 100HZ PWB ASS'Y FEATURE UNIT SMB0Z001B-U2 VIEW ON MAIN PWB ASS'Y SMB-1901B-U2

100HZ PWB ASS'Y FEATURE UNIT SMB0Z001B-U2

It's mAinly based on SIEMENS MEGAVISION CHIPSET.



SDA 9205-2 Triple 8-Bit Analog-to-Digital-Converter CMOS IC


General Description
The SDA 9205-2 is a single monolithic IC containing three separate 8-bit analog to digital converters
for video (YUV) applications. It utilizes an advanced VLSI 1.2 mm CMOS process providing 30-MHz
sampling rates at 8 bits. Different digital output multiplex formats are selectable on chip via several
control inputs, compatible to inputs of all Siemens Featureboxes, Siemens TV-SAM, and CCIR 656
output format.
The ADCs have no missing codes over the full operating temperature range of 0 to + 70 °C.
Operation is from + 5 V DC-power supply.


Features
l Three equivalent CMOS A/D converters on chip
l 30-MHz sample rate
l 8-bit resolution
l No external sample & hold required
l On-chip input buffer for each analog channel
l Internal clamping circuits for each of the ADCs
l Different digital output multiplex formats:
– 3 independent unmultiplexed 8-bit outputs
– Multiplexed formats compatible to inputs of all
Siemens Featureboxes and Siemens TV-SAM
– CCIR 656 output format
l Overflow and underflow outputs

Circuit Description
Analog to Digital Converter
The SDA 9205-2 implements 3 independent 8-bit analog-to-digital converters.
They are two step converters with a coarse comparator block and two fine comparator blocks each
using pipeline architecture for high speed sampling performance. During the first clock cycle, the
coarse comparator samples and determines 4 MSBs and one of the fine comparator blocks
samples the input voltage. During the second clock cycle this fine comparator block makes its
decision for the 4 LSBs. So the coarse comparator block makes its decisions at each clock cycle,
the fine comparator blocks make the comparison alternating every two clock cycles.
The converter uses the redundancy principle to correct fine conversion. The sample and hold
function has been distributed in each comparator due to the two step conversion principle.
Clamping
An internal clamping circuit is provided in each of three analog channels. The analog pins AINA,
AINB, AINC are switched simultaneously to on chip generated clamping levels by an active high
pulse on pin 30 (CLAMP).

Digital Signal Processing
The digital signal processing block performs averaging of sampled data. The a, b, g 8-bit busses
represent the results of DSP function with input data from a, b, c, 8-bit busses. A special DSP
function in combination with a special output coding format is defined by four control pins
CONT0 … CONT3

Output Coding
Eight different digital output multiplex formats are available. They are selectable via four control
lines CONT0 … CONT3. These multiplexed formats perform combinations of DSP functions of the
several converters (A, B, C).

The digital output data are synchronized by the FSY signal. The first high of FSY defines the first
output format byte and is synchronized to CLK. In case of asynchronism the first (in formats 8:1:1,
4:1:1 the first and the second) output format byte after FSY had gone high does not contain valid
data.

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SDA 9251-2X 868352-Bit Dynamic Sequential Access Memory for Television Applications (TV-SAM) CMOS IC


Functional Description
The SDA 9251 is a triple port 868 352 bit dynamic sequential-access memory for high-data-rate
video applications. It is organized as 212 rows by 64 columns by 16 arrays by 4 bit to allow for the
storage of 4-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality
(13.5-MHz basic sample rate) or 4-bit planes of parts of a HDTV field. The memory is fabricated
using the same CMOS technology used for 1-Mbit standard dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 4-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 x 4-bit input
shift register C to an addressed location of the memory array and from the memory array to one of
the 16 x 4-bit output shift registers A or B is controlled by the serial column address (SAC) which
contains the desired column address and an instruction code (mode bits) for transfer and refresh.
Circuit Description
Memory Architecture
As shown in the block diagram, the TV-SAM comprises 64 memory arrays which are accessed in
parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the
64 (= 16 x 4) arrays can be randomly addressed, reading or writing 16 x 4 bits at a time. To obtain
the extremely high data rate at the 4-bit wide data input (SDC) and outputs (SQA, SQB), a parallel
to serial conversion is done using shift registers of 16-bit length and 4-bit width. In this way the
memory speed is increased by a factor of 16. (This is independent on the number of ports if the total
data rate is regarded.)
Independent operation of the serial input and the two serial outputs is guaranteed by using three
shift registers. The decoupling from the common 16 x 4-bit memory data bus is done by three
latches which allow a flexible memory timing and a flying real-time data transfer.
A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at
maximum clock speed.
To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row
address and a serial 8-bit column address which includes two mode control bits. The serial row and
column addresses are converted to parallel addresses internally, then latched and fed to the row
and column decoders. The internal memory controller is responsible for the timing of the memory
read/write access and the refresh operation.

Features
l 212 x 64 x 16 x 4-bit organization
l Triple port architecture
l One 16 x 4-bit input shift register
l Two 16 x 4-bit output shift registers
l Shift registers independently and simultaneously
accessible
l Continuous data flow even at maximum speed
l 33-MHz shift rate - 0.27-Gbit/s total data rate
l All inputs and outputs TTL-compatible
l Tristate outputs
l Random access of groups of 16 x 4 bits for a wide range
of applications
l Refresh-free operation possible
l 5 V ± 10 % power supply
l 0 … 70 °C operating temperature range
l Low power dissipation: 550 mW active, 28 mW standby
l Suitable for all common TV standards
l Allows flicker and noise reduction simultaneously
with only one field memory
l Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV


SDA 9270 Field Mixer



1 Introduction
The Field Mixer SDA 9270 is an add-on component for
the Siemens MEGAVISION IC set which enables the
system to reduce large area and line flickering of
interlaced TV standards.


System Description
The device generates at its output an opportune sequence of 100/120 Hz fields derived
by processing the field A and the field B which are stored in 2 external field memories
and made available to the SDA 9270 on 2 separate input ports of 16 bit width each.
The device SDA 9270 generates also control signals for the SDA 9251 which are
necessary to operate the TV - SAMs in the Frame mode, that is to write the incoming
information alternatively in one or the other field memory.
Additionally the device generates a vertical sync pulse which has to be synchronized
with the respective field output. A horizontal blanking signal in phase with the output data
is also made available.

Input Data Format
The SDA 9270 accepts for the input channels A and B two different input formats
(I2C-Bus : INFOR) with two possible sample frequency relations of Y : (B-Y) : (R-Y). The
representation of the samples is programmable separately for luminance and
chrominance signals as positive dual code or 2’s complement code (I2C-Bus : INCODL,
INCODC)

The amplitude resolution for each input signal component is 8 bit, the maximum clock
frequency is 30 MHz. Consequently the SDA 9270 is dedicated for applications in high
quality digital video systems. The data input stages and the internal data multiplexer
operate with a special input clock (SCA). For applications in the Siemens MEGAVISION
System the SCA-clock is identical with the memory output clock.


Field Interpolation and Switching
In order to reduce the annoying line and edge flickering a frame rate upconversion is
implemented. The upconversion includes a combination of interpolation algorithms
which are determined via I2C-Bus and then selected automatically depending on the
picture motion content.
The field interpolation and switching block accepts at its input the data of the two
channels A and B, which are the combined luminance and chrominance information
respectively of the field A and the field B. The field rate is 100/120 Hz.
A fallback mode which corresponds to the operating mode AABB of the original
MEGAVISION system is made available. This mode is selected automatically in case of
non-standard input signals carrying unstable sync informations or it can be forced via
I2C-Bus.
2.4 Motion Detection
The motion detection output is switched in a 25/30 Hz frame synchronous raster. As
input signals for this block are accepted the luminance signal components of the input
channels A and B. By comparing the two fields the motion detector generates an
information about 3 possible motion content levels: LOW, MEDIUM and HIGH.
2.5 Field Memory Control
The Field Mixer SDA 9270 has to provide the two external field memories – composed
of TV-SAM SDA 9251 – with two pairs of control signals. One pair RENA and RENB
enables the MEGAVSION system to write the incoming field A and field B information
alternately into one field memory block and then into the other. A second pair of control
signals OEBA and OEBB enables alternately the output back channels of field memory
A and B for the noise reduction in the Picture Processor SDA 9290. Because of the
timing the serial address signals SAC and SAR generated by the MSC SDA 9220 must
be delayed by 4 SCAD-clock periods. This delay is implemented in the SDA 9270.
The Sync signals VS1 and BLN and the clock signal SCAD are used as timing reference
signals.
2.6 Frame Synchronization
In order to synchronize the data flows within field memories and Field Mixer and to
coordinate the signal information with the associated deflection control the Field Mixer
SDA 9270 has to generate 25 Hz picture frame sync signals.
One 25 Hz frame sync signal is necessary for generating the field memory control
signals RENA, RENB, OEBA, OEBB with a pattern repetition of 25 Hz each. This signal
is synchronized to the front end side video signal of the MEGAVISION block and uses
therefore as input signals the 50 Hz vertical sync signal VS1 generated by the MSC SDA
9220 and the horizontal blanking signal BLN.

A second 25 Hz frame sync signal is needed in the interpolation and switching block and
in the VS3 pulse generation block for assuring an output data sequence of the channel
Q synchronized with the VS3 pulse. As reference signals for this second frame sync
signal are used the 100 Hz vertical sync signal VS2 and the blanking signal BLN2 both
generated by the MSC SDA 9220.
2.7 SYNC-Signal Generation
This functional block generates a couple of sync signal needed in the processing stages
following the Field Mixer device. This couple includes the vertical sync signal VS3 and
the horizontal blanking signal BLN3. All these signals are synchronized with the output
channel Q.



SDA 9253 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) CMOS IC


Functional Description
The SDA 9253 is a triple port 2605056 bit dynamic sequential-access memory for high-data-rate
video applications. It is organized as 212 rows by 64 columns by 16 arrays by 12 bit to allow for the
storage of 12-bit planes of a TV field (NTSC, PAL, SECAM, MAC) in standard or studio quality
(13.5-MHz basic sample rate) or 12-bit planes of parts of a HDTV field. The memory is fabricated
using the same CMOS technology used for 4-Mbit standard dynamic random access memories.
The extremely high maximum data rate is achieved by three internal shift registers, each of 16-bit
length and 12-bit width, which perform a serial to parallel conversion between the asynchronous
input/output data streams and the memory array. The parallel data transfer from the 16 ´ 12-bit
input shift register C to an addressed location of the memory array and from the memory array to
one of the 16 ´ 12-bit output shift registers A or B is controlled by the serial row-(SAR) and column
address (SAC) which contains the desired column address and an instruction code (mode bits) for
transfer and refresh.
Circuit Description
Memory Architecture
As shown in the block diagram, the TV-SAM comprises 192 memory arrays, which are accessed in
parallel. Each memory array has a size of 212 rows by 64 columns. The rows and columns of the
192 arrays can be randomly addressed, reading or writing 16 ´ 12 bits at a time. To obtain the
extremely high data rate at the 12-bit wide data input (SDC) and outputs (SQA, SQB), a parallel to
serial conversion is done using shift registers of 16-bit length and 12-bit width. In this way the
memory speed is increased by a factor of 16. (This is independent on the number of ports if the total
data rate is regarded.)
Independent operation of the serial input and the two serial outputs is guaranteed by using three
shift registers. The decoupling from the common 16 ´ 12-bit memory data bus is done by three
latches which allow a flexible memory timing and a flying real-time data transfer.
A real-time data transfer is necessary to ensure a continuous data flow at the data pins even at
maximum clock speed.
To save pins without loosing speed, the TV-SAM is addressed serially using a serial 8-bit row
address and a serial 8-bit column address which includes two mode control bits. The serial row and
column addresses are converted to parallel addresses internally, then latched and fed to the row
and column decoders. The internal memory controller is responsible for the timing of the memory
read/write access and the refresh operation.


Features
l 212 ´ 64 ´ 16 ´ 12-bit organization
l Triple port architecture
l One 16 ´ 12-bit input shift register
l Two 16 ´ 12-bit output shift registers
l Shift registers independently and simultaneously
accessible
l Continuous data flow even at maximum speed
l 40-MHz shift rate – 0.96-Gbit/s total data rate
l All inputs and outputs TTL-compatible
l Tristate outputs
l Random access of groups of 16 ´ 12 bits for a wide range
of applications
l Refresh-free operation possible
l 5 V ± 10 % power supply
l 0 … 70 °C operating temperature range
l Low power dissipation: 700 mW active, 28 mW standby
l Suitable for all common TV standards
l Allows flicker and noise reduction simultaneously
with only one field memory
l Applications: TV, VCR, image processing,
video printers, data compressors, delay lines,
time base correctors, HDTV




SDA 9280 B22 Display Processor

Features
• 8-Bit amplitude resolution of each input component
Input sample frequency up to 30 MHz
Application in flicker reduction systems possible
• Four input data formats
4:1:1 luminance and chrominance parallel
(8 + 4 wires)
4:2:2 CCIR 656-format (8 wires)
4:2:2 luminance and chrominance parallel (2 x 8 wires)
4:4:4 all components parallel (3 x 8 wires)
• Two different representations of input data
Positive dual code
2’s complement code
• Three D/A converters on-chip
9-Bit amplitude resolution
80 MHz maximal clock frequency
• DCTI (digital color transient improvement)
A digital algorithm improves the sharpness of vertical color edges
avoiding the artifacts of analog CTI-circuits
• Luminance peaking
Separate programmable lowpass, bandpass, and highpass digital filters
• High performance digital interpolation for anti-imaging
Two-fold oversampling
Simplification of external analog postfiltering
• 16:9 compatibility
Signal compression for displaying 4:3-signals on16:9-screens
Signal expansion for displaying 16:9-signals on 4:3-screens
Full screen display of 4:3 letter box pictures.

Programmable delay for the luminance signal
Phase adjustment between luminance and chrominance signals
• Signal manipulations
Inverted display
Graphic display
• Insertion of colored areas
Programmable color and position
• Insertion of an arbitrary pattern
Control by an external signal
One of 4096 colors programmable
Frame insertion for multi picture display
• N-Fold zoom facility for image memory systems
• Programmable internal PLL for clock generation
Control of compression and expansion factors.


General Description
The Display Processor SDA 9280 is an integrated triple 9 Bit D/A converter which
performs digital enhancements and manipulations of digital video component signals.
Multiple input data formats are accepted. Operation with normal as well as doubled
horizontal deflection frequency is supported. 4:3 or 16:9 display formats are possible.

Digital Color Transient Improvement (DCTI)
A new digital algorithm is implemented to improve horizontal transitions of the
chrominance signals resulting in a better picture sharpness. A slow change from one
color to another by reason of small chrominance bandwidth is replaced by a steep
transition.
The exact position of a color transition (POS) is calculated by detecting the
corresponding zero transition of the second derivative of both chrominance signals. Low
pass filtering (LPU, LPV, LPUV) is performed to avoid noise sensitivity. The width of a
transition is derived from a threshold detector signal. It indicates an area around the
detected position where the first derivatives of the chrominance signals exceed a
programmable threshold (I2C signal: THRESH). The parameter THRESH modifies the
sensitivity of the DCTI-circuit. High values cause that only significant color transitions are
improved. Small color variations remain unchanged. The detected transition width can
be limited by the programmable parameter TRAWID. This parameter performs an
adaption to the input chrominance band width. For signals with small chrominance
bandwidth (e.g. video recorders) the DCTI-performance is optimized using high values
for TRAWID. Input signals with high chrominance bandwidth should be processed with
small values for TRAWID. If standard 4:1:1 video signals are processed, it is
recommended to choose values of the mid range for both parameters THRESH and
TRAWID.


Picture Manipulations
A graphic display effect is realized by programmable reduction of amplitude resolution
(I2C signals: YGR, YGRRES, CGR, CGRRES). A resolution of 1 to 4 bits is available. A
special characteristic avoids a reduction of picture brightness and color saturation.
The inverted display mode is attained by a programmable bit inversion for each signal
component (I2C signals: YINV, UINV, VINV).
Multiple combinations of both manipulations supply very amazing effects on the display.
2.6 16:9-Operation, Signal Compander
The compander enables a display with correct geometric proportions of 4:3 signals on
16:9-screens or 16:9-signals on 4:3-screens. A full screen display of 4:3-letterbox
signals on 16:9-screens is also practicable. Having a full screen display of such signals
on 4:3-screens only a part of the picture can be shown. In this operation mode a
horizontal shift of the picture part used for display is programmable (I2C signal: READD).
Expansion in vertical direction must be realized by manipulation of the vertical deflection
current.
To satisfy all these demands a horizontal compression or expansion of the video signals
is performed by raising or reducing the sample frequency. The data are written into a
memory using the system clock CLL and read with a clock of higher or lower frequency.

This realization does not effect the horizontal detail resolution of the picture because no
filtering is executed.
The highest read frequency is 4/3 of the CLL-frequency for signal compression, the
lowest is 3/4 of the CLL-frequency for signal expansion. The reading clock is supplied by
the internal PLL.
The compander operation mode is programmable via I2C signals COMP and COMEX.