The Panasonic EURO-1 Is the first PANASONIC TV CHASSIS entirely Digital Technology.
IT Is completely based on the ITT DIGIVISION DIGIT2000 Chipset technology but furtherer improved by ITT adding more improvement functions in the original DIGIT2000.
For a complete technology reference of the Digivision ITT DIGIT2000 you can Read HERE
Indeed there are newly named IC's such as:
- VDU2146 Video Display Unit.
- DTI2223 Digital Transient Improvement
- ACVP2205 Adaptive Combifilter Video Processing
- MCU2600 Main Clock Unit
- SPU2243 Secam Processing Unit
- DPU2553 Deflection Processor Unit
- SAD2140 Signal Analog to Digital Conversion
- TPU2735 Teletext Processor Unit
- CCU3000 Computer control Unit
- MN8333 Digital feature Unit (Panasonic)
- ACP2371 Audio Control Processing
Technology overview:ACVP2205 (Adaptive Combifilter Video Processing)
In a chroma control circuit for a digital television receiver, the system clock lies in the range of four-times the chrominance-subcarrier frequency. The originally received color-burst signal is locked in frequency and phase to the system clock by means of an all-digital phase-locked loop. The phase-difference angle between the color-burst signal and the system clock appears as a sine or cosine value in the two standard color-difference signals of the chrominance demodulator during the reception of the color-burst signal. One of the standard color-difference signals, the B-Y signal, is fed through a horizontal-frequency-suppressing loop filter to a digital oscillator. The latter determines the speed of rotation of a hue adjustment angle rotating at approximately constant angular speed. The respective sine and cosine values of the hue adjustment angle are read as data values from first and second read-only memories, respectively, and are fed to the sine and cosine inputs of a hue adjuster in a calculating stage which derives the color-burst signal and the chrominance signal.The ACVP 2205 is a digital real–time signal processor for multistandard color TV sets based on the DIGIT2000
system. It handles composite video signals as well as
S–VHS signals. For PAL and NTSC a 2H adaptive
combfilter is implemented. It considerably improves the
picture quality by a sophisticated luminance and chrominance
separation. A single silicon chip contains the following
– selectable 7 or 8 bit video input
– code converter and a data demultiplexer for composite
and S–VHS input signals
– 2H adaptive combfilter for PAL and NTSC composite
– adjustable horizontal and vertical peaking filter for luminance
– selectable luminance filter for enhanced frequency response
– black–level–expander for improving the picture contrast
and the gamma correction
– contrast multiplier with limiter for the luminance signal
– adjustable chrominance filter
– all color signal processing circuits such as automatic
color control (ACC), color killer, PAL identification, decoder
with PAL compensation, hue correction
– color saturation multiplier with multiplexer for the color
– IM bus interface for communication with the CCU 2070
or CCU 3000 Central Control Unit
– circuitry for measuring dark current (CRT spot–cutoff),
white level and photo current, and for transferring this
data to the CCU.
The ACVP 2205 is pin compatible to the PVPU 2204 . It
is designed in N–MOS technology and is available in a
40 pin Dil plastic package.
2. Functional Description
Supplied by one of the DIGIT2000 A/D converters (VCU
2136 or SAD 2140), the ACVP 2205 separates the video
signal into luminance and chrominance. These two signals
are processed in different circuits, which will be described
in the following. The output signals are reconverted
to analog signals in the VCU 2136 or VDU 2146.
Their RGB output amplifiers are used to drive the cathodes
of the CRT (see Fig. 2–4). Additionally, the ACVP
2205 performs a number of measurements and control
operations (in conjunction with the VCU 2136 or VDU
2146)relating to picture tube alignment such as spot–
cutoff current adjustment, white level control, beam current
For a multistandard application including SECAM, the
SPU 2243 SECAM Chroma Processor must be connected
in parallel to the ACVP 2205 for chroma processing.
The different processing delays Dt can be equalized
in the DTI 2223.
A comb filter arrangement operating at a reduced data rate is provided, which requires comparably fewer storage locations than previous arrangements. A digitized composite video signal of a given codeword rate is applied to a bandpass filter, which produces a filtered signal restricted to a portion of the passband of the composite video signal. The filtered signal is then subsampled at a rate which satisfies the Nyquist criterion for information of the restricted passband. Codewords, now at a reduced data rate, are applied to a one-H delay line, and delayed and undelayed signals are combined to produce a first comb-filtered signal. The first comb-filtered signal is then applied to an interpolator, which provides a sequence of codewords at the codeword rate of the original digitized composite video signal. This sequence of codewords is then combined with the codewords of the composite video signal to produce a second comb-filtered signal.
This invention relates to signal separation systems and, in particular, to a comb filter arrangement for separating the luminance and chrominance components of a digitized video signal at a reduced data rate.
Conventional television broadcast systems are arranged so that much of the brightness (luminance) information contained in an image is represented by signal frequencies which are concentrated about integer multiples of the horizontal linescanning frequency. Color (chrominance) information is encoded and inserted in a portion of the luminance signal spectrum around frequencies which lie halfway between the multiples of the line scanning frequency (i.e., at odd multiples of one-half theline scanning frequency).
Chrominance and luminance information can be separated by appropriately combing the composite signal spectrum. Known combing arrangements take advantage of the fact that the odd multiple relationship between chrominance signal components andhalf the line scanning frequency causes the chrominance signal components for corresponding image areas on successive lines to be 180.degree. out of phase with each other. Luminance signal components for corresponding image areas on successive linesare substantially in phase with each other.
In a comb filter system, one or more replicas of the composite image-representative signal are produced which are time delayed from each other by at least one line scanning interval (a so-called one-H delay). The signals from one line are addedto signals from a preceding line, resulting in the cancellation of the chrominance components, while reinforcing the luminance components. By subtracting the signals of two successive lines (e.g., by inverting the signals of one line and then combiningthe two), the luminance components are cancelled while the chrominance components are reinforced. Thus, the luminance and chrominance signals may be mutually combed and thereby may be separated advantageously.
The composite video signal may be comb filtered in an analog form, a sampled data form, or a digital form. Comb filters using analog signal glass delay lines for the (approximately) one-H delay lines are commonly employed in PAL-type receiversto separate the red and blue color difference signals, taking advantage of the one-quarter line frequency offset of the interlacing of the two signals. An example of a comb filter system for a sampled data signal is shown in U.S. Pat. No. 4,096,516,in which the delay line comprises a 6821/2 stage charge-coupled device (CCD) delay line which shifts signal samples from stage to stage at a 10.7 MHz rate to achieve a one-H delay. The article "Digital Television Image Enhancement" by John P. Rossi,published in Volume 84 of the Journal of the Society of Motion Picture and Television Engineers (1974) beginning at page 37 shows a digital comb filter in which the one-H delay is provided by a digital storage medium for 682 codewords which is accessedat a 10.7 MHz rate.
In the CCD delay line described in the above-referenced U.S. patent, 6821/2 stages are needed to transfer charge packets related to the analog video signal. But in the digital delay line described in the Rossi article, the video signal is inthe form of eight-bit digital codewords. This arrangement requires the use of eight storage locations for each of the 682 codewords in a horizontal line, or a storage medium for 5,456 bits. Moreover, this delay line is only of sufficient size for asystem in which an NTSC color video signal is sampled at a rate of three times per subcarrier cycle (i.e., using a 10.738635 MHz sampling signal). A frequently discussed sampling frequency for digitizing the analog video signal is 14.3181818 MHz, orfour times the color subcarrier frequency. A one-H digital delay line operating at this frequency requires storage for 910 codewords which, at eight bits per codeword, requires a total of 7280 storage locations. Since a storage medium of this capacityis difficult to fabricate economically, it is desirable to provide a digital comb filter system which requires fewer storage locations.
In accordance with the principles of the present invention, a comb filter arrangement operating at a reduced data rate is provided, which requires comparably fewer storage locations than previous arrangements. A digitized composite video signalof a given codeword rate is applied to a bandpass filter, which produces a filtered signal restricted to a portion of the passband of the composite video signal. The filtered signal is then subsampled at a rate which satisfies the Nyquist criterion forinformation of the restricted passband. Codewords, now at a reduced data rate, are applied to a one-H delay line, and delayed and undelayed signals are combined to produce a first comb-filtered signal. The first comb-filtered signal is then applied toan interpolator, which provides a sequence of codewords at the codeword rate of the original digitized composite video signal. This sequence of codewords is then combined with the codewords of the composite video signal to produce a second comb-filteredsignal.
The invention pertains to a chroma control circuit for a digital television receiver.
A chroma control circuit of this kind is described in an INTERMETALL Data Book entitled "Digit 2000 VLSI Digital TV System", Freiburg/Br., June 1985, pages 163 to 174, which explain the CVPU 2210 NTSC comb-filter video processor. The chroma control circuit according to the aforementioned preambles is contained especially in FIG. 10-2 on page 165, which is described in Section 10.1.4 on page 167 and in Section 10.1.6 on page 168.
In the NTSC and PAL television standards, the hue of a picture element can be represented as an angle-coded signal with respect to a transmitter reference system. The different phase angles from 0° to 360° correspond to hues assigned thereto, the zero reference phase being the zero phase of one of the two standard color-difference signals, namely the B-Y signal. The transmitter reference system is the unmodulated chrominance subcarrier, which is suppressed during the horizontal trace period but is transmitted for a short time as a burst signal during the horizontal retrace period, the phase of the burst signal, referred to the B-Y color-difference signal, being
-180° in the case of the NTSC television standard, and
+/-135° in the case of the PAL television standard.
In the prior art chroma circuit, the receiver reference system is the system clock, which has four times the frequency of, and is locked in frequency and phase to, the unmodulated chrominance subcarrier; four successive system-clock pulses, beginning with the zero phase of the B-Y color-difference signal, correspond to the phase angles of 0°, 90°, 180° and 270° of the unmodulated chrominance subcarrier. The latter, which is included in the composite color signal as mentioned above, is fed to the chroma control circuit after the chrominance and luminance components have been separated from the composite color signal by means of the chrominance filter.
In the NTSC and PAL television standards, the zero reference phase of the receiver reference system is the zero phase of the B-Y color-difference signal during the reception of the color burst. In that case, the R-Y color-difference signal is zero, and the phase comparison in the phase-locked loop is very simple.
If this chroma control circuit is to operate correctly, the chrominance subcarrier and the system clock, which has four times the chrominance-subcarrier frequency, must be locked together in frequency and phase. This is accomplished with a phase-locked loop, which causes the system clock to lock with the unmodulated chrominance subcarrier.
During the further development and improvement of this integrated chroma control circuit, the inventors discovered that the action of the phase-locked loop on the frequency and phase of the system clock is disadvantageous. For example, the phase-locked loop requires a voltage-controlled oscillator for the system clock whose deviation from the reference phase during a line period must not exceed 3°. This corresponds to a permissible deviation of the system-clock frequency of only 0.03 per mill from its nominal value if the phase difference at the beginning of the scanned line is zero. Otherwise, the permissible frequency deviation is even smaller. The necessary frequency stability and control accuracy are thus very high, so that tunable crystal oscillators are used for generating the system clock.
In addition, the data resulting from the phase comparison must be fed to the voltage-controlled oscillator, which is a tunable crystal oscillator forming part of a separate monolithic integrated circuit, so that additional terminals and interconnecting leads are required for both integrated circuits.
Another problem arises if such chroma control circuits are used in television receivers with two or more receiving units which present the information from two or more signal sources or television channels on the screen simultaneously. Each of those receiving units requires a separate clock system whose frequency must be synchronized with the frequency of the respective color-burst signal. With the small differences in the frequencies of the various received color-burst signals, interaction of the associated voltage-controlled oscillators is hardly avoidable, which results in interferences on the screen. The greater the lock-in range of the tunable crystal oscillators, the stronger the interaction will be, because the frequency stability of the oscillators decreases with increasing lock-in range.
Accordingly, one object of the invention is to improve the prior art chroma control circuit in such a way that the system clock need not be locked to four times the frequency of the originally received chrominance subcarrier, so that it can be locked to other system-related signals, such as a fixed-frequency signal, and that the phase-locked loop is an all-digital circuit.
The fundamental idea of the invention is to achieve the correct adjustment of the frequency and phase between the system clock, which forms the receiver reference system, and the color-burst signal not by locking the system clock to four times the frequency and four times the phase of the color-burst signal by means of a voltage-controlled oscillator, i.e., by analog means, as has been done so far, but by leaving the frequency and phase of the system clock unchanged and taking the necessary locking measures on the received color-burst and chrominance signals. The phase of the digitalized burst signal is, therefore, rotated with respect to the zero phase of the receiver reference system purely digitally by means of a phase-locked loop until it is -180° or +/-135° in accordance with the NTSC or PAL television standard, respectively; at the same time, frequency equality is established between the rotated burst signal and the system clock. The necessary correction angle is then applied to the chrominance signal too. In case of large frequency differences between the original received color-burst signal and the system clock, the correction of the chrominance signals during the scanning line must be interpolated.
A special advantage of the invention that one or more chroma control circuits in accordance with the invention can be added to the prior art chroma control circuit to produce a television receiver for multipicture reproduction that has only a single system clock for all receiving systems.
Another important advantage is that the system clock can be synchronized with signals which are locked to the horizontal frequency or a multiple thereof. This offers advantages during operation of a video recorder and in signal processing for picture enhancement as is performed, for example, to obtain a flicker-free television picture.
Finally, the necessary interpolation of the chroma correction during the scanning line is achieved by the invention in an advantageous manner even in case of large frequency differences between the originally received color-burst signal and the system clock.
CCU 3000, CCU 3000-I Main System Processor
CCU 3001, CCU 3001-I
The CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I
are integrated circuits designed in 1.2 mm CMOS
technology, with the exception of CCU 3000, TC18 and
TC19, which is designed in 1 mm CMOS technology. The
CPU contained on the chips is a functionally unchanged
65C02-core, which means that for program development,
systems can be used which are on the market; including
high level language compilers.
The pin numbers mentioned in this data sheet refer to
the 68-pin PLCC package unless otherwise designated.
The CCU 3000-I is described separately in an addendum
on page 66.
1.1. Features of the CCU 3000, CCU 3000-I,
CCU 3001, CCU 3001-I
– CCU 3000 = ROM-less version of the CCU 3001
– 65C02 CPU with max. 8 MHz clock
– 32 kByte internal ROM (CCU 3001 only)
– 1344 internal Bytes RAM with stand-by option
– 51 I/O lines (CCU 3001)
– 26 I/O lines (CCU 3000)
– clock generator with programmable clock frequency
– 8 level interrupt controller
– CCU 3000, CCU 3001:
2 Multimaster IM bus interfaces
– CCU 3000-I, CCU 3001-I: 1I2C/IM bus and
1 Multimaster IM bus interface (see addendum)
– IR-input for software-decoded IR-systems
– on-chip power on, stand-by and clock supervision
– on-chip watchdog
– 3 multifunctional timers
– supports memory banking (external 2MBytes)
– power down signal for external memory
– mask option: EMU mode
– programs can be written in Assembler or in “C”
– CCU 3000 TC 18/19: 1.0 mm CMOS technology, (see
– application software available.
The chip is equipped with 32 kByte mask-programmable
ROM. The ROM uses up the address space from 8000H
to FFFFH. This ROM can be supplemented or replaced
externally. Only the CCU 3001 has an internal ROM.
The RAM area is split into three parts:
– page 0 (address 0 to FFH)
– page 1 (address 100H to 1FFH)
– page 3, 4, 5, 6 (address 300H to 63FH)
Page 0 offers a particularly fast access to the 65C02 and
is therefore very valuable for fast, compact programs.
Page 1 contains the stack and must therefore also have
RAM. The remaining RAM-memory follows in pages 3,
4, 5, 6, as page 2 is reserved as I/O address space. The
RAM can be kept in the stand-by mode via stand-by pin.
The CPU core is fully compatible with the 65C02 microprocessor.
However, not all the pins of the 65C02 processor
are accessible for the user outside the chip. One
switch in the control register allows the CPU to be
switched off, so that an external processor can take over
its tasks. This external processor can of course also be
an in-circuit emulator, which makes near-hardware
emulation possible, even though the status and control
lines of the internal CPU are not accessible. If an external
processor is used, all hardware blocks of the chip are
as accessible to it as if it were the internal CPU.
2.4. Clock Generator
An integrated two-pin oscillator generates the clock for
the microcontroller. The frequency created by the oscillator
can be programmed to be reduced with a divider
by the factor 1 ... 255. This enables the user to decrease
the current consumption by the controller by reducing
the working frequency as well as to increase the access
time for the (slower) external memory. This divider contains
the value 4 after a reset, so that the system can also
start with a slow external memory. If the mask-option
OSC is set (EMU version), a switch in the control register
makes it possible to receive the internal clock F2 at
XTAL2. In this case the oscillator must be external and
the clock must be fed to the pin XTAL1. In this way, the
user gets a time reference for internal operations in the
microcomputer. This is especially important with the interrupt
controller. The production version of the CCU
does not have this function!
2.5. PORT 1 to PORT 3, PORT 6 to PORT 8
8 ports belong to the system, of which 5 are 8 bits wide,
one 6 bit, one 4 bit and one 1 bit wide. All port lines of
PORTS 1 to 3 and 6 to 8 can be used as inputs or outputs
independently from each other. One register per port
defines the direction. PORT1 to PORT3 have push-pull
outputs and PORT6 to PORT8 have open drain outputs.
Even a line defined as output can be read, the pin level
being important. This property makes it possible for the
software to find desired and undesired short circuits.
Each port reserves a byte for the direction register and
the data in the I/O page. If the corresponding bit in the
direction register is set to 0, the output mode is switched
on. After a reset, all bits of a direction register are set
to 1. The falling edge of bit 7 of PORT 8 generates interrupts
if the priority of the corresponding interrupt controller
source (7) is not set to 0.
2.6. PORT 4
PORT 4 consists of only one line (LSB, P40). After a reset,
PORT 4 operates as an input only. As soon as PORT
4 is written for the first time, it is switched to output mode
(push-pull). Later read accesses read the actual level at
port 4. If bit 3 in the control word is active, P4 is used as
an R/W-line. If the internal CPU is active, R/W is an output
line, otherwise it is an input. But P4 has another, very
important function during RESET. The level at P4 during
RESET decides whether the control word is read from
the internal ROM (FFF9H) or from the external memory.
It is therefore important that the desired level during RESET
is set at P4. An internal pull-down resistor of approx.
100 kW is integrated in the CCU 3001, which ensures
that the control word is read by the internal ROM. The
external control word access is obtained via an external
pull-up resistor of approx. 5 kW. The CCU 3000 has an
internal pull-up resistor at P4 (external ROM access).
The further mode of operation of the CCU 3000, CCU
3001 depends only on the control word though.
Please note that this mode is always necessary for
the CCU 3000 since this device does not have internal
2.7. I/O-Lines P50 to P55
The 6 additional I/O-lines have a two-fold function:
– input or output line (open drain output) or
– fully decoded I/O-select lines (push-pull outputs)
As a rule these lines can be used as input or output lines.
As soon as ports 1 to 4 are used as system bus, they are
lost as I/O-channels. However, a total of 48 port lines (24
inputs and outputs each) can be reconstructed without
difficulties (1 housing for 8 lines), if the additional 6 I/Olines
of the CCU 3000, CCU 3001 are switched into the
port select mode. They then represent the select lines of
the original ports 1 to 3. Each line can be defined as I/O
or port select line separately. In the I/O-page three bytes
TEA6415C Bus-Controlled Video Matrix Switch
20 MHz Bandwidth
Cascadable with another TEA6415C (Internal
Address can be changed by Pin 7 Voltage)
8 Inputs (CVBS, RGB, Chroma, ...)
Possibility of Chroma Signal for each Input
by switching off the Clamp with an external
6.5 dB Gain between any Input and Output
-55 dB Crosstalk at 5 MHz
Full ESD Protection
The main function of the TEA6415C is to switch 8
video input sources on the 6 outputs.
Each output can be switched to only one of the
inputs, whereas any single input may be connected
to several outputs.
All switching possibilities are controlled through the
Driving a 75 W load requires an external transistor.
The switches configuration is defined by words of 16 bits: one word of 16 bits for each output
So, 6 words of 16 bits are necessary to determine the starting configuration upon power-on (power supply: 0 to 10V). But a new configuration needs only the words of the changed output channels.
Using a Second TEA6415C
The programming input pin (PROG) allows two TEA6415C circuits to operate in parallel and to select them independently through the I²C bus by modifying the address byte. Consequently, the switching capabilities are doubled, or IC1 and IC2 can be cascaded.
TEA6420 BUS-CONTROLLED AUDIO MATRIX SWITCH
5 Stereo Inputs
4 Stereo Ouputs
Gain Control 0/2/4/6dB/Mute for each Output cascadable (2 different addresses) Serial Bus Controlled Very low Noise
Very low Distorsion
DESCRIPTION The TEA6420 switches 5 stereo audio inputs on 4stereo outputs. All the switching possibilities are changed through the I2C bus.
The power Supply is based on TDA4601 (SIEMENS)
Power supply is based on TDA4601d (SIEMENS)
TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.
The invention relates to a blocking oscillator type switching power supply for supplying power to electrical equipment, wherein the primary winding of a transformer, in series with the emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, and a secondary winding of the transformer is provided for supplying power to the electrical equipment, wherein, furthermore, the first bipolar transistor has a base controlled by the output of a control circuit which is acted upon in turn by the rectified a-c line voltage as actual value and by a set-point transmitter, and wherein a starting circuit for further control of the base of the first bipolar transistor is provided.
Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
TDA8175 TV VERTICAL DEFLECTION OUTPUT CIRCUIT:
The TDA8175 is a monolithic integrated circuit in
HEPTAWATT package. It is a high efficiency power
booster for direct driving of vertical windings of TV
yokes. It is intended for use in Color and B & W
television sets as well as in monitors and displays.
.AUTOMATIC PUMPING COMPENSATION
.THERMAL PROTECTION .
Symbol Parameter Value Unit
VS Supply Voltage (PIn 2) 35 V
V5, V6 Flyback Peak Voltage 60 V
V3 Voltage at PIn 3 +VS
V1, V7 Amplifier Input Voltage +VS
IO Output Peak Current (non-repetitive, t = 2ms) 2.5 A
IO Output Peak Current at :
f = 50 or 60Hz, t 3 10ms
f = 50 or 60Hz, t > 10ms
I3 Pin 3 DC Current at V5 < V2 100 mA
I3 Pin 3 Peak-to-peak Flyback Current at f = 50 or 60Hz, tfly 3 1.5ms 3 A
Ptot Total Power Dissipation at Tcase = 70oC 20 W
Tj, Tstg Storage and Junction Temperature -40, +150 oC