JVC AV-32WP2EN CHASSIS MB UNITS VIEW ON MAIN PWB ASS'Y SMB-1901B-U2

JVC  AV-32WP2EN   CHASSIS MB  - DOLBY 3D SOUND UNIT:SMB0D002B-U2 DOLBY PWB ASS'Y

Dolby Surround Multimedia:
The introduction of Dolby Surround Multimedia, Dolby's surround sound system tailored for use with computers, combined with the upcoming release of DVD ROM titles, has generated new levels of interest in Dolby Surround within the computer industry. The first Dolby Surround Multimedia system to use 3-D DSP audio processing to create a surround effect from two speakers was announced in February of this year by Texas Instruments and Victor Company of Japan, Ltd. (JVC). The system uses the Texas Instruments TMS57052 DSP IC which combines a Dolby Pro Logic decoder and JVC's 3D-Phonic technology to create a three dimensional soundfield using just two speakers.













 

SAA7367 Bitstream conversion ADC for digital audio systems
GENERAL DESCRIPTION
The SAA7367 is a CMOS low-cost stereo
Analog-to-Digital Converter (ADC) using the Philips
bitstream conversion technique.

FEATURES
· Total Harmonic Distortion plus Noise
(THD + N) = -88 dB (0.004%); DR = 93 dB;
S/N = 97 dB
· Simple interfacing to analog inputs
· Small, non-critical PCB layout
· Low pin-out SO24 package (pin-compatible to
SAA7366)
· 4 flexible serial interface modes
· 4.5 to 5.5 V operation
· Standby mode
· Detection of digital signal ³-1 dB amplitude
· Up to 18 significant bits serial output
· Selectable high-pass filter.
APPLICATIONS
The device is designed for the digital acquisition of analog
audio signals for digital audio systems such as:
· Compact Disc-Recordable (CD-R)
· Audio digital signal processing systems for hi-fi and
musical instrument applications
· Digital Audio Tape (DAT).

FUNCTIONAL DESCRIPTION
General
The SAA7367 is a bitstream conversion CMOS ADC for
digital audio systems. The conversion is achieved using a
third-order Sigma-Delta Modulator (SDM), running at
128 times the output sample frequency (fs). The high
oversampling ratio greatly simplifies the design of the
analog input anti-alias filter. In most events, the internal
buffer operational amplifier, configured as a low-pass filter,
will suffice. The 1-bit code from the SDM is filtered and
down-sampled (decimated) to 1fs by Finite Impulse
Response (FIR) filters. An optional I2R high-pass filter is
provided to remove DC, if required. The device has been
designed with ease of use, low board area and low
application costs in mind.


Input buffer
Two input buffers are provided, one for each channel, for
signal amplitude matching, signal buffering and anti-alias
filter purposes. These are configured for inverting use.
Access is provided by pins BIL, BIR (inverting inputs) and
BOL, BOR (outputs), for left and right channels
respectively. By the choice of feedback component values,
the application signal amplitude can be matched to the
requirements of the ADC.
Typically, the operational amplifiers are configured as
low-pass filters with a gain of 1 and a pole at
approximately 5fs.
Remark: the complete ADC is non-inverting. Hence, a
positive DC input (referenced to Vref) will yield a positive
digital output.
Input level
The overall system gain is proportional VDDA, or more
accurately the potential difference between the DAC
reference voltages (VVDACP) and (VVDACN). For
convenience, the ADC input signal amplitude is defined as
that amplitude seen on BOL or BOR, the operational
amplifier outputs (i.e. the input to the SDM). Also, the 0 dB
input level is defined as that which gives a -1 dB (actually
-1.12 dB) digital output, relative to full-scale swing. This
reduced gain provides headroom to accommodate small
random DC offsets, without causing the digital output to
clip.
Hence:
The user of the IC should ensure that, when all sources of
signal amplitude variation are taken into account, the
maximum input signal should conform to the 0 dB level.
In the event that the maximum signal level cannot be
pre-determined, e.g. live microphone input, the average
signal level should be set at -10 to -20 dB down. The
exact value will depend on the application and the balance
between headroom and operating Signal-to-Noise Ratio
(SNR).
Behaviour during overload
As previously defined, the maximum input level for normal
operation is 0 dB. If the input level exceeds this value,
clipping may occur. Within the system, excessive
amplitudes are detected after the high-pass filter.
Infringements are limited to the maximum permitted
positive or negative values 217 - 1 or -217 respectively.
VI 0 dB ( )
VVDACP VVDACN – ( )
5 V (RMS)
------------------------------------------------------- =
Input signals in the range 0 to 1 dB may or may not be
clipped, depending on the values of DC dither and small
random offsets in the analog circuitry.
When using the recommended application circuitry,
clipping will initially be observed on negative peaks, due to
the use of negative DC dither.
The maximum level of overload that can be safely
tolerated is application circuit dependent. In the case of the
recommended circuit, the following applies: the inverting
operational amplifier inputs BIL and BIR are protected
from excessive voltages (currents) by diodes to VDDA and
VSSA. These have absolute maximum ratings of
Id = ±20 mA, with a safe practical limit of ±2 mA.
Given the input resistor of 10 kW, ±2 mA diode current and
the operation of the operational amplifier, a maximum
signal (applied to the input resistor) of ±30 V can be
handled safely. This level represents an overload of 26 dB.
During overload, the in-band portion of the waveform will
be correctly converted. The out-of-band portion will be
limited as previously detailed.
Sigma-Delta Modulator (SDM)
The SAA7367 uses two third-order SDMs with a
quantization noise floor of approximately -104 dB. The
scaling of the feedback has been optimized for stable
operation, even during overload. Thus, with a maximum
signal swing of 0 V to VDDA on the input, the digital output
remains well-behaved, i.e. it does not burst into random
oscillation. During overload, the output is simply a clipped
version of the input. The gain of this stage is -4.64 dB.
Decimation filter
Decimation from 128fs is performed in two stages. The first
stage, a comb filter, uses 64 symmetrical coefficients to
implement a 3rd sin x¤x characteristic. This filter decimates
from 128 to 8fs. The second stage, an FIR filter, consists of
three half-band filters, each decimating by a factor of 2.

Serial interface
The serial interface provides 2 formats in master mode
and 4 in slave mode (see Figs 3 and 4). Format 2 is similar
to Philips I2S. In all modes, the interface provides up to
18 significant bits of output data per channel. During
standby mode (STDB = LOW), all interface pins are in
their high impedance state. On recovery from standby, the
serial data output SDO is held LOW until valid data is
available from the decimation filter. This time depends on
whether the high-pass filter is selected:
HPEN = 0; T = 1024/fs, T = 21.3 ms when fs = 48 kHz
HPEN = 1; T = 12288/fs, T = 256.0 ms when
fs = 48 kHz
Overload detection
The OVLD output is used to indicate when the output data,
in either the left or right channel, is greater than -1 dB
(actual figure -1.023 dB) of the maximum possible digital
swing. When this condition is detected, the OVLD output is
forced HIGH for at least 512fs cycles (10.6 ms at
fs = 48 kHz). This time-out is reset for each infringement.




PIP PANEL BOARD P&P PWB ASS'Y SMB0P901B-U2


TA8865BN PLL MULTI PIF / SIF SYSTEM FOR COLOR TV AND VCR
The TA8865BN is a PIF / SIF with PLL detection that is
compatible with the PAL, NTSC and L-SECAM systems.
Intercarrier PLL detection system is adopted to realize high
quality audio in L-SECAM. Use of a 2-stage variable high-gain
SIF AGC amplifier makes possible NICAM compatibility.
The TA8865BN combine these functions in a 36pin dual-in-line
shrink type plastic package.

FEATURES
PIF circuit
• PLL type synchronous detector
• 2-stage variable-gain PIF amplifier
• High-speed AGC with dual time constant
• Keyed AGC with L-SECAM system ; peak AGC with B / G
system
• Keyed APC with L-SECAM system
• Synchronous separation circuit
• Mute output (can be used to distinguish that signal is inputted or not.)
• Adjustment free AFT (bipolar)
• Reverse RF AGC
SIF circuit
• SIF split input
• High-gain SIF AGC amplifier (compatible NICAM system)
• Quadrature-type FM audio detector (for B / G system)
• Direct PLL AM detector (for L-SECAM system)


SAB9077H Picture-In-Picture (PIP) controller
GENERAL DESCRIPTION
The SAB9077H is a picture-in-picture controller for
multi-standard TV-sets. The circuit contains ADCs,
reduction circuitry, memory control, display control and
DACs.
It inserts one or two live video signals with original or
reduced sizes into a live video signal. All video signals are
expected to be analog base band signals. The conversion
into the digital environment and back to the analog
environment is done on chip. Internal clocks are generated
by two acquisition PLLs and a display PLL.
The two PIP channels and a large external memory offer a
wide range of PIP modes. The emphasis is put on single
PIP, double PIP, split-screen mode and many multi-PIP
modes.

FEATURES
Display
· 50/60 Hz PIP modes possible
· Twin PIP in interlaced mode at 8-bit resolution
· Sub-title mode features built in
· Large display fine positioning area, both channels
independent
· Only 2 Mbit needed as external VDRAM
(2 ´ 1 Mbit or 1 ´ 2 Mbit)
· Four 8-bit Analog-to-Digital Converters (ADCs; > 7-bit
performance) with clamp circuit
· Most PIP modes handle interlaced pictures without joint
line error
· Two PLLs which generate the line-locked clocks for the
acquisition channels
· Display PLL to generate line-locked clock for the display
· Three 8-bit Digital-to-Analog Converters (DACs)
· 4 : 1 : 1 data format
· Data reduction factors 1 to 1, 1 to 2, 1 to 3 and 1 to 4,
horizontal and vertical independent.
I2C-bus programmable
· Single and double PIP modes can be set
· Full field still mode available
· Several aspect ratios can be handled
· Reduction factors can be set freely
· Selection of vertical filtering type
· Freeze of live pictures
· Fine tuned display position, H (8-bit), V (8-bit),
both channels independent
· Fine tuned acquisition area, H (4-bit), V (8-bit),
both channels independent
· Eight main borders, sub-borders and background
colours available
· Border and background brightness adjustable, 30%,
50%, 70% and 100% IRE
· Several type of decoder input signals can be set.

FUNCTIONAL DESCRIPTION
Pixel rate
The internal chrominance format used is 4 : 1 : 1. It is
expected that the bandwidth of the input signals is limited
to 4.5 MHz for the Y input and 1.125 MHz for the U/V
inputs.
The Y input is sampled with a 1728 ´ Hsync (»27.0 MHz)
clock and is filtered and down sampled to the internal
864 ´ Hsync (»13.5 MHz) pixel rate.
The U and V inputs are multiplexed and sampled with a
432 ´ Hsync clock and down sampled to the internal
216 ´ Hsync (»3.375 MHz) pixel rate.
Acquisition area
Synchronization is done via the acquisition HSync and
VSync pins. With the acquisition fine positioning added to a
system constant the starting point of the acquisition can be
controlled.
The acquisition area is 672 pixels/line and 228 lines/field
for NTSC and 276 lines/field for PAL. Both main and
sub-channel are equivalent in handling the data.
Display mode
The internal display pixel rate is 864 ´ DPHsync which is
13.5 MHz. This pixel rate is upsampled by interpolation to
1728 ´ DPHsync before the DAC stage.
Display area
The display background is an area of 696 pixels for both
PAL and NTSC, 238 lines for NTSC and 286 lines for PAL.
This can be put on/off by the BGON bit independent of the
PIPON bits. This area can be moved by the display
background fine positioning (BGHFP and BGVFP).
Its colour is determined by the BGCOL and BGBRT bits.
Within this area PIPs are defined dependent on the
PIP mode. The PIP sizes are determined by the display
reduction factors as is shown in Table 2. Whether a PAL or
NTSC fixed number is used is depends on the DPAL bit.
The display fine positioning determines the location of the
PIPs with respect to the background. sub and
main-channel both have their independent PIP size and
location control.

PIP modes
The two independent acquisition channels can also be
controlled independently on the display side. A wide
variety of modes is possible but a subset of 7 modes is
fixed and can be set easily by the I2C-bus. An overview of
the preconditioned modes is given in Table 3. For all PIP
modes the main and sub-display fine positioning must be
set to obtain a display configuration.
DATA TRANSFER
The internal data path has an 8-bit resolution and 4 : 1 : 1
data format. The communication to the external VDRAM
takes place at 864 ´ Hsync (both display and acquisition).
Approximately 800 8-bit words can be fetched from the
external VDRAM in one display line which is not enough to
display one complete display line with true 8-bit resolution.
Two methods of reducing data are available. One is simply
skipping the 8-bit to 6-bit (SKIP6, I2C-bus bit) and the other
is a small form of data reduction to come from 8-bit to 6-bit
(SMART6, I2C-bus bit). If both bits are set to logic 0 the
device is in true 8-bit resolution mode. For the twin PIP
mode the main channel is not placed in the VDRAM but in
an internal buffer, 8 bit resolution is then possible for both
PIPs.

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AUTO ASPECT UNIT WITH JCC5035 ASIC OF JVC.


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TDA9141 PAL/NTSC/SECAM decoder/sync processor

GENERAL DESCRIPTION
The TDA9141 is an I2C-bus controlled, alignment-free
PAL/NTSC/SECAM decoder/sync processor. The
TDA9141 has been designed for use with baseband
chrominance delay lines, and has a combined subcarrier
frequency/comb filter enable signal for communication
with a PAL comb filter.
The IC can process CVBS signals and Y/C input signals.
The input signal is available on an output pin, in the event
of a Y/C signal, it is added into a CVBS signal.
The sync processor provides a two-level sandcastle, a
horizontal pulse (CLP or HA pulse, bus selectable) and a
vertical (VA) pulse. When the HA pulse is selected a
line-locked clock (LLC) signal is available at the output port
pin.
A fast switch can select either the internal Y signal with the
UV input signals, or YUV signals made of the RGB input
signals. The RGB input signals can be clamped with either
the internal or an external clamping signal (search tuning
mode).
Two pins with an input/output port and an output port of the
I2C-bus are available.
The I2C-bus address of the TDA9141 is hardware
programmable.

FEATURES
· Multistandard PAL, NTSC and SECAM
· I2C-bus controlled
· I2C-bus addresses can be selected by hardware
· Alignment free
· Few external components
· Designed for use with baseband delay lines
· Integrated video filters
· CVBS or YC input with automatic detection
· CVBS output
· Vertical divider system
· Two-level sandcastle signal
· VA synchronization pulse (3-state)
· HA synchronization pulse or clamping pulse CLP
input/output
· Line-locked clock output or stand-alone I2C-bus output
port
· Stand-alone I2C-bus input/output port
· Colour matrix and fast YUV switch
· Comb filter enable input/output with subcarrier
frequency.

FUNCTIONAL DESCRIPTION
General
The TDA9141 is an I2C-bus
controlled, alignment-free
PAL/NTSC/SECAM colour
decoder/sync processor which has
been designed for use with baseband
chrominance delay lines.
In the standard operating mode the
I2C-bus address is 8A. If the address
input is connected to the positive rail
the address will change to 8E.
Input switch
WARNING: THE VOLTAGE ON THE
CHROMINANCE PIN MUST NEVER
EXCEED 5.5 V. IF IT DOES THE IC
ENTERS A TEST MODE.
The TDA9141 has a two pin input for
CVBS or YC signals which can be
selected via the I2C-bus. The input
selector also has a position in which it
automatically detects whether a
CVBS or YC signal is on the input. In
this input selector position, standard
identification first takes place on an
added Y/CVBS and C input signal.
After that, both chrominance signal
input amplitudes are checked once
and the input with the strongest
chrominance burst signal is selected.
The input switch status is read out by
the I2C-bus via output bit YC.
CVBS output
In the standard operating mode with
the I2C-bus address 8A, a CVBS
output signal is available on the
address pin, which represents either
the CVBS input signal or the Y/C input
signal, added into a CVBS signal
RGB colour matrix
WARNING: THE VOLTAGE ON THE UIN
PIN MUST NEVER EXCEED 5.5 V. IF IT
DOES THE IC ENTERS A TEST MODE.
The TDA9141 has a colour matrix to
convert RGB input signals into YUV
signals. A fast switch, controlled by
the signal on pin F and enabled by the
I2C-bus via EFS (enable fast switch),
can select between these YUV
signals and the YUV signals of the
decoder. The Y signal is internally
connected to the switch. The -(R-Y)
and -(B-Y) output signals of the
decoder have to first be delayed in
external baseband chrominance
delay lines. The outputs of the delay
lines must be connected to the UV
input pins. If the RGB signals are not
synchronous with the selected
decoder input signal, clamping of the
RGB input signals is possible by
I2C-bus selection of STM (search
tuning mode), EFS and by feeding an
external clamping signal to the CLP
pin.
Also in search tuning mode the VA
output will be in a high impedance
OFF-state.
Standard identification
The standards which the TDA9141
can decode are dependent on the
choice of external crystals. If a
4.4 MHz and a 3.6 MHz crystal are
used then SECAM, PAL 4.4/3.6 and
NTSC 4.4/3.6 can be decoded. If two
3.6 MHz crystals are used then only
PAL 3.6 and NTSC 3.6 can be
decoded. Which 3.6 MHz standards
can be decoded is dependent on the
exact frequencies of the 3.6 MHz
crystals. In an application where not
all standards are required only one
crystal is sufficient (in this instance
the crystal must be connected to the
reference crystal input (pin 30)). If a
4.4 MHz crystal is used it must always
be connected to pin 30. Both crystals
are used to provide a reference for
the filters and the horizontal PLL,
however, only the reference crystal is
used to provide a reference for the
SECAM demodulator.
To enable the calibrating circuits to be
adjusted exactly two bits from I2C-bus
subaddress 00 are used to indicate
which crystals are connected to the
IC.
The standard identification circuit is a
digital circuit without external
components; the search loop is
illustrated in Fig.3.
The decoder (via the I2C-bus) can be
forced to decode either SECAM or
PAL/NTSC (but not PAL or NTSC).
Crystal selection can also be forced.
Information concerning which
standard and which crystal have been
selected and whether the colour killer
is ON or OFF is provided by the read
out. Using the forced-mode does not
affect the search loop, it does,
however, prevent the decoder from
reaching or staying in an unwanted
state. The identification circuit skips
impossible standards (e.g. SECAM
when no 4.4 MHz crystal is fitted) and
illegal standards (e.g. is forced
mode). To reduce the risk of wrong
identification PAL has priority over
SECAM (only line identification is
used for SECAM).
Integrated filters
All filters, including the luminance
delay line, are an integral part of the
IC. The filters are gyrator-capacitor
type filters. The resonant frequency of
the filters is controlled by a circuit that
uses the active crystal to tune the
SECAM Cloche filter during the
vertical flyback time. The remaining
filters and the luminance delay line
are matched to this filter. The filters
can be switched to either 4.43 MHz,
4.28 MHz or 3.58 MHz irrespective of
the frequency of the active crystal.
The switching is controlled by the
identification circuit.
In YC mode the chrominance notch
filter is bypassed, to preserve full
signal bandwidth.
For a CVBS signal the chrominance
notch filter can be bypassed by
I2C-bus selection of TB (trap bypass).
The luminance delay line delivers the
Y signal to the output 60 ns after the
-(R-Y) and -(B-Y) signals have
arrived at their outputs.

This compensates for the delay of the
external chrominance delay lines.
Colour decoder
The PAL/NTSC demodulator
employs an oscillator that can operate
with either crystal (3.6 or 4.4 MHz). If
the I2C-bus indicates that only one
crystal is connected it will always
connect to the crystal on the
reference crystal input (pin 30).
The Hue signal, which is adjustable
via the I2C-bus, is gated during the
burst for NTSC signals.
The SECAM demodulator is an
auto-calibrating PLL demodulator
which has two references. The
reference crystal, to force the PLL to
the desired free-running frequency
and the bandgap reference, to obtain
the correct absolute value of the
output signal. The VCO of the PLL is
calibrated during each vertical
blanking period, when the IC is in
search mode or SECAM mode. If the
reference crystal is not 4.4 MHz the
decoder will not produce the correct
SECAM signals.
The frequency of the active crystal is
fed to the Fscomb output, which can
be connected to an external comb
filter IC. The DC value on this pin
contains the comb enable
information. Comb enable is true
when bus bit ECMB is HIGH. If ECMB
is LOW, the subcarrier frequency is
suppressed. The external comb filter
can force the DC value of Fscomb
LOW, as pin Fscomb also acts as
input pin. In this event the subcarrier
frequency is still present. If the DC
value of Fscomb is HIGH, the input
switch is always forced in Y/C mode,
indicated by bus bit YC.
Sync processor (j1 loop)
The main part of the sync circuit is a
432 ´ fH (6.75 MHz) oscillator the
frequency of which is divided by 432
to lock the Phase 1 loop to the
incoming signal. The time constant of
the loop can be forced by the I2C-bus
(fast or slow). If required the IC can
select the time constant, depending
on the noise content of the input
signal and whether the loop is
phase-locked or not (medium or
slow). The free-running frequency of
the oscillator is determined by a
digital control circuit that is locked to
the active crystal.
When a power-on-reset pulse is
detected the frequency of the
oscillator is switched to a frequency
greater than 6.75 MHz to protect the
horizontal output transistor. The
oscillator frequency is reset to
6.75 MHz when the crystal indication
bits have been loaded into the IC. To
ensure that this procedure does not
fail it is absolutely necessary to send
subaddress 00 before subaddress
01. Subaddress 00 contains the
crystal indication bits and when
subaddress 01 is received the line
oscillator calibration will be initiated
(for the start-up procedure after
power-on reset detection see the
I2C-bus protocol. The calibration is
terminated when the oscillator
frequency reaches 6.75 MHz. The
oscillator is again calibrated when an
out-of-lock condition with the input
signal is detected by the coincidence
detector. Again the calibration will be
terminated when the oscillator
frequency reaches 6.75 MHz.
The Phase 1 loop can be opened
using the I2C-bus. This is to facilitate
On Screen Display (OSD)
information. If there is no input signal
or a very noisy input signal the phase
1 loop can be opened to provide a
stable line frequency and thus a
stable picture.
The sync part also delivers a
two-level sandcastle signal, which
provides a combined horizontal and
vertical blanking signal and a
clamping pulse for the display section
of the TV.
Vertical divider system
The vertical divider system has a fully
integrated vertical sync separator.
The divider can accommodate both
50 and 60 Hz systems; it can either
locate the field frequency
automatically or it can be forced to the
desired system via the I2C-bus. A
block diagram of the vertical divider
system is illustrated in Fig.4. The
divider system operates at twice the
horizontal line frequency. The line
counter receives enable pulses at this
line frequency, thereby counting two
pulses per line.
A state diagram of the controller is
illustrated in Fig.5. Because it is
symmetrical only the right hand part
will be described.
Depending on the previously found
field frequency, the controller will be
in one of the COUNT states. When
the line counter has counted 488
pulses (i.e. 244 lines of the video
input signal) the controller will move
to the next state depending on the
output of the norm counter. This can
be either NORM, NEAR_NORM or
NO_NORM depending on the
position of the vertical sync pulse in
the previous fields. When the
controller is in the NORM state it
generates the vertical sync pulse
(VSP) automatically and then, when
the line counter is at LC = 626,
moves to the WAIT state. In this
condition it waits for the next pulse of
the double line frequency signal and
then moves to the COUNT state of
the current field frequency. When the
controller returns to the COUNT state
the line counter will be reset half a line
after the start of the vertical sync
pulse of the video input signal.