JVC AV-32WP2EN CHASSIS MB SIGNAL PROCESSING BOARD MAIN PWB ASS'Y SMB-1901B-U2 OVERVIEW.

M37207EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER



DESCRIPTION The M37207MF-XXXSP/FP and M37207M8-XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. It is housed in a 64-pin shrink plastic molded DIP or a 80-pin plastic molded QFP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy programming. The M37207MF-XXXSP/FP has a PWM function and an OSD function, so it is useful for a channel selection system for TV. The features of the M37207EFSP/FP are similar to those of the M37207MFXXXSP/ FP except that these chips have a built-in PROM which can be written electrically. The difference between M37207MF-XXXSP/ FP and M37207M8-XXXSP are the ROM size, RAM size, ROM size for display and kinds of character. Accordingly, the following descriptions will be for the M37207MF-XXXSP/FP unless otherwise noted.

FEATURES
• Number of basic instructions .................................................... 71
• Memory size .................................................................................
ROM ...................... 32K bytes (M37207M8-XXXSP)
62K bytes (M37207MF-XXXSP/FP,
M37207EFSP/FP)
RAM ...................... 512 bytes (M37207M8-XXXSP)
960 bytes (M37207MF-XXXSP/FP,
M37207EFSP/FP)
ROM correction memory ............................ 64 bytes
ROM for display....... 8K bytes (M37207M8-XXXSP)
12K bytes (M37207MF-XXXSP/FP,
M37207EFSP/FP)
RAM for display ........................................ 144 bytes
• Minimum instruction execution time
........................................ 0.5 µs (at 8 MHz oscillation frequency)
• Power source voltage .................................................. 5 V ± 10 %
• Subroutine nesting ............................................ 128 levels (Max.)
• Interrupts ...................................................... 15 types, 14 vectors
• 8-bit timers ................................................................................. 6
• Programmable I/O ports
(Ports P0, P1, P2, P30–P36, P4, P6) ....................................... 47
• Input ports (Ports P70, P71) ....................................................... 2
• Output ports (Ports P52–P56) ..................................................... 5
• 12 V withstand ports ................................................................. 10
• LED drive ports .......................................................................... 4
• Serial I/O ....................................... 8-bit 5 1 channel (2 systems)

• Multi-master I2C-BUS interface ............................... 1 (3 systems)
• Power dissipation
In high-speed mode ........................................................ 165 mW
(at VCC = 5.5 V, 8 MHz oscillation frequency, CRT on)
In low-speed mode ......................................................... 0.33 mW
(at VCC = 5.5 V, 32 kHz oscillation frequency)
• A-D comparator (6-bit resolution) ................................ 8 channels
• PWM output circuit ...................................... 14-bit 5 1, 8-bit 5 10
• Interrupt interval determination circuit ........................................ 1
• ROM correction function .......................................... 32 bytes 5 2
• CRT display function
Number of display characters ............... 24 characters 5 3 lines
(16 lines maximum)
Kinds of characters .................. 256 kinds (M37207M8-XXXSP)
384 kinds (M37207MF-XXXSP/FP,
M37207EFSP/FP)
Character display area .......................................... 12 5 16 dots
Kinds of character sizes ................................................. 4 kinds
Kinds of character colors (It can be specified by the character)
maximum 15 kinds (R, G, B, I)
Kinds of character background colors (It can be specified by the character)
maximum 7 kinds (R, G, B)
1/2-character unit color specification is possible.
Kinds of raster colors (maximum 15 kinds)
Display position
Horizontal .................................................................. 64 levels
Vertical .................................................................... 128 levels
Bordering (horizontal and vertical)
Wipe function
Scanning line double count mode display is possible.


FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used. MEMORY Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for storing user programs as well as the interrupt vector area. RAM for Display RAM for display is used for specifying the character codes and colors to display. ROM for Display ROM for display is used for storing character data. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 4. Memory Map ROM Correction Memory (RAM) This is used as the program area for ROM correction.

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SDA 30C163-3 8-Bit Microcontroller ROMLESS


Features l SAB 8051 Architecture – On-chip oscillator and clock circuits – Binary or decimal arithmetic – Signed-overflow detection and parity computation – Integrated Boolean processor for control applications – Full depth stack for subroutine return linkage and data storage – Two priority level, nested interrupt structure – 16-MHz oscillator frequency, 0.75 ms instruction cycle – 8 data pointer registers l Serial Interface – Full duplex UART-interface l On-Chip RAM – Direct byte and bit addressability – Four register banks – 256 bytes of data memory, including 128 user-defined software flags – 1024 bytes of data memory accessible with MOVX-instructions l External Program Memory Interface – 512 Kbytes of program memory may be addressed by a 8-bit data bus and a 16 + 3-bit address bus – Extension stack depth 32 byte. 34 Bidirectional I/O-Lines – Two 8-bit ports, one comprising up to eight programmable D/A-outputs – One 8-bit multifunction port – One 8-bit port with open drain output – One 2-bit port with optional memory extension function l Pulse Width Modulation Unit – Up to eight programmable PWM-output channels for low cost digital-to-analog conversion l Timers – Two 16-bit general purpose timers/event counters – Watchdog timer l Analog-to-Digital Converter – Four multiplexed input channels to 8-bit resolution. Functional Description 2.1 Architecture The CPU manipulates operands in three memory spaces. These are the program memory (512 Kbyte) and (256 + 1024) byte internal data memory spaces. The program memory address space is provided to accommodate relocatable code. The internal data memory address space is further divided into the 256-byte internal data RAM, 1024 bytes XRAM and the 128-byte Special Function Register (SFR) address spaces. Four register banks (each bank has eight registers),128 addressable bits, and the stack reside in the internal data RAM. The stack depth is limited only by the available internal data RAM. Its location is determined by the 8-bit stack pointer. All registers except the program counter and the four 8-register banks reside in the special function register address space. These memory mapped registers include arithmetic registers, pointers, I/O-ports, registers for the interrupt system, timers, pulse width modulator and serial channel. Many locations in the SFR-address space are addressable as bits. Note that reading from unused locations in internal data memory will yield undefined data. Conditional branches are performed relative to the program counter. The register-indirect jump permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. Sixteen-bit jumps and calls permit branching to any location within one 64 K block of the 512 K program memory address space. There are five methods for addressing source operands: register, direct, register-indirect, immediate, and base-register plus index-register indirect addressing. The first three methods can be used for addressing destination operands. Most instructions have a “destination, source” field that specifies the data type, addressing methods and operands involved. For operations other than moves, the destination operand is also a source operand. Registers in the four 8-register banks can be accessed through register, direct, or register-indirect addressing; the lower 128 bytes of internal data RAM through direct or register-indirect addressing, the upper 128 bytes of internal data RAM through register-indirect addressing; and the special function registers through direct addressing. Look-up tables resident in program memory can be accessed through base-register plus index-register indirect addressing. 2.1.1 CPU-Hardware Instruction Decoder Each program instruction is decoded by the instruction decoder. This unit generates the internal signals that control the functions of each unit within the CPU-section. These signals control the sources and destination of data, as well as the function of the Arithmetic/Logic Unit (ALU). Program Control Section The program control section controls the sequence in which the instructions stored in program memory are executed. The conditional branch logic enables conditions internal and external to the processor to cause a change in the sequence of program execution. The 16-bit program counter holds the address of the instruction to be executed.
Internal Data RAM
The internal data RAM provides a 256-byte scratch pad memory, which includes four register banks
and 128 direct addressable software flags. Each register bank contains registers R0 – R7. The
addressable flags are located in the 16-byte locations starting at byte address 32 and ending with
byte location 47 of the RAM-address space.
In addition to this standard internal data RAM the processor contains additional 1024 bytes internal
RAM. It can be considered as a part of an external data memory. It is located at addresses 63488
to 64511 of the external data memory address space and is referenced by MOVX-instructions
(MOVX A, @DPTR).
Arithmetic/Logic Unit (ALU)
The arithmetic section of the processor performs many data manipulation functions and includes
the Arithmetic/Logic Unit (ALU) and the A, B and PSW-registers. The ALU accepts 8-bit data words
from one or two sources and generates an 8-bit result under the control of the instruction decoder.
The ALU performs the arithmetic operations of add, subtract, multiply, divide, increment,
decrement, BCD-decimal-add-adjust and compare, and the logic operations of and, or, exclusiveor,
complement and rotate (right, left, or nibble swap).
The A-register is the accumulator, the B-register is dedicated during multiply and divide and serves
as both a source and a destination. During all other operations the B-register is simply another
location of the special function register space and may be used for any purpose.
Boolean Processor
The Boolean processor is an integral part of the processor architecture. It is an independent bit
processor with its own instruction set, its own accumulator (the carry flag) and its own bitaddressable
RAM and l/O. The bit manipulation instructions allow the direct addressing of 128 bits
within the internal data RAM and several bits within the special function registers. The special
function registers which have addresses exactly divisible by eight contain directly addressable bits.
The Boolean processor can perform, on any addressable bit, the bit operations of set, clear,
complement, jump-if-set, jump-if-not-set, jump-if-set then-clear and move to/from carry. Between
any addressable bit (or its complement) and the carry flag it can perform the bit operation of logical
AND or logical OR with the result returned to the carry flag.

Program Status Word Register (PSW)
The PSW-flags record processor status information and control the operation of the processor. The
carry (CY), auxiliary carry (AC), two user flags (F0 and F1), register bank select (RS0 and RS1),
overflow (OV) and parity (P) flags reside in the program status word register. These flags are bitmemory-
mapped within the byte-memory-mapped PSW. The CY, AC, and OV flags generally
reflect the status of the latest arithmetic operations. The CY-flag is also the Boolean accumulator for
bit operations. The P-flag always reflects the parity of the A-register. F0 and F1 are general purpose
flags which are pushed onto the stack as part of a PSW-save.

Stack Pointer (SP)
The 8-bit stack pointer contains the address at which the last byte was pushed onto the stack. This
is also the address of the next byte that will be popped. The SP is incremented during a push. SP
can be read or written to under software control. The stack may be located anywhere within the
internal data RAM address space and may be as large as 256 bytes.
Data Pointer Register (DPTR)
The 16-bit Data Pointer Register DPTR is the concatenation of registers DPH (high-order byte) and
DPL (low-order byte). The DPTR is used in register-indirect addressing to move program memory
constants and to access the extended data memory. DPTR may be manipulated as one 16-bit
register or as two independent 8-bit registers DPL and DPH.
Eight data pointer registers are available, the active one is selected by a special function register
(DPSEL).

Port 0, Port 1, Port 2, Port 3, Port 4
The five ports provide 34 I/O-lines to interface to the external world. All five ports are both byte and
bit addressable. Port 0 and port 2.4 – 2.7 are used for binary l/O only. Port 1 provides eight PWMoutput
channels as alternate functions while port 2.0 – 2.3 are digital or analog inputs. Port 3
contains special control signals. Port 4 will usually be selected as memory extension interface.
Interrupt Logic
Controlled by two special function registers (IE, IP) the interrupt logic provides several interrupt
vectors. Each of them may be assigned to high or low priority (see chapter “Interrupt System”).
Timer/Counter 0/1
Two general purpose 16-bit timers/counters are controlled by the special function registers TMOD
and TCON (see chapter “General Purpose Timers/Counters”).
Serial Interface
A full duplex serial interface is provided where one of three operation modes may be selected. The
serial interface is controlled by two special function registers (SCON, SBUF) as described in
chapter “Serial Interface”.
Watchdog Timer
For software- and hardware security, a watchdog timer is supplied, which resets the processor, if
not cleared by software within a maximum time period.
Pulse Width Modulation Unit
Up to eight lines of port 1 may be used as PWM-outputs. The PWM-logic is controlled by registers
PWME, PWMC, PWCOUNT, PWCOMP0 … 7 (see chapter “Pulse Width Modulation Unit”).
2.1.2 CPU-Timing
Timing generation is completely self-contained, except for the frequency reference which can be a
crystal or external clock source. The on-board oscillator is a parallel anti-resonant circuit with a
frequency range of 1.2 MHz to 16 MHz. There is a divide-by-12 internal timing which leads to a minimum
instruction cycle of 0.75 ms with a 16-MHz crystal. The XTAL2-pin is the output of a high-gain
amplifier, while XTAL1 is its input. A crystal connected between XTAL1 and XTAL2 provides the
feedback and phase shift required for oscillation. The 1.2 MHz to 16-MHz range is also
accommodated when an external clock is applied to XTAL1 as the frequency source.
A machine cycle consists of 12 oscillator periods. Most instructions execute in one cycle. MUL
(multiply) and DIV (divide) are the only instructions that take more than two cycles to complete. They
take four cycles.
Normally, two code bytes are fetched from program memory during every machine cycle. The only
exception to this is when a MOVX-instruction is executed. MOVX is a 1-byte 2-cycle instruction that
accesses XRAM. During a MOVX, two fetches are skipped while the internal XRAM is being
addressed.

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MEGATEXT PLUS SDA 5275-2


MEGATEXT PLUS (SDA 5275-2) has been developed based on the original Megatext
(SDA 5273). To make it easy for the user to recognize the differences between these two
versions, this delta specification is provided. It is assumed that the reader of this
document is familiar with the documentation of the SDA 5273 (“Volume 1”).
MEGATEXT PLUS is completely hardware compatible to the SDA 5273. However its
internal processing has been changed to enable reception of all level 2.5 related data
with only little external software support.
MEGATEXT PLUS is able to request, acquire and display HiText (teletext level 2.5)
pages automatically in real-time. The firmware processes objects, DRCS-characters,
parallel attributes, CLUT and sidepanel information for 16:9 applications.
The only remaining task for the user is to reserve enough external memory space for
higher level pages like MOTs, POPs, DRCS-pages and related pseudopackets. For
Level 2.5 transmission this number of additional pages should not exceed more than 500
packets. So the user should reserve appropriate memory for MOTs, POPs and DRCS -
pages (refer to [3]). Because some part of high level information is transmitted in
pseudopackets X/25, X/26, X/27, X/28 and X/29, enough memory should also be
reserved in the P40 and P80 chains.
The Serial/Parallel Conversion (S/P-C) is able to handle all teletext level 2.5 features
which are described in the “World Standard Teletext Norm”. For the evaluation of all
information stored in packets X/25, X/26, X/27, X/28, X/29 and in the linked pseudo
pages, the S/P-C needs additional temporary memory space in the external memory, the
so-called hidden display memory.
The S/P-C first builds up a temporary page in the hidden display memory and than
copies it into block 2 and block 3 of the internal DRAM of the MEGATEXT PLUS. So all
10 KBytes of the display memory are used by the S/P-C.
Because it is necessary to store a lot of additional information, MEGATEXT PLUS is
only working with external RAM.
From the point of view of the user, the following changes have been made compared to
the SDA 5273.
– CLUT of display generator
– Number and addressing of DRCS characters
– Megatext Command Interface (MCI)
– WSS support


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MSP 3410D Multistandard Sound Processor


Introduction The MSP 3410D is designed as a single-chip Multistandard Sound Processor for applications in analog and digital TV sets, satellite receivers, video recorders, and PC-cards. As the successor of the MSP 3410B and MSP 3400C, the MSP 3410D combines all features of the two and adds several new features. The MSP 3410D, again, improves function integration: The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed in a single chip. It covers all European TVStandards (some examples are shown in Table 3–1). The MSP 3400 1.0 m CMOS version is fully pin and software compatible to the MSP 3410, but is not able to decode NICAM. It is also compatible to the MSP 3400C 0.8 m CMOS version. The IC is produced in submicron CMOS technology, combined with high performance digital signal processing. The MSP 3410D is available in a PLCC68, PSDIP64, PSDIP52, and in a PQFP80 package. Note: The MSP3410D version is fully downward compatible to the MSP 3410B, the MSP 3400B, and the MSP 3400C. To achieve full software compatibility with MSP 3400C, MSP 3400B, and MSP 3410B, the demodulator part must be programmed as described in the data sheet of MSP 3410B. 1.1. MSP 3410D Additional Features and Major Improvements compared with MSP 3410B (section 8.) – AVC: Automatic Volume Correction – Subwoofer Output – 5-band graphic equalizer (as in MSP 3400C) – Enhanced spatial effect (pseudostereo/basewidth enlargement as in MSP 3400C) – headphone channel with balance, bass, treble, loudness – balance for loudspeaker and headphone channels in dB units (optional) – Additional pair of D/A converters for SCART2 out – improved oversampling filters (as in MSP 3400C) – Additional SCART input – Full SCART in/out matrix without restrictions – Scart volume in dB units (optional) – Additional I2S input (as in MSP 3400C) – New FM-identification (as in MSP 3400C) – Demodulator short programming – Autodetection for terrestrial TV-sound standards – Precise bit-error rate indication – Automatic switching from NICAM to FM/AM or vice versa – Improved NICAM synchronization algorithm – Improved carrier mute algorithm – Improved AM-demodulation – ADR together with DRP 3510A – Dolby Pro Logic together with DPL 35xx A – Reduction of necessary controlling – Less external components – Significant reduction of radiation.
Basic Features of the MSP 3410D 2.1. Demodulator and NICAM Decoder Section The MSP 3410D is designed to simultaneously perform digital demodulation and decoding of NICAM-coded TV stereo sound, as well as demodulation of FM or AMmono TV sound. Alternatively, two carrier FM systems according to the German or Korean terrestrial specs or the satellite specs can be processed with the MSP 3410D. The MSP offers a powerful feature to calculate the carrier field strength, which can be used for automatic standard detection (terrestrial) and search algorithms (satellite). Therefore, the IC facilitates a first step towards multistandard capability. It may be used in TV-sets, as well as in satellite tuners, and video recorders. The MSP 3410D facilitates profitable multistandard capability, offering the following advantages: – two selectable analog inputs (TV and SAT-IF sources) – Automatic Gain Control (AGC) for analog input: input range: 0.10 – 3 Vpp – integrated A/D converter for sound-IF inputs – all demodulation and filtering is performed on chip and is individually programmable – easy realization of all digital NICAM standards (B/G, I, L, and D/K) – FM-demodulation of all terrestrial standards (incl. identification decoding) – FM-demodulation of all satellite standards – no external filter hardware is required – only one crystal clock (18.432 MHz) is necessary – FM carrier level calculation for automatic search algorithms and carrier mute function – high deviation FM-mono mode (max. deviation:approx. ±360 kHz)

DSP-Section (Audio Baseband Processing)
– flexible selection of audio sources to be processed
– two digital input and one output interface via I2S-Bus
for external DSP-processors, featuring surround
sound, ADR etc.
– digital interface to process ADR (Astra Digital Radio)
together with DRP 3510A
– performance of all deemphasis systems including
adaptive Wegener Panda 1 without external components
or controlling
– digitally performed FM-identification decoding and dematrixing
– digital baseband processing: volume, bass, treble,
5-band equalizer, loudness, pseudostereo, and basewidth
enlargement
– simple controlling of volume, bass, treble, equalizer
etc.
2.3. Analog Section
– four selectable analog pairs of audio baseband inputs
(= four SCART inputs)
input level: 32 V RMS,
input impedance: .25 kW
– one selectable analog mono input (i.e. AM sound):
input level: 32 V RMS,
input impedance: .15 kW
– two high-quality A/D converters, S/N-Ratio: .85 dB
– 20 Hz to 20 kHz bandwidth for SCART-to-SCARTcopy
facilities
– MAIN (loudspeaker) and AUX (headphones): two
pairs of fourfold oversampled D/A-converters
output level per channel: max. 1.4 VRMS
output resistance: max. 5 kW
S/N-ratio: .85 dB at maximum volume
max. noise voltage in mute mode: 310 mV
(BW: 20 Hz ...16 kHz)
– two pairs of four-fold oversampled D/A converters
supplying two selectable pairs of SCART-outputs.
output level per channel: max. 2 V RMS,
output resistance: max. 0.5 kW,
S/N-Ratio: .85 dB (20 Hz...16 kHz)

3. Application Fields of the MSP 3410D
In the following sections, a brief overview about the two
main TV sound standards, NICAM 728 and German FMStereo,
demonstrates the complex requirements of a
multistandard audio IC.
3.1. NICAM plus FM/AM-Mono
According to the British, Scandinavian, Spanish, and
French TV-standards, high-quality stereo sound is
transmitted digitally. The systems allow two high-quality
digital sound channels to be added to the already existing
FM/AM-channel. The sound coding follows the format
of the so-called Near Instantaneous Companding
System (NICAM 728). Transmission is performed using
Differential Quadrature Phase Shift Keying (DQPSK).
Table 3–2 gives some specifications of the sound coding
(NICAM); Table 3–3 offers an overview of the modulation
parameters.
In the case of NICAM/FM (AM) mode, there are three different
audio channels available: NICAM A, NICAM B,
and FM/AM-mono. NICAM A and B may belong either to
a stereo or to a dual language transmission. Information
about operation mode and about the quality of the NICAM
signal can be read by the CCU via the control bus.
In the case of low quality (high bit error rate), the CCU
may decide to switch to the analog FM/AM-mono sound.
Alternatively, an automatic NICAM-FM/AM switching
may be applied.
3.2. German 2-Carrier System (DUAL FM System)
Since September 1981, stereo and dual sound programs
have been transmitted in Germany using the
2-carrier system. Sound transmission consists of the already
existing first sound carrier and a second sound
carrier additionally containing an identification signal.
More details of this standard are given in Tables 3–1 and
3–4. For D/K and M-Korea, very similar systems are used.

4. Architecture of the MSP 3410D
Fig. 4–1 shows a simplified block diagram of the IC. Its
architecture is split into three main functional blocks:
1. demodulator and NICAM decoder section
2. digital signal processing (DSP) section performing
audio baseband processing
3. analog section containing two A/D-converters, 9 D/Aconverters,
and SCART Switching Facilities.
4.1. Demodulator and NICAM Decoder Section
4.1.1. Analog Sound IF – Input Section
The input pins ANA_IN1+, ANA_IN2+, and ANA_IN– offer
the possibility to connect two different sound IF (SIF)
sources to the MSP 3410D. By means of bit [8] of
AD_CV (see Table 6–5), either terrestrial or satellite
sound IF signals can be selected. The analog-to-digital
conversion of the preselected sound IF signal is done by
an A/D-converter, whose output can be used to control
an analog automatic gain circuit (AGC), providing an optimal
level for a wide range of input levels. It is possible
to switch between automatic gain control and a fixed
(setable) input gain. In the optimal case, the input range
of the A/D converter is completely covered by the sound
IF source. Some combinations of SAW filters and sound
IF mixer ICs, however, show large picture components
on their outputs. In this case, filtering is recommended.
It was found, that the high pass filters formed by the coupling
capacitors at pins ANA_IN1+ and ANA_IN2+ (as
shown in the application diagram) are sufficient in most
cases.
Quadrature Mixers The digital input coming from the integrated A/D converter may contain audio information at a frequency range of theoretically 0 to 9 MHz corresponding to the selected standards. By means of two programmable quadrature mixers, two different audio sources; for example, NICAM and FM-mono, may be shifted into baseband position. In the following, the two main channels are provided to process either: – NICAM (MSP-Ch1) and FM/AM mono (MSP-Ch2) simultaneously or, alternatively, – FM mono (channel 2) – FM2 (MSP-Ch1) and FM1 (MSP-Ch2). Two programmable registers, to be divided up into Low and High Part, determine frequency of the oscillator, which corresponds to the frequency of the desired audio carrier. 4.1.3. Lowpass Filtering Block for Mixed Sound IF Signals Data shaping and/or FM bandwidth limitation is performed by a linear phase Finite Impulse Response (FIRfilter). Just like the oscillators’ frequency, the filter coefficients are programmable and are written into the IC by the CCU via the control bus. Thus, for example, different NICAM versions can easily be implemented. Two not necessarily different sets of coefficients are required, one for MSP-Ch1 (NICAM or FM2) and one for MSPCh2 (FM1 = FM-mono).
Phase and AM Discrimination The filtered sound IF signals are demodulated by means of the phase and amplitude discriminator block. On the output, the phase and amplitude is available for further processing. AM signals are derived from the amplitude information, whereas the phase information serves for FM and NICAM (DQPSK) demodulation. 4.1.5. Differentiators FM demodulation is completed by differentiating the phase information output. 4.1.6. Lowpass Filter Block for Demodulated Signals The demodulated FM and AM signals are further lowpass filtered and decimated to a final sampling frequency of 32 kHz. The usable bandwidth of the final baseband signals is about 15 kHz. 4.1.7. High Deviation FM Mode By means of MODE_REG [9], the maximum FM-deviation can be extended to approximately ±360 kHz. Since this mode can be applied only for the MSP sound IF channel 2, the corresponding matrices in the baseband processing must be set to sound A. Apart from this, the coefficient sets 380 kHz FIR2 or 500 kHz FIR2 must be chosen for the FIR2. In relation to the normal FM-mode, the audio level of the high-deviation mode is reduced by 6 dB. The FM-prescaler should be adjusted accordingly. In high deviation FM-mode, neither FM-stereo nor FMidentification nor NICAM processing is possible simultaneously. 4.1.8. FM Carrier-Mute Function in the Dual Carrier FM Mode To prevent noise effects or FM identification problems in the absence of one of the two FM carriers, the MSP 3410D offers a carrier detection feature, which must be activated by means of AD_CV[9]. If no FM carrier is available at the MSPD channel 1, the corresponding channel FM2 is muted. If no FM carrier is available at the MSPD channel 2, the corresponding channel FM1 is muted. 4.1.9. DQPSK-Decoder In case of NICAM-mode, the phase samples are decoded according the DQPSK-coding scheme. The output of this block contains the original NICAM-bitstream. 4.1.10. NICAM-Decoder Before any NICAM decoding can start, the MSP must lock to the NICAM frame structure by searching and synchronizing to the so-called Frame Alignment Words (FAW). To reconstruct the original digital sound samples, the NICAM- bitstream has to be descrambled, deinterleaved, and rescaled. Also, bit error detection and correction (concealment) is performed in this NICAM specific block. To facilitate the Central Control Unit CCU to switch the TV-set to the actual sound mode, control information on the NICAM mode and bit error rate are supplied by the the NICAM-Decoder. It can be read out via the I2C-Bus. An automatic switching facility (AUTO_FM) between NICAM and FM/AM reduces the amount of CCU-instructions in case of bad NICAM reception.


SCART Switching Facilities
The analog input and output sections include full matrix
switching facilities, which are shown in Fig. 4–3.To design
a TV set with 4 pairs of SCART-inputs and two pairs
of SCART-outputs, no external switching hardware is required.
The switches are controlled by the ACB bits defined in
the audio processing interface (see section 7. Programming
the DSP Section).


DSP Section (Audio Baseband Processing)
All audio baseband functions are performed by digital
signal processing (DSP). The DSP functions are
grouped into three processing parts: input preprocessing,
channel source selection, and channel postprocessing
(see Fig. 4–5 and section 7.).
The input preprocessing is intended to prepare the various
signals of all input sources in order to form a standardized
signal at the input to the channel selector. The
signals can be adjusted in volume, are processed with
the appropriate deemphasis, and are dematrixed if necessary.
Having prepared the signals that way, the channel selector
makes it possible to distribute all possible source signals
to the desired output channels.
The ability to route in an external coprocessor for special
effects, like surround processing and sound field processing,
is of special importance. Routing can be done
with each input source and output channel via the I2S inputs
and outputs.
All input and output signals can be processed simultaneously
with the exception that FM2 cannot be processed
at the same time as NICAM. FM-identification
and adaptive deemphasis are also not possible simultaneously.
Note that the NICAM input signals are only
available in the MSP 3410B and MSP 3410D versions.
4.3.1. Dual Carrier FM Stereo/Bilingual Detection
For the terrestrial dual FM carrier systems, audio information
can be transmitted in three modes: Mono, stereo,
or bilingual. To obtain information about the current
audio operation mode, the MSP 3410D detects the socalled
identification signal. Information is supplied via
the Stereo Detection Register to an external CCU.



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CXA1645 AV Selector

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TDA4780 RGB video processor with automatic cut-off control and gamma adjust

FEATURES · Gamma adjust · Dynamic black control (adaptive black) · All input signals clamped on black-levels · Automatic cut-off control, alternative: output clamping on fixed levels · Three adjustable reference voltage levels via the I2C-bus for automatic cut-off control · Luminance/colour difference interface · Two luminance input levels allowed · Two RGB interfaces controlled by either fast switches or by the I2C-bus · Two peak drive limiters, selection via the I2C-bus · Blue stretch; selection via the I2C-bus · Luminance output for Scan Velocity Modulation (SCAVEM) · Extra luminance output; same pin can be used as hue control output e.g. for the TDA4650 and TDA4655 · Non standard operations like 50 Hz vertical at 32 kHz horizontal are also possible · Either 2 or 3 level sandcastle pulse applicable · High bandwidth for 32 kHz application · White point adjusts via the I2C-bus · Average beam current and improved peak drive limiting · Two switch-on delays to prevent discoloration during start-up · All functions and features programmable via the I2C-bus · PAL/SECAM or NTSC matrix selection. GENERAL DESCRIPTION The TDA4780 is a monolithic integrated circuit with a luminance and a colour difference interface for video processing in TV receivers. Its primary function is to process the luminance and colour difference signals from a colour decoder which is equipped e.g. with the multistandard decoder TDA4655 or TDA9160 plus delay line TDA4661 or TDA4665 and the Picture Signal Improvement (PSI) IC TDA467X or from a feature module. The required input signals are: · Luminance and negative colour difference signals · 2 or 3-level sandcastle pulse for internal timing pulse generation · I2C-bus data and clock signals. Two sets of analog RGB colour signals can also be inserted, e.g. one from a peritelevision connector (SCART plug) and the other one from an On-Screen Display (OSD) generator. The TDA4780 has I2C-bus control of all parameters and functions with automatic cut-off control of the picture tube cathode currents. It provides RGB output signals for the video output stages. In clamped output mode it can also be used as an RGB source. The main differences with the sister type TDA4680 are: · Additional features; namely gamma adjust, adaptive black, blue stretch and two different peak drive limiters · The measurement lines are triggered by the trailing edge of the vertical component of the sandcastle pulse · I2C-bus receiver only; automatic white level control is not provided; the white levels are determined directly by the I2C-bus data · The TDA4780 is pin compatible (except pin 18) with the TDA4680. The I2C-bus slave address can be used for both ICs. When a function of the TDA4780 is not included in the TDA4680, the I2C-bus command is not executed. Special commands (except control bit FSWL) for the TDA4680 will be ignored by the TDA4780.
FUNCTIONAL DESCRIPTION Signal input stages The TDA4780 contains 3 sets of input signal stages for: 1. Luminance and colour difference signals: a) Y: 0.45 V (p-p) VBS or 1.43 V (p-p) VBS; selectable via the I2C-bus b) -(R - Y): 1.05 V (p-p) c) -(B - Y): 1.33 V (p-p). The capacitively coupled signals are matrixed to RGB signals by either a PAL/SECAM or NTSC matrix (selected via the I2C-bus). 2. (RGB)1 signals: 0.7 V (p-p) VB; capacitively coupled (e.g. from external source) 3. (RGB)2 signals: 0.7 V (p-p) VB; capacitively coupled (e.g. video text and OSD). All input signals are clamped in order to have the same black levels at the signal switch input. Displayed signals must be synchronous with the sandcastle pulse. Signal switches Both fast signal switches can be operated by switching pins (e.g. SCART facilities) or set via the I2C-bus. With pin FSW1 the luminance and colour difference signals or the (RGB)1 signals can be selected and with pin FSW2 the above selected signals or the (RGB)2 signals are enabled. During the vertical and horizontal blanking time an artificial black level equal to the clamped black level is inserted in order to clip off the sync pulse of the luminance signal and to suppress hum during the cut-off measurement time and eliminate noise during these intervals. Saturation, contrast and brightness Saturation, contrast and brightness adjustments are controlled via the I2C-bus and act on luminance and colour difference signals as well as on RGB input signals. Gamma acts on the luminance content of the input signals. Gamma adjust stage The gamma adjust stage has a non-linear transmission characteristic according to the formula y = xgamma, where x represents the input and y the output signal. If gamma is smaller than unity, the lower parts of the signal are amplified with higher gain. Adaptive black (ADBL) The adaptive black stage detects the lowest voltage of the luminance component of the internal RGB signals during the scanning time and shifts it to the nominal black level. In order to keep the nominal white level the contrast is increased simultaneously. Blue stretch (BLST) The blue stretch channel gets additional amplification if the blue signal is greater than 80% of the nominal signal amplitude. In this event the white point is shifted towards higher colour temperature so that white parts of a picture seem to be brighter. Measurement pulse and blanking stage During the vertical and horizontal blanking time and the measurement period the signals are blanked to an ultra black level, so that the leakage current of the picture tube can be measured and automatically compensated for. During the cut-off measurement lines (one line period for each R, G or B) the output signal levels are at cut-off measurement level. The vertical blanking period is timed by the sandcastle pulse. The measurement pulses (leakage, R, G and B) are triggered by the negative going edge of the vertical pulse of the sandcastle pulse and start after the following horizontal pulse. The IC is prepared for 2fH (32 kHz) application. Output amplifier and white adjust potentiometer The RGB signals are amplified to nominal 2 V (p-p), the DC-levels are shifted according to cut-off control. The nominal signal amplitude can be varied by ±50% by the white point adjustment via the I2C-bus (individually for RGB respectively).

Automatic cut-off control
During the leakage measurement time the leakage current
is compensated in order to get a reference voltage at the
cut-off measurement information pin. This compensation
value is stored in an external capacitor. During cut-off
current measurement times for the R, G and B channels,
the voltage at this pin is compared with the reference
voltage, which is individually adjustable via the I2C-bus for
each colour channel. The control voltages that are derived
in this way are stored in the external feedback capacitors.
Shift stages add these voltages to the corresponding
output signals. The automatic cut-off control may be
disabled via the I2C-bus. In this mode the output voltage is
clamped to 2.5 V. Clamping periods are the same as the
cut-off measurement periods.
Signal limiting
The TDA4780 provides two kinds of signal limiting. First,
an average beam limiting, that reduces the signal level if a
certain average is exceeded. Second, a peak drive
limiting, that is activated if one of the RGB signals even
shortly exceeds a via the I2C-bus adjusted threshold. The
latter can be either referenced to the cut-off measurement
level of the outputs or to ground.
When signal limiting occurs, the contrast is reduced, and
at minimum contrast the brightness is reduced
additionally.
Sandcastle decoder and timer
A 3-level detector separates the sandcastle pulse into
combined line and field pulses, line pulses, and clamping
pulses. The timer contains a line counter and controls the
cut-off control measurement.
Application with a 2-level 5 V sandcastle pulse is possible.
Switch-on delay circuit
After switch-on all signals are blanked and a warm-up test
pulse is fed to the outputs during the cut-off measurement
lines. If the voltage at the cut-off measurement input
exceeds an internal level the cut-off control is enabled but
the signal remains still blanked. In the event of output
clamping, the cut-off control is disabled and the switch-on
procedure will be skipped.
Y output and hue adjust
The TDA4780 contains a digital-to-analog converter for
hue adjust. The analog information can be fed, e.g. to the
multistandard decoder TDA4650 or TDA4655. This output
pin may be switched to a Y output signal, which can be
used for scan velocity modulation. The Y output is the
Y input signal or the matrixed (RGB) input signal according
to the switch position of the fast switch.
I2C-bus
The TDA4780 contains an I2C-bus receiver for control
functions.
ESD protection
The pins are provided with protection diodes to ground and
supply voltage (see Chapter “Internal pin configuration”).
I2C-bus input pins do not shunt the I2C-bus signals in the
event of missing supply voltage.