1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical
BACKGROUND OF THE INVENTION
The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.
TDA2522 PAL TV CHROMA DEMODULATOR COMBINATION
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION- The TDA2522 is a monolithic integrated circuit designed as
a synchronous demodulator for PAL color television receivers. It includes an 8,8 MHz
oscillator and divider to generate two 4.4 MHz reference signals and provides color difference outputs.
PACKAGE OUTLINE 9B
The TDA2522 is Intended to Interface directly with the TDA2560 with a minimum oF external components. The TDA2530 may be added if RGB drive is required. The TDA2522
is constructed using the Fairchild Planar* process.
TDA2560 LUMINANCE AND CHROMINANCE CONTROL COMBINATION
The TDA2560 is a monolithic integrated circuit for use in decoding systems of COLOR
television receivers. The circuit consists of a luminance and chrominance amplifier.
The luminance amplifier has a low input impedance so that matching of the luminance
delay line is very easy.
It also incorporates the following functions:
- d.c. contrast control;
- d.c. brightness control;
- black level clamp;
- blanking;
- additional video output with positive-going sync.
The chrominance amplifier comprises:
- gain controlled amplifier;
- chrominance gain control tracked with contrast control;
- separate d.c. saturation control:
- combined chroma and burst output, burst signal amplitude not affected by contrast and
saturation control;
- the delay line can be driven directly ‘by the IC.
APPLICATION INFORMATION (continued)
The function is quoted against the corresponding pin number
Balanced chrominance input signal (in conjunction with pin 2)
This is derived from the chrominance signal bandpass filter, designed to provide a
push-pull input. A signal amplitude of at least 4 mV peak-to-peak is required
between pins l and 2. The chrominance amplifier is stabilized by an external feedback
loop from the output (pin 6) to the input (pins I and 2). The required level at pins l
and 2 will be 3 V.
All figures for the chrominance signals are based on a colour bar signal with 75%
saturation: i.e. burst-to-chrominance ratio of input signal is 1 1 2.
Chrominance signal input (see pin 1)
A. C.C. input
A negative-going potential, starting at +l,2 V, gives a 40 dB range of a. c. c.
Maximum gain reduction is achieved at an input voltage of 500 mV.
Chrominance saturation control
A control range of +6 dB to >-14 dB is provided over a range of d. c. potential on
pin 4 from +2 to +4 V. The saturation control is a linear function of the control
voltage.
Negative supply (earth)
Chro minance signal output
For nominal settings of saturation and contrast controls (max. -6 dB for saturation,
and max. -3 dB for contrast) both the chroma' and burst are available at this pin, and
in the same ratio as at the input pins 1 and 2. The burst signal is not affected by the
saturation and contrast controls. The a.c. c. circuit of the TDA2522 will hold
constant the colour burst amplitude at the input of the TDA2522. As the PAL delay
line is situated here between the TDA256O and TDA2522 there may be some variation
of the nominal 1 V peak-to-peak burst output of the TDA2560, according to the
tolerances of the delay line. An external network is required from pin 6 of the
TDA256O to provide d. c. negative feedback in the chroma channel via pins I and 2.
Burst gating and clamping pulse input
A two-level pulse is required at this pin to be used for burst gate and black level
clamping. The black level clamp is activated when the pulse level is greater than
7 V. The timing of this interval should be such that no appreciable encroachment
occurs into the sync pulse on picture line periods during normal operation of the
receiver. The burst gate, which switches the gain of the chroma amplifier to
maximum, requires that the input pulse at pin 7 should be sufficiently wide, at least
8 ps, at the actuating level of 2,3 V.
+12 V power supply
Correct operation occurs within the range 10 to 14 V. All signal and control levels
have a linear dependency on supply voltage but, in any given receiver design, this
range may be restricted due to considerations of tracking between the power supply
variations and picture contrast and chroma levels.
Flyback blanking input waveform
This pin is used for blanking the luminance amplifier. When the input pulse exceeds
the +2, 5 Vlevel, the output signal is blanked to a level of about 0 V. When the input
exceeds a +6 V level, a fixed level of about 1, 5 V is inserted in the output. This
level can be used for clamping purposes.
Luminance sigal output
An emitter follower provides a low impedance output signal of 3 V black-to-white
amplitude at nominal contrast setting having a black level in the range 1 to 3 V. An
external emitter load resistor is not required.
The luminance amplitude available for nominal contrast may be modified according
to the resistor value from pin 13 to the +12 V supply. At an input bias current
114 of 0,25 mA during black level the amplifier is compensated so that no black
level shift more than 10 mV occurs at contrast control. When the input current
deviates from the quoted value the black level shift amounts to 100 mV/rnA.
Brightness control
The black level at the luminance output (pin 10) is identical to the control voltage
required at this pin, A range of black level from l to 3 V may be obtained.
Black level clamp capacitor
Luminance gain setting resistor
The gain of the luminance amplifier may be adjusted by selection of the resistor
value from pin 13 to +12 V. Nominal luminance output amplitude is then 3 V
black-to-white at pin 10 when this resistor is 2, 7 l
TDA2530 RGB MATRIX PREAMPLIFIER
The TDA2530 is an integrated RGB -matrix preamplifier for colour television receivers,
incorporating a matrix preamplifier for RGB cathode drive of the picture tube with
clamping circuits.
The three channels have the same layout to ensure identical frequencybehaviour.
This integrated circuit has been designed to be driven from the TDA2522 Synchronous
demodulator and oscillator IC.
TDA2591 / TDA2593 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET
DESCRIPTION
The TDA2591 is a circuit intended for the horizontal
deflection of color TVsets, supplied with transistors
or SCR’S.
The TDA2591 and TDA2593 are integrated line
oscillator ‘_circuits for colour television receivers using
thyristor or transistor line deflection output stages.
The _circuits incorporate a line oscillator ‘which is
based on the threshold switching principle, a line de-
flection output stage capable of direct drive of thyristor
deflection circuits, phase comparison between the
oscillator voltage and both the sync pulse and line
flyback pulse. Also included on the chip is a switch for
changing the filter characteristic and the gate circuit
when used for VCR.
The TDA2593 generates a sandcastle pulse (at pin
7) suitable for use with the TDA.2532.
.LINE OSCILLATOR(two levels switching)
.PHASE COMPARISON BETWEEN SYNCHRO-
PULSE AND OSCILLATOR VOLTAGE Ø 1, ENABLED BY AN INTERNAL PULSE,
(better parasitic immunity)
PHASE COMPARISON BETWEEN THE FLYBACK
PULSES AND THE OSCILLATOR VOLTAGE Ø2
.COINCIDENCE DETECTOR PROVIDING A LARGE HOLD-IN-RANGE.
.FILTER CHARACTERISTICS AND GATE SWITCHING FOR VIDEO RECORDER APPLICATION.
.NOISE GATED SYNCHRO SEPARATOR
.FRAME PULSE SEPARATOR .BLANKING AND SAND CASTLE OUTPUT PULSES
.HORIZONTAL POWER STAGE PHASE LAGGING CIRCUIT
.SWITCHING OF CONTROL OUTPUT PULSE WIDTH
.SEPARATED SUPPLY VOLTAGE OUTPUT STAGE ALLOWING DIRECT DRIVE OF SCR’S CIRCUIT
.SECURITY CIRCUIT MAKES THE OUTPUT PULSE SUPPRESSED WHEN LOW SUPPLY
VOLTAGE.
GALAXI MOD. GALAXONE 27" CHASSIS GF77/M1702 Electronic tuning circuit arrangement for direct and indirect station selection using a memory circuit :
1. An electronic tuning circuit arrangement comprising:
(a) a control panel (101) having a plurality of push-buttons or sensors;
(b) first means (104) actuable by at least one of said push-buttons or sensors to produce digitally coded information identifying respective ones of a plurality of tunable signals;
(c) second means (128) which receive said digitally coded information and correspondingly supply a respective number (N) in digital form for tuning each signal;
(d) a counter divider (126) connected to receive the digital output of said second means (128) as a divider, and a clock signal (f) derived from a voltage-controlled oscillator (130) as a dividend, for producing a quotient signal (f/N) representing the clock signal frequency divided by said respective number;
(e) means (133) for comparing said quotient signal (f/N) with a frequency reference oscillation (fr) and producing a resultant signal which is supplied in controlling relation to said voltage-controlled oscillator (130) for causing said oscillator to produce a tuning signal (fo) directly proportional to said respective number;
(f) a memory circuit (108) having a plurality of cells; said first means (104) supplying to said memory circuit (108), and storing in each of said cells, under the action of push-buttons or sensors of said control panel (101) the digitally coded information relating to each of a plurality of preferred signals preselected by the user from among said plurality of tunable signals; said first means (104) under the action of push-buttons or sensors of said control panel (101) selectively supplying to said counter divider (126) from said second means (128) only one desired respective number in digital form for the tuning of each signal, either through digitally coded information directly supplied to said second means (128) from said first means (104) or through digitally coded information supplied from said memory circuit (108) to said second means (128); and
(g) third means (113) supplying said counter divider (126) from said second means (128) with said respective number in digital form, by sequentially scanning one after another said cells of said memory circuit (108) and then supplying said second means (128) with the stored digitally coded information obtained from each cell scanned.
2. The circuit arrangement of claim 1, wherein said third means (113) comprises an electronic counter whose outputs are connected through gate means (109) to address inputs of said memory circuit (108), and control logic circuits included in said first means (104) which control said gate means (109) and said memory circuit (108) in such a manner that, when the third means (113) are activated, the digitally coded information received by said second means (128) will only be that stored in the cell scanned of said memory circuit (108). 3. The circuit arrangement of claim 2, wherein said counter (113) is a binary counter operable both up and down. 4. The circuit arrangement of claim 3, wherein said counter (113) supplies a four bit output. 5. The circuit arrangement of claim 3, wherein further logic circuits (115, 117, 120, 121) are provided which are activated by manually actuating a push-button or sensor of said control panel (101) for causing the output of said counter (113) to advance or to recede by one step at a time. 6. The circuit arrangement of claim 3, wherein a clock signal of predetermined frequency is fed to the input of said counter (113) upon manually actuating a push-button or sensor of said control panel (101), the output of said counter progressively increasing (or progressively decreasing) by one step at a time as long as said push-button or sensor is actuated. 7. The circuit arrangement of claim 2, wherein second control logic circuits included in said first means (104) are provided which control, through second gate means (122) connected at the outputs of said electronic counter (113), the utilization of said counter (113) for at least a second function. 8. The circuit arrangement of claim 7, wherein, in being utilized for said second function, said electronic counter (113) supplies digit correction signals to said second means (128) and to said counter divider (126), said digit correction signals being also supplied to said memory circuit (108) for storage in a cell corresponding to stored digitally coded information relating to a tunable signal, whereby the stored digitally coded information relating to a tunable signal and the stored digit correction signals from each cell are supplied to said second means (128) and to said counter divider (126) either by said first means (104) or by said third means (113). 9. The circuit arrangement of claim 8, wherein fourth means (112, 124) are provided for stopping said counter in the stage in which it supplies said digit correction signals, when the count reached by said counter, in counting up and down, corresponds to predetermined numbers, said fourth means (112, 124) being inactive during the stage in which said third means (113) operates for sequentially scanning the cells of said memory circuit (108). 10. The circuit arrangement of claim 8, wherein said counter divider (126) receives twelve bits at its input.BACKGROUND OF THE INVENTION
This invention relates to a circuit arrangement for the selection of one among a plurality of radioelectric signals receivable in a signal receiving set, particularly television signals, comprising a memory circuit in which information relating to a plurality of tunable signals can be stored in digital form. A circuit arrangement of this type is described in copending U.S. patent application Ser. No. 729,757 filed on Oct. 5, 1976 in the name of Mario Malerba and of common assignment herewith.
Such circuit arrangement, applied, for example, to a television set, comprises a voltage controlled oscillator (VCO) whose output signal has a frequency determined by a control loop as a function of a number N different for each one of the frequencies of the selectable signals and obtained from a memory circuit. To select a frequency of a television channel, the number of the channel is set, for example, by means of a push button panel having ten push buttons numbered from 0 to 9, as that of a pocket calculator, and is sent as an address to the memory circuit which substantially produces the number N corresponding to the frequency to be selected. In this way, it is possible to select directly any one of 100 tunable channels, by forming a number of two figures from 00 to 99 on the push button panel. Moreover, it is possible to apply to the tuning thus obtained, which is the theoretical tuning, a manual correction by means of two further push buttons, which determines a variation of the less significant digits of the number N. Thus, it is possible to store in one of the cells of a second memory circuit the information for forming the number N, which is relative to the tuned channel, and to correlate it to a chosen one of the ten push buttons of the panel, so that it will then be possible to read out the ten stored channels with the tunings already corrected.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved electronic tuning circuit arrangement which, by adding a further possibility of selection of stored channels, ameliorates the convenience of tuning for the user.
It is also an object of the invention to provide for the above object to be attained in a very economical way by utilizing devices already existing in the circuit of the receiving set.
A further object of the present invention is to provide an electronic tuning circuit arrangement for a signal receiving set, in particular a television set, comprising a memory circuit having a plurality of cells for storing in digital form information relating to a plurality of tunable signals; and means for sequentially scanning the cells of the memory circuit and for obtaining the stored information for the desired selection of a tunable signal.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the invention, it will now be described in detail with reference to the accompanying drawings given by way of example and in which:
FIG. 1 shows a diagram of a circuit arrangement for a digital control tuner in a television signal receiving set, embodying the principles of the present invention; and
FIGS. 2 and 3 respectively show in detail the control unit and processing unit depicted as blocks in FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION
In
FIG. 1, there is diagramatically shown a control board 101 having ten push buttons or touch sensors numbered from 0 to 9, and having, moreover, four additional push buttons or sensors distinguished by the indications D, M, +, -.
Each of the ten push buttons numbered from 0 to 9 is connected to the input of a decimal-binary converter logic circuit 102 having four output conductors on which the information corresponding to the number of the actuated push button appears in binary code.
These four conductors, together with two conductors connected to the push buttons D and M and with a further output conductor from an AND gate 103, arrive at respective inputs 500, 501, 502, 503, 519, 520 and 521 of a control unit 104 comprising a plurality of logic circuits which operate on the input signals in a manner to be described later. Unit 104 may be of the type described in the aforementioned copending U.S. patent application Ser. No. 729,757 and it possesses fifteen outputs 504-518, the first eight (504-511) of which are connected to the inputs of:
a circuit converter 105, converting the data in BCD code into data in binary code, which converts into a single binary number (of seven bits) two binary numbers (of four bits each) which it receives, giving to them the respective weight;
a double seven-segments display 106, through a double binary-seven segments converter 107; and to eight of the twelve inputs-outputs of a RAM (Random Access Memory) 108 having ten memory cells of twelve bits and preferably of the non-volatile type.
The subsequent four outputs 512-515 of the control unit 104 are connected to four address inputs of RAM 108 to which are also connected four outputs of a separator (or buffer) circuit 109 which has an enabling input CE (Chip Enable) connected to the output of gate 103. Separator circuit 109 may conveniently be represented by four AND gates.
The remaining three outputs 516-518 of control unit 104 are connected:
the first: to an input of AND gate 103, to the read-write (R/W) input of RAM memory 108, to the input of an inverting gate 111 and finally to an input of an OR gate 112 having four inputs;
the second: to the enabling input CE of RAM memory 108;
the third: to the reset input R of a four bit counter 113 capable of counting up and down, from zero to nine.
The push button + of control board 101 is connected, through a conductor 114, to an input of an AND gate 115; the push button - is connected, through a conductor 116, to an input of an AND gate 117. The outputs of the gates 115 and 117 are connected to two inputs SET 118 and RESET 119 of a bistable multivibrator 120 and also to the two inputs of an OR gate 121. One output of multivibrator 120 is connected to a count inversion input U/D (UP-DOWN) of counter 113; the output of gate 121 is connected to the second input of gate 103 and to the clock input of counter 113. The four outputs of counter 113 are connected both to the inputs of separator circuit 109 and to the inputs of another identical separator circuit 122. Circuit 122 has an enabling input CE which is connected to the output of inverting gate 111, which output is connected also to an input of a four input NAND gate 124.
Separator circuit (or buffer) 122 has three outputs (of which one, which corresponds to the most significant input, is free) which are connected to the remaining inputs both of gate 112 and of gate 124. The output of NAND gate 124 is connected to the second input of AND gate 115; the output of OR gate 112 is connected to the second input of AND gate 117.
The three outputs of buffer 122 are connected also to three of the remaining inputs-outputs of RAM 108. The two less significant outputs of buffer 122 are connected also to two (the less significant) of twelve inputs of a twelve bit binary counter-divider 126; the third output of buffer 122 is also connected to an input 127 of a processing unit 128 which comprises a plurality of logic circuits and an adder circuit and whose operation will be described later. Processing unit 128 may conveniently be of the type described in my copending U.S. patent application Ser. No. 735,564 filed on Oct. 26, 1976 and of common assignment herewith. The seven outputs of converter circuit 105 are connected to as many inputs 530-536 of processing unit 128 which has ten outputs 540-549 connected to the remaining ten most significant inputs of counter 126. A voltage controlled oscillator (VCO) 130 supplies to the tuner (not shown) a local frequency oscillation fo for frequency conversion and supplies this local oscillation also to a frequency divider (or prescaler) 131 which divides in the ratio 1:256.
At the output of divider 131, there is present a frequency oscillation f which arrives as a clock signal at counter 126 which produces a frequency signal f/N, where N is the number in binary code which is present at the twelve inputs of counter 126. The output of counter 126 is connected to a first input 132 of a phase comparator 133 which has a second input 134 which receives from a circuit 135 of well-known type a frequency reference oscillation fr. Circuit 135 may comprise, for example, a line frequency oscillator, tuned by line synchronism pulses, followed by a frequency divider circuit which divides, for example, in the ratio 1:16.
The output of comparator 133 is connected to the input of oscillator 130, and it controls the frequency fo so that: f/N=fr
and consequently, with the hypotheses assumed: fo =256 N fr (1)
The processing unit 128 has another two outputs 140 and 141 which supply to the tuner the informations relative to band change.
Control unit 104 of FIG. 1 is shown in detail in FIG. 2, and it represents a part of the circuit disclosed in the aforementioned copending U.S. patent application 
Ser. No. 729,757. In the diagrammatic representation of FIG. 2, the groups of conductors which follow the same path of connection are shown by a single line, by the side of which a numeral indicates how many conductors the group contains; where no numeral is present, it means that the line is formed by a single conductor.
The inputs 500, 501, 502, 503 of control unit 104 are connected through four conductors to inputs of three identical latches, indicated in FIG. 2 by reference numerals 611, 612 and 613, each of which is provided with four inputs and with an enabling input IE (Input Enable). The outputs of latches 611 and 612 are connected, through two lines of four conductors each, and through a separator circuit (or buffer 649) to the two groups of four outputs of circuit 104, respectively 504, 505, 506, 507 and 508, 509, 510, 511.
The inputs 500, 501, 502 and 503 are also connected to inputs of an OR gate 605. The input 520 is connected to a further input of the gate 605 and to an input of a bistable multivibrator (flip-flop) 608 provided with a reset input R. The input 519 is connected to an input of a bistable multivibrator (flip-flop) 609 and to an input of an OR gate 610 having two inputs.
The output of gate 605 is connected to the input of a bistable multivibrator (flip-flop) 615 provided with a reset input R, this latter being connected to the output of the gate 610. Multivibrator 615, as well as multivibrators 608 and 609, have two outputs, one of which is at the opposite logic level of the other. For simplicity of representation, only one output is shown in FIG. 2; however, it can be seen that said output arrives sometimes to negative inputs of gates or to inverter circuits, such as that indicated by reference numeral 617. It is clear that, actually, the corresponding circuits are connected to the negative output of the respective multivibrator.
Thus, the negative output of multivibrator 615 is connected through a delay circuit 618 to:
one input of an AND gate 619 having two inputs;
one input of an AND gate 620 having two inputs;
and, through an additional delay circuit 622, to a differentiator circuit 623.
The positive output of multivibrator 615 is, in turn, connected to an input of an AND gate 624 having two inputs, also through a delay circuit 618 (the delay circuit 618, instead of being disposed at the outputs, may be disposed at the input of multivibrator 615).
The positive output of multivibrator 608 is connected to:
a light source 602, for illuminating the push button M
and, through a delay circuit 625, to the other input of the AND gate 620.
The delay circuits 618, 625 and 622, which produce a time delay equal to τ1, τ2 and τ3 respectively, are such that τ1 <τ2 <τ3.
The negative output of multivibrator 608 is connected:
to the other input of AND gate 619, and to
the other input of AND gate 624.
The outputs of gates 619 and 624 are connected to enabling inputs IE of latches 611 and 612, respectively.
The output of AND gate 620 arrives at an input of an OR gate 626 having two inputs.
The positive output of multivibrator 609 is connected to:
a light source 603, for illuminating the push button D; and
to the enabling input CE of the buffer 649.
The negative output of multivibrator 609 is connected to:
the other input of gate 626; and
through the inverter 617, to the output 516.
The output of gate 626 is connected to the output 517 and, through an inverter 651, to an input of an OR gate 650; the output of latch 613 is connected, through a four conductor line, to the outputs 512, 513, 514 and 515.
A terminal S which receives the external supply voltage is connected, through a switch 641 of the receiving set, to a differentiator circuit 642 whose output is connected:
to the reset input R of multivibrator 609;
to the other input of gate 610; and
to an input of an OR gate 643 having two inputs.
The other input of gate 643 is connected to the output of differentiator circuit 623; the output of gate 643 is connected to the reset input R of multivibrator 608 and to the output 518. The input 521 is connected to the other input of gate 650. The output of gate 650 is connected to an output disable terminal OD of latch 613.
The pr
ocessing unit 128 is shown, in detail, in FIG. 3, and it represents a part of the circuit disclosed in the aforementioned copending U.S. patent application 735,564. The seven inputs 530, 531, 532, 533, 534, 535 and 536 are connected to seven wires indicated by I, II, III, IV, V, VI and VII.
Wires I and II are connected to the inputs of an OR gate 701 whose output, together with a connection from wire III, is connected to the inputs of an OR gate 702. The output of OR gate 702 is connected to an input of an OR gate 703, to an input of an AND gate 704 and to an input of an OR gate 705. Wires VI and VII are connected to the two inputs of an OR gate 706 whose output, together with a connection from wire V, is connected to the two inputs of an AND gate 707. The output of this AND gate 707, together with a connection from wire IV, is connected to the two inputs of a NOR gate 708 whose output is connected to the other input of OR gate 703. The output of OR gate 703 is connected both to an input of an AND gate 709, and to an inverter 710. The output of AND gate 707 is connected also to an input of an OR gate 711, the other input of which having connected thereto the output of OR gate 701. The output of OR gate 711 is connected to an input of an OR gate 712, the other input of which has connected thereto the output of an exclusive NOR gate 713 whose two inputs are connected to the wires III and IV. The output of OR gate 712 is connected to the other input of AND gate 709. The output of AND gate 709 is connected to the other input of AND gate 704, to the input of an inverter 714, to an input of an AND gate 715, to an input of a NOR gate 729 and to an input 17 of an adder 716 which effects the addition of a first addend of nine binary digits, which it receives at inputs numbered from 11 to 19, with a second addend of ten binary digits which it receives at inputs numbered from 21 to 30. The output of AND gate 704 is connected to an input of an OR gate 717, to an input of NOR gates 718, 719 and 720 respectively, and to the input 19 of adder 716. The output of inverter 714 is connected to an input of an OR gate 721, to an input of an AND gate 722 and to the input 18 of adder 716. The other input of gates 721 and 722 is connected to a wire to which is applied a signal at logic level "0". The output of the AND gate 722 is connected to the other input of the OR gate 717 and to an input of an AND gate 723.
The wire α is connected also to an input of exclusive OR gates 725, 726, 727 and 728 respectively. Gate 725, whose other input is connected to the wire IV, has its output connected to the other input of NOR gate 729. Gate 726, whose other input is connected to the wire V, has its output connected to the other input of gate 720. Gate 727, whose other input is connected to the wire VI, has its output connected to the other input of gates 719 and 723. Gate 728, whose other input is connected to the wire VII, has its output connected to the other input of gate 718. The wire V is connected to an input of two AND gates 730 and 731 respectively. Gate 730, whose other input is connected to the output of gate 723, has its output connected to an input of an OR gate 732, whose output is connected to the other input of gate 731 and to the input of an inverter 733. Connected to the other input of gate 715 is the wire α, and the output of gate 715 is connected to the other input of OR gates 705 and 732. The output of gate 718 is connected to the input 11 of adder 716. The outputs of gates 719 and 731 are connected to the two inputs of an OR gate 735, whose output is connected to the input 12 of adder 716. The output of gate 720 is connected to the input 13 of adder 716. To the inputs 14, 15 and 16 of adder 716 are connected, respectively, the outputs of NOR gate 729, of OR gate 705 and of inverter 710. To the inputs 21, 22 and 23 of adder 716 there are connected the outputs of inverter 733, of OR gate 721 and of OR gate 717, respectively. The inputs from 24 to 30 of adder 716 are connected, respectively, to the wires VII, VI, V, IV, III, II and I.
Adder 716 has ten outputs, indicated progressively by reference numerals 41 to 50, which are respectively connected to the ten outputs (540, 541, 542, 543, 544, 545, 546, 547, 548, 549) of processing unit 128.
The input 127 is connected to an additional input 62 of adder 716.
The outputs of inverter 714 and of gate 704 are respectively connected to outputs 140 and 141.
The operation of the circuit arrangement of FIG. 1 will now be explained.
Control unit 104 comprises a plurality of logic circuits which operate on the various input signals so as to supply, in the various stages of operation which will be listed, the following levels of the output signals:
(I)--At the switching on of the receiving set:
"zero" on all the first twelve outputs 504-515;
"one" on the thirteenth output 516 (the RAM memory 108 therefore disposes itself to be "read", and the buffer circuit 122 is disabled);
"one" on the fourteenth output 517 (the RAM memory 108 is enabled);
a pulse on the fifteenth output 518, which pulse causes the output of the counter 113 to assume the value which has been set and which is equal to four.
In fact, at the moment of switching on the receiving set, by means of the switch 641, the three multivibrators 608, 609 and 615 are reset by means of differentiator circuit 642 and gates 610 and 643, and the outputs of said three multivibrators become "zero" level (reference is made here, as well as hereinafter, unless otherwise stated, to the normal, not negative, outputs), so that the circuit arrangement is prepared for indirect selection as will be better explained later. For accomplishing indirect access by switching on the receiving set, however, it is assumed that memory 108 has been pre-loaded by the user with the desired channels. It will, however, be useful to initiate the explanation by referring to the operation on direct station selection.
(II)--By actuating the push button D and then a couple of numbered push buttons of the control board 101 (for example the one with the digit 1 and then the one with the digit 2), whereby the signals corresponding to said two digits arrive at the control unit 104 successively, through the converter 102;
the digit (in binary code) which corresponds to the first numbered push button which has been actuated (i.e. 1) appears on the first four outputs 504-507;
the digit (in binary code) which corresponds to the second numbered push button which has been actuated (i.e. 2) appears on the second four outputs 508-511; moreover, there is:
"zero" on the third group of four outputs 512-515;
"zero" on the thirteenth output 516 and fourteenth output 517 (the memory RAM 108 is disabled and the buffer circuit 122 is enabled);
a reset pulse on the fifteenth output 518, which pulse causes the output of the counter 113 to assume the value of +4.
In fact, by pressing push button D of panel 101, a "one" signal is produced at input 519. Accordingly, multivibrator 609, which has been reset at the moment of switching on the receiving set, changes state and its output becomes high, thereby producing the switching on of light source 603, the signal "zero" at output 516, and the signal "zero" at output 517. Actually, gate 620 has an input at low level (the one connected to the output of multivibrator 608 through delay circuit 625) and, accordingly, gate 626 has both inputs at low levels. Then, when the number of the channel to be selected is formed (in this case, the number 12), the user presses first the push button having the numeral 1 and then the push button having the numeral 2 (should he want to select a channel having a number less than 10, it is necessary to form 01, 02, etc.). The corresponding signals in binary code arrive at inputs 500 . . . 503 of control unit 104, and the output of multivibrator 615, which is reset by pressing push button D, becomes high level when the push button bearing the numeral 1 is pressed, and returns to low level when the push button bearing the numeral 2 is pressed.
After having pressed push button D, the latch 611, after the time τ1 has elapsed, becomes enabled and therefore receives in binary code the number 1 from inputs 500 . . . 503 of control unit 104, but after elapsing of the time τ1 from the moment at which the push button having numeral 1 has been pressed, latch 611 is disabled and latch 612 is enabled and thus receives the number 2.
Therefore, the numbers 1 and 2 appear, in binary codes, at the outputs 504 . . . 507, and 508 . . . 511 respectively, the buffer 649 being enabled.
After the time (τ1 +τ3) has elapsed, a pulse appears at output 518 (through differentiator circuit 623 and gate 643). The signal "zero" at the output of gate 626, through gate 650, produces a "one" signal at input OD of latch 613 which disables the outputs of latch 613 which remain at level "zero".
At this point, oscillator 130 is caused by the loop formed by circuits 131, 126, 133 and 130 to supply an oscillation frequency fo given by the relation (1), i.e. at the theoretical frequency required for receiving channel 12. In fact, processing unit 128 receives the number 12 in binary code from converter 105, and moreover, counter 113 supplies the number four. Processing unit 128, through buffer circuit 122 which is enabled, receives therefore an additional "1" at the input 127; and processing unit 128, which supplies a number suitable for each channel, supplies at its outputs 540-549 for channel 12 the number 263 (see the following Tables I and II) which arrives in binary code at the ten most significant inputs of counter 126.
| TABLE I |
| ______________________________________ |
| EUROPEAN CHANNELS BAND (K) fo (MHz) |
| ______________________________________ |
I 02 87 03 94 04 101 III 05 214 06 221 07 228 08 235 09 242 10 249 11 256 12 263 ... ... 20 319 UHF 21 510 22 518 23 526 24 534 ... ... ... ... 67 878 68 886 69 894 |
| ______________________________________ |
| TABLE II |
| ______________________________________ |
| Channel lst Addend 2nd Addend input Outputs (k) Code inputs 11... inputs 21... 62 41...(fo) |
| ______________________________________ |
3 03 0001000100 0000011001 1 94 10 10 0010100101 0001010011 1 249 12 12 0010100011 0001100011 1 263 18 18 0010011101 0010010011 1 305 21 21 0101010000 0010101101 1 510 69 69 0101010000 1000101101 1 894 |
| ______________________________________ |
Counter 126 results therefore in being set (since it receives also two "zeroes" from buffer circuit 122) to divide by N=263×4=1052. For the relation (1) it results thus, if fr =15625/16=976.5625 Hz; fo =256×976.5625×1052=263×106 Hz
which, assuming the intermediate frequency of the receiving set to be calibrated for a value of 38.75 MHz, is just the theoretical frequency of oscillator 130 which is necessary to receive channel 12 whose video carrier has the frequency of 224.25 MHz.
Let us see now how one gets the value of adder 716 to be equal to frequency fo.
At wires I . . . VII of processing unit 128 are applied, from inputs 530 . . . 536, signals representing in binary code (0-1) the number 12, the signal on wire VII being of the less significant digit, while that on wire I is of the most significant digit.
Referring to FIG. 3, it can be seen that the circuit formed by logic OR gates 701 and 702 supplies a signal at level 1 for all those circuits whose number is greater than 15; the further circuit formed by OR gate 706, AND gate 707, NOR gate 708, OR gate 703, and by inverter 710 supplies, in combination with the preceding circuits, a signal at level 1 for channels whose number is between 5 and 15; the circuit formed by gates NOR exclusive 713, or 711, OR 712 and AND 709 and by inverter 714 supplies, in combination with the preceding circuits, a signal at level 1 for the channels having a number between 5 and 20; finally, AND gate 704 supplies, in combination with the preceding circuits, a signal at level 1 for all those channels whose number is greater than 20. All this will be clearly apparent from the following Table III.
| TABLE III |
| ______________________________________ |
| Output gate signal Input of at high level (1) produced by input adder 716 signals on wires I, II, III, IV, V, VI connected Output VII determined by the selection of to gates: channels: output gate |
| ______________________________________ |
701 32 to 99 702 16 to 99 703 0 to 4; 16 to 99 704 21 to 99 19 705 16 to 99 15 706 1 to 3; 5 to 7; 9 to 11; 13 to 15; 17 to 19; 21 to 23; and so on. 707 5 to 7; 13 to 15; 21 to 23; 29 to 31; 37 to 39; and so on. 708 0 to 4; 16 to 20, 32 to 36; 48 to 52; and so on. 709 0 to 4; 21 to 99 17 710 5 to 15 16 711 5 to 7; 13 to 15; 21 to 23; 29 to 99 712 0 to 7; 13 to 15, 21 to 99 713 0 to 7; 24 to 31; 48 to 55; 72 to 79; 96 to 99 714 5 to 20 18 715 -- 717 21 to 99 23 718 even channels from 0 to 20 11 719 0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20 720 0 to 3; 8 to 11; 16 to 19 13 721 5 to 20 22 722 -- 723 -- 725 8 to 15; 24 to 31; 40 to 47; and so on. 726 4 to 7; 12 to 15; 20 to 23; 28 to 31; 36 to 39; and so on. 727 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, and so on. 728 odd channels 729 5 to 7; 16 to 20 14 730 -- 731 -- 732 -- 733 0 to 99 21 735 0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20 12 |
| ______________________________________ |
It has to be noted that, with the hypotheses which have been made and with reference to Table I, which is an internationally established table setting forth for each channel number a predetermined value of frequency assigned for the video carrier, the frequency fo is bound to the number K of the television channel by the following relations, for the various ranges:
BI (channels 2 to 4): fo =73+7K=[64+(7-K)]+[8K+1]+1
BIII (channels 5 to 15): fo =179+7K=[160+(15-K)]+[8K+3]+1
BIII (channels 16 to 20): fo =179+7K=[144+(31-K)]+[8K+3]+1
UHF (channels 21 to 99): fo =342+8K=[336]+[8K+5]+1
Said relations, for the various ranges of tunable signals, are seen to be of the type fo =M+RK, where R is a number indicative of the channel's step frequency in a predetermined range and M is indicative of a basic value of frequency which has to be fixed in said range. These relations, which give the value of fo, are not calculated directly in the circuit, but are obtained by calculating the second expressions comprising the terms shown above in square brackets. It should be noted also that for multiplying a binary number by eight it is sufficient to add three zeroes to it, and that the expressions (7-K); (15-K); (31-K) are obtained from the last three or four inverted digits of the number K expressed in binary code, as shown by the following examples (the last three digits in band I, the last four digits in band III)
| ______________________________________ |
| K = 3 = 011 7-K = 4 = 100 K = 10 = 1010 15-K = 5 = 0101 K = 18 = 10010 31-K = 13 = 1101 |
| ______________________________________ |
If the first expression between square brackets of the relations written hereinabove is sent to the inputs 11 to 19 of adder 716 and the second expression between square brackets is sent to the inputs 21 to 30 of adder 716, there remains to be added only the digit outside the square brackets, which is always 1, and it is added on the additional input 62. The first expression between square brackets, which is of the type (P-K) for the European VHF channels and P for the channels in UHF, is formed and sent to the inputs 11 to 19 in the following manner.
The number P is obtained from a series of logic gates, as will be explained hereinafter; the term -K or zero is obtained by connecting wires IV, V, VI and VII (which correspond to the four less significant digits of the number K) to the four less significant inputs of the left-hand side of adder 716, i.e. 11, 12, 13 and 14 through the four OR exclusive gates 725, 726, 727 and 728 and through the four NOR gates 729, 720, 719 and 718. Said NOR gates act as inverters (to obtain the minus sign for the European channels in the VHF range). As can be seen from FIG. 3, OR gate 729 is blocked in the UHF range and in Band I (in which three digits only have to be inverted). The other three gates 718, 719 and 720 are blocked in the UHF range, so that in the UHF range at the inputs 11, 12, 13 and 14 of adder 716 there arrive four zeroes.
The second expression between square brackets, which is of the type [8K+S], is obtained in a simple way by connecting the seven most significant inputs of the right hand side of adder 716, i.e. from 24 to 30, to the seven wires I-VII corresponding to the seven digits of the number K of the channel, and by connecting the remaining three inputs 21, 22 and 23 to logic gates for obtaining the number S (which is always less than 8).
The annexed Table II summarizes the functions of adder 716 on six European channels taken as an example.
Observing Table II, it can be seen that the first digit (starting from the right) of the second addend is always 1, said first digit is obtained by means of AND gates 730, 723 and 715, OR gate 732 and inverter 733. The second digit of the second addend is 1 in Band III, this being obtained by means of OR gate 721. The third digit is 1 in UHF; this is obtained by means of AND gate 722 and OR gate 717. In the first addend, the fifth digit is 1 in the channels over 15, which is obtained by means of OR gate 705; the sixth digit is 1 in the channels between 5 and 15, which information is already available from inverter 710; the seventh digit is always 1, except in Band III, while the eighth digit, instead, is 1 in Band III (such information being available upstream and downstream of inverter 714); the ninth digit is 1 in the UHF range and is obtained by means of AND gate 704.
Moreover, inverter 714 supplies a signal at level "1" when the selected channel is in Band III of the VHF range, and said signal is available at output 140; while the output of AND gate 704 supplies a signal at level "1" when the selected channel is in the UHF range, and said signal is available at output 141. The signals at outputs 140 and 141 are supplied to the tuner of the receiving set for controlling its band switch-over members. Processing unit 128 is also suitable for use with a tuner designed to recieve the signals of American television channels instead of European ones, as American channels are spaced by a 6 MHz step both in VHF and in UHF. Thus, the expressions of fo are all of the type fo =T+6K, where T is a fixed number, which expressions are obtainable easily by breaking the factor 6 into (4+2), i.e. fo =T+4K+2K, and where it is clear that to multiply by two in binary code it is sufficient to add a zero, and to multiply by 4 it is sufficient to add two zeroes; or, it is possible to obtain the factor 6 as (8-2), and so on.
Therefore, it is sufficient to send the signals representing said number K to a first counter whose least significant input receives a zero and to a second counter having two least significant inputs each of which receives a zero and then add to the binary signals representing said number T the binary outputs of the first and second counters.
At this point the set is therefore tuned to the theoretical frequency corresponding to channel 12.
If it is desired to effect a correction of the tuning, it is sufficient to press the push button + or the push button - of control panel 101. By pressing the push button +, a signal arrives at AND gate 115, which is enabled by the output at level "1" of NAND gate 124, so that counter 113 increases the count by one unit, i.e. the output passes from four to five. By pressing the push button -, a signal arrives at AND gate 117, which also is enabled by the output at level "1" of OR gate 112, and counter 113 shifts down the output by one unit, i.e. passes to three. Therefore, through buffer 122, the output of the counter, varied by one unit, arrives at processing unit 128 and at counter 126, whereby the number N correspondingly increases or decreases by one unit. As a result, the frequency fo increases or decreases by 0.25 MHz.
Gates 115, 117, 112 and 124 prevent counter 113 from rising above 7 and from dropping below zero, to avoid sudden jumps of tuning. In fact, with the output of counter 113 at the value 7, the output of NAND gate 124 passes to the value "0", so that gate 115 is blocked, thereby inhibiting the action of further pulses on connection 114 to increase the count.
When, instead, the output of counter 113 is at the value zero, the output of OR gate 112 passes to "0" and gate 117 is blocked, thereby inhibiting the action of further pulses on connection 116 to reduce the count.
(III)--If now one actuates push button M and then a numbered push button (for instance, the push button 3), control unit 104, which receives the signals, supplies in output:
on the first group 504-507 and second group 508-511 of four outputs, always the same digit as before, i.e. 1 and 2 respectively;
on the third group 512-515 of four outputs, the digit corresponding to the last push button actuated, i.e. 3;
"zero" on the thirteenth output 516 (buffer circuit 122 is enabled) and also on the fifteenth output 518 (the output of counter 113 is not varied);
"one" on the fourteenth output 517 (memory 108 is enabled to be "written").
More particularly, on pressing push button M, there is produced a signal at input 520, the light source 602 is switched on, the enabling inputs of latches 611 and 612 are disabled and, after the time τ2, the output of gate 620 becomes at level 1 together with output 517, as soon as the output of multivibrator 615 becomes at its low level again. Moreover, the output of multivibrator 615 becomes at its high level as soon as the push button M has been pressed and after having pressed the push button which bears the numeral 3, the number 3 is stored in latch 613 (always enabled) and after the time τ1 has elapsed (to ensure that latch 613 is charged), output 517 becomes at level 1, there being "zero" at input OD of latch 613 so that the number 3 appears at outputs 512 . . . 515.
The number 12, which arrives at the first eight inputs of memory 108, is therefore stored at the address three, the number 3 arriving from control unit 104 at the address inputs of memory 108, and moreover, by means of the last three inputs of memory 108, there is stored the number which corresponds to the tuning correction (for example, the number five, if the push button + has been pressed once before starting the storage stage).
When, after a suitable period of time, memory 108 has stored said information, the last seven outputs 512-518 of control unit 104 automatically return to zero, so that memory 108 is disabled, and moreover there is a pulse on the fifteenth output 518 for restoring the output of counter 113 on the present value of four.
More particularly, after a time (τ1 +τ3), there is a pulse at output 518, and multivibrator 608 is reset (through differentiator circuit 623 and through gate 643), light source 602 is extinguished to indicate that the storage has been accomplished and, after a further time τ2, the output of gate 626 returns to "zero" as does output 517 and the signal at input OD of latch 613, which brings to zero the outputs 512-515.
At this point, if a different pair of numbered push buttons of control panel 101 is pressed, the receiving set is thereby tuned to the corresponding frequency (i.e. the case in paragraph II recurs). Thus, it is possible to correct tuning by means of the push buttons + or - and, if desired, the new channel, with the tuning corrections, can be stored at another address of memory 108, i.e. the operation in case (III) recurs.
It is thus possible to select up to 100 different channels (00 to 99) and to store up to ten of them (in the addresses from 0 to 9 memory 108).
(IV)--By again actuating the push button D, the circuit arrangement returns to the situation previously described herein in paragraph (I) so that it is prepared for indirect station selection.
By then pressing one of the numbered push buttons of control panel 101 (for instance, the push button having the number 3), indirect station selection becomes operative and control unit 104 supplies the following outputs:
the first eight outputs 504-511 are insulated;
the digit corresponding to the actuated push button (for example 3) appears on the third group of four outputs 512-515;
on the thirteenth (516), fourteenth (517) and fifteenth (518) outputs there are present the same signals of the case in paragraph (I), i.e. "1", "1", and a short pulse.
More particularly, by pressing push button D, there is produced a signal at input 519, thus the output of multivibrator 609 returns to zero, light source 603 is extinguished, outputs 516 and 517 become "1" and the outputs of latch 613 are enabled, while buffer 649 is disabled and the outputs 504-507 and 508-511 are insulated. In this condition, by pressing push button 3 of control panel 101, the corresponding number is stored in latch 613 from inputs 500-503 and appears at outputs 512-515.
Under these conditions, the two buffer circuits 109 and 122 are both disabled and all the information to processing unit 128 and to counter 126 is supplied by memory 108 which is enabled to be read, this information being that which was previously stored in the case of paragraph (III) at the selected address, which in this case is the third address. Therefore, the receiving set becomes tuned to channel 12 (whose number is indicated also by display 106), with the tuning correction effected some time before. At this point, a different numbered push button of control panel 101 may be actuated, whereby memory 108 will supply new information to processing unit 128 and to counter 126 in order to obtain the tuning of the channel which has been stored therein.
(V)--The selection of the channels stored in memory 108 may, however, be effected also in the following different way. By pressing the push button + (or the push button -) of control panel 101, counter 113 increases by one unit (or reduces by one unit) the value of the output and, by means of gate 103, buffer 109 is enabled. Moreover, by means of the connection from the output of gate 103 to input 521 of control unit 104, a signal "one" arrives at input OD of latch 613 and the third group of outputs 512-515 of control unit 104 is insulated. Accordingly, memory 108 receives at the address inputs the number formed by counter 113 (for example, the number 5) and supplies to processing unit 128 and to counter 126, in the same manner as in case (IV), the information of the channel stored at the address five.
By successive actuations of the push button + (or -) it is possible to automatically scan sequentially up (or down) the ten addresses of memory 108, i.e. to tune in successively the ten stored channels.
The output of counter 113 no longer stops at seven or at zero, because when the thirteenth output of control unit 104 is at level "1" (i.e. memory 108 is conditioned to be read) gates 112 and 124 supply always signals at level "1", so that gates 115 and 117 are never locked. The number supplied by counter 113 remains at the address input of memory 108 even after the push button + or - has been released (and consequently buffer 109 is disabled again), inasmuch as it is maintained by a special latch conveniently contained in control unit 104.
Said special latch, designated in FIG. 2 by the numeral 560, has its input and output connected at control unit outputs 512, 513, 514 and 515, its IE terminal (Input Enable) connected at control unit input 521, and its OD terminal (Output Disable) connected at the output of gate 650. In this manner, when the push button + (or -) is actuated and there is a signal at level 1 at input 521, special latch 560 holds the number present at outputs 512, 513, 514 and 515 from counter 113, without transferring it to its output. When the push button + or - has been released, and the signal at input 521 becomes zero, the input of special latch 560 is insulated and the signal zero at its OD terminal transfers to the output and then to outputs 512, 513, 514 and 515, and therefore to the addresses of memory 108, the number previously stored from counter 113.
For a clearer explanation, the following Table IV is presented to show a recapitulatory scheme relating to the various cases described hereinabove.
| TABLE IV |
| ______________________________________ |
| Outputs of control Enablings of the unit 104 Memory 108 set circuits case 516 517 to be: enabling 103 109 122 |
| ______________________________________ |
II 0 0 written no no no yes III 0 1 written yes no no yes I-IV-V 1 1 read yes yes x no |
| ______________________________________ |
(x) is enabled by pressing one of the push buttons + or -.
Hence, the circuit arrangement according to the present invention affords a considerable convenience for the user, since in order to scan the various channels stored in memory 108 it is sufficient to actuate the push buttons + or -.
From the foregoing description, the advantages of the circuit arrangement according to the present invention are clearly apparent; of course, variations in what has been described by way of example will be possible to those skilled in the art, without departing from the scope of the invention.
Thus, for instance, it is possible to send to counter 113 a signal at clock frequency (derived, for example, from a division of the frequency produced by circuit 135) and to cause it to reach the input of counter 113 only when the output of gate 121 is at high level. In this way, as long as the push button + is pressed, the output of counter 113 increases, and as long as the push button - is pressed said output decreases. This occurs up to the value 7 (or down to zero) if a direct selection is carried out (as in case II, correction of tuning); and if an indirect selection is effected (as in case V, automatic rescan), the output of counter 113 will, instead, continue to cyclically vary from 0 to 9 in one or the other direction as long as one maintains the push button + or - pressed.
Therefore, with the circuit arrangement according to the present invention, it is possible to have: a direct station selection by selecting a channel with two digits of control panel 101 and with eventual correction of tuning, as per case (II); a storing of a selected channel, as per case (III); and an indirect station selection, either by selecting a desired cell of memory 108, as per case (IV), or by sequentially scanning the cells of memory 108, as per case (V).
GALAXI MOD. GALAXONE 27" CHASSIS GF77/M1702 Television set which displays analog data relevant to the operation of the television set on its video display:
The present invention relates to a television set which includes a picture display device, an alpha numerical character generating circuit connected to said device, a control device, means for determining analogue data relating to the operation of the set, such as volume, brightness and color, and means for displaying on said display device a combination of alpha numerical characters, supplied by said character generating device, indicating the values of said analogue data.
A control keyboard has six keys "V+", "V-", "L+", "L-", "C+" and "C-". The output of the keyboard is connected to a processing unit which is connected via a digital to analogue converter and switch to an alpha numerical character generator which is connected to a picture display device. When one of the six keys is pressed a combination of signals proportional to the analogue signal level of volume, brightness and color (V, L, C) is displayed on the picture display device. If one of the + keys is pressed, the corresponding analogue level is increased by 1/64 of maximum value, while a similar decrease is obtained by pressing one of the - keys.
a picture display device for displaying a video picture;
character generator means for generating signals representative of alphabetical, numerical and/or abstract characters;
said picture display device receiving said signals and displaying the alphabetical, numerical and/or abstract characters represented thereby; and
control means for determining the value of analog data, other than the tuning frequency of said television set, relating to the operation of said television set, and for causing said character generator means to generate signals representative of alphabetical, numerical and/or abstract characters which indicate said value of said analog data.
An integrated circuit for a programmable television receiver comprises a memory for storing a plurality of programs, a digital clock and a character generating circuit for generating character signals for displaying the programs in the memory and/or time of the digital clock on the screen of a television receiver. The integrated circuit uses dynamic circuits to reduce the number of elements required, and CMOS transistors to attain a lower power dissipation. 2. A television set, comprising:a picture display device for displaying a video picture;
character generator means for generating signals representative of alphabetical, numerical and/or abstract characters;
said picture display device receiving said signals and displaying the alphabetical, numerical and/or abstract characters represented thereby; and
control means for determining the value of analog data relating to the operation of said television set and for causing said character generator means to generate signals representative of alphabetical, numerical and/or abstract characters which indicate said value of said analog data, said control means also causing said character generator means to generate signals representative of alphabetical, numerical and/or abstract characters indicative of which of said data the user of said television set has last selected to adjust.
3. A television set, comprising: a picture display device for displaying a video picture;
1. An integrated circuit for use in a programmable television receiver comprising:
an oscillator to which a quartz crystal is to be externally coupled;
a digital clock coupled to said oscillator;
a memory for storing a plurality of programs each including time data and associated channel data and having a plurality of recirculating dynamic shift registers each adapted to store one program;
a character generating circuit coupled to said memory and adapted to generate character signals to permit the content of said memory to be displayed on the screen of a cathode ray tube of a television receiver;
circuit means coupled to the output of said oscillator to generate shift pulses for driving said recirculating dynamic shift registers in said memory;
time comparision means coupled to the outputs of said memory and said digital clock for comparing the time data in said memory and the time of said digital clock;
means to readout said channel data from said memory; and
means responsive to said time comparing means and said readout means to form a program execution output based on said channel data when a coincidence occurs between the time data in said memory and the time of said digital clock.
2. An integrated circuit according to claim 1, in which said character generating circuit comprises:an input for receiving horizontal timing pulses which synchronize with horizontal synchronizing pulses of the television receiver, have a frequency higher than that of the horizontal synchronizing pulse and provide a unit length in displaying characters in the horizontal direction of the cathode ray tube;
a horizontal component pulse generating circuit responsive to the horizontal timing pulses for generating horizontal component pulses which provide horizontal components of each character and have a horizontal one-digit display period, and clock pulses having the horizontal one-digit display period;
a horizontal display digit designation pulse generating circuit connected to said horizontal component pulse generating circuit to generate horizontal display digit designation pulses in response to the clock pulses;
a vertical component pulse generating circuit for generating vertical component pulses which provide vertical components of each character in response to the horizontal synchronizng pulse in the television receiver;
a multiplexer connected to said memory and said horizontal display digit designation pulse generating circuit to deliver hour data, minute data and channel data in the binary form from said memory in a predetermined sequence in response to said horizontal display digit designation pulses;
segment decoders for decoding the outputs of said multiplexer and generating segment outputs; and
output circuit means for generating character signals during each horizontal one-digit display period in response to the outputs of said segment decoders, said horizontal components pulses and said vertical component pulses.
3. An integrated circuit according to claim 2, in which said multiplexer includes a plurality of series-connected circuits each having a plurality of first MOS transistors of first channel type connected between each bit output of said multiplexer and a first potential point, the gate of one MOS transistor in each series circuit being connected to receive a binary signal having the same weight of each data and the gates of the remaining MOS transistors in each series circuit being connected to receive display digit designation pulses from said display digit designation pulse generating circuit; and a second MOS transistor of second channel type connected between the bit output and a second potential point, the gate of said second MOS transistor being connected to receive one clock pulse from said digit designation pulse generating circuit. 4. An integrated circuit according to claim 2, in which said segment decoders each include a plurality of first MOS transistors of first channel type connected between a decoder output and a first potential point, the gates of said first MOS transistors being connected to receive respective outputs of said multiplexer, and said output circuit means includes a second MOS transistor of the first channel type connected between a circuit point and each output of those segment decoders corresponding to the same horizontal component of the character and having a gate connected to receive from said vertical component pulse generating circuit a vertical component pulse associated with the horizontal component, a third MOS transistor of a second channel type connected between said circuit point and a second potential point and having a gate connected to receive one clock pulse from said display digit designation pulse generating circuit, a CMOS clocked inverter connected to said circuit point and adapted to be driven by clock pulses from said display digit designation pulse generating circuit which are different in phase from the clock pulse applied to the gate of said third transistor, and logic circuit means for gating the output of said clocked inverter in response to the corresponding horizontal component pulse. 5. An integrated circuit according to claim 1, in which said memory and digital clock are connected to a first power source line and said character generating circuit is connected to a second power source line.This invention relates to a program memory built-in integrated circuit for a programmable television receiver.
A programmable TV receiver capable of preliminarily setting the time and channel number of a desired television program has recently been developed. In this case, the television receiver is automatically switched ON and OFF when a programmed time comes. Most of such programmable TV receivers use a mechanically operated clock and memory and have the drawbacks that only a lesser number of programs can be memorized. The use of the electronic memory and digital electronic clock leads to a prominent increase in the number of storable programs and also provides an accurate counting of time. The use of electronic devices permits a stored content (time and channel number) to be displayed on the screen of CRT of a TV set. When such electronic memory and electronic digital clock are realized by discrete elements, a programming device is made bulkier, incurring a high cost. In order to attain miniaturization of the device at low cost the adoption of integrated circuit is considered. However, problem arises from the standpoint of a restricted chip size when all the circuits necessary for a programmable device is integrated into an integrated circuit.
In an electronic programmable device it is necessary to prevent the content of the memory and of the digital clock from being erased when an AC power source is turned OFF. In order to prevent such a situation, switching must be effected from the power source to a dry cell. In this case, the power consumption of the programmable device must be restricted.
It is accordingly the object of this invention to provide a CMOS integrated circuit which has a low power dissipation and incorporates a memory, digital clock, character generating circuit, etc., necessary for a programmable television receiver in a chip of practical size.
According to this invention there is provided an integrated circuit for use in a programmable television receiver comprising an oscillator to which a quartz crystal is to be externally coupled; a digital clock coupled to said oscillator; a memory adapted to store a plurality of programs each including a time data and a channel data and having a plurality of recirculating dynamic shift registers each for storing one program; a character generating circuit coupled to said memory and adapted to generate character signals to permit the content of said memory to be displayed on the screen of a cathode ray tube of a television receiver; circuit means coupled to the output of said oscillator to generate shift pulses for driving said recirculating dynamic shift registers in said memory; time comparison means coupled to the outputs of said memory and said digital clock for comparing the time data in said memory and the time of said digital clock; and means responsive to said time comparing means to form a program execution output when a coincidence occurs between the time data in said memory and the time of said digital clock.
This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
character generator means for generating signals representative of alphabetical, numerical and/or abstract characters;
said picture display device receiving said signals and displaying the alphabetical, numerical, and/or abstract characters represented thereby; and
control means for determining the value of analog data relating to the operation of said television set and for causing said character generator means to generate signals representative of alphabetical, numerical and/or abstract characters which indicate said value of said analog data, said alphabetical, numerical and/or abstract characters consisting of a number of characters proportional to the value of said analog data.
4. A television set, comprising:a picture display device for displaying a video picture;
character generator means for generating signals representative of alphabetical, numerical and/or abstract characters;
said picture display device receiving said signals and displaying the alphabetical, numerical and/or abstract characters represented thereby; and
control means for determining the value of analog data relating to the operation of said television set and for causing said character generator means to generate signals representative of alphabetical, numerical and/or abstract characters which indicate said value of said analog data, at least one of said alphabetical, numerical andl/or abstract characters indicating the type of data concerned.
5. A television set as claimed in claim 2, wherein said visual indication of which of said data the user has last selected to adjust includes a given additional character alongside said data the user has selected to adjust. 6. A television set as claimed in claim 2, wherein said visual indication of which of said data the user has last selected to adjust includes a given color for the data the user has selected to adjust. 7. A television set as claimed in claim 1, wherein said control means includes a push-button panel for generating digital electronic signals, in response to actuation thereof by the user of said television set, which instructs said control means to change the value of said analog data, said control means also causing said character generator means to generate signals representative of alphabetical, numerical and/or abstract characters which indicate the value of said adjusted analog data and also indicate that said analog data has been adjusted. 8. A television set as claimed in claim 7, wherein said control means generates digital electronic signals indicative of said adjusted value of said analog data, said control means further including a digital to analog converter for converting said digital signal into an analog signal, and a signal switch controlled by said control means for applying said analog signal to that portion of said television circuit which will cause the value of said analog data to assume said adjusted value. 9. A television set as claimed in any one of claims 1-6, additionally comprising a memory for memorizing values of said analog data. 10. A television set as claimed in claim 9, wherein the television set includes a tuning arrangement, capable of memory selection in which each of a series of keys is associated with a preselected and memorised television channel, and a memory circuit capable of memorising, for each of the said channels, number signals representing the preselected values of the said analog data. 11. A television set as claimed in any one of claims 1-6, additionally comprising means for producing an alarm when the said combination of alphabetical, numerical and/or abstract characters coincides with one or more preset combinations.BACKGROUND OF THE INVENTION
The present invention relates to a television set which includes a picture display device, an alpha numerical character generating circuit connected to the said device, a control device and means for checking analogue data relating to the operation of the set, such as volume, brightness and color. The system commonly used on television receivers for tuning into the required channels is the so-called FREQUENCY SYNTHESIZER system. This system, made possible by the advent of integrated circuits, offers a number of advantages over other known systems, such as the conventional potentiometer type MECHANICAL MEMORY systems and the more recent so-called VOLTAGE SYNTHESIZER systems. The frequency synthesizer system is fully electronic enabling any channel to be called up directly by the user who formulates the channel number on a keyboard or other control device. The system usually consists of a quartz-controlled reference oscillator, a phase lock loop, a programmable divider and a computer which supplies the number to be sent to the programmable divider in response to the number of the channel set by the user. Thanks to the phase lock loop, for each channel number set by the user, the frequency of the local oscillator on the set is kept so stable and accurate that the set is tuned with great precision to the corresponding channel signal. For further details concerning frequency synthesizer tuning systems, refer to the article entitled "A Frequency Synthesizer for Television Receivers" by E. G. Breeze, published in the November, 1974 issue of the "Transactions BTR" Magazine, or "Digital Television Tuner Uses MOS LSI and Non Volatile Memory" by L. Penner, published in the April 1, 1976 issue of "Electronics".
The frequency synthesizer system lends itself well to a number of different modes of television chanel tuning;
direct selection by formulating the required channel number as described above television channels are numbered: for example, in the European C.C.I.R. standard, V.H.F. band channels are numbered from 2 to 12 and U.H.F. band channels from 21 to 69; in the American Standard, VHF channels are numbered from 2 to 13 and UHF from 14 to 83).
memory selection: each of a certain set of keys corresponds to a preselected and memorised channel;
automatic scanning of all the channels of a given standard, or of all the channels contained in the memory or continuous scanning of all the frequency bands involved.
The first application enables immediate, direct selection of any one of the channels in the relative standard (60 in Europe, 82 in America).
the second enables faster detection of one of a limited number of preferred channels.
The third is a fast, simple way of finding out which standard channels can be received, which channels have been memorised and whether other broadcasting stations exist on non-standard frequencies such as the private broadcasting stations in Italy (there are currently over a hundred operating).
Examples of frequency synthesizer systems with this wide range of selection modes are described in West German Patent Applications No. 26 45 833 and 26 52 185 and, in particular, Italian Patent Application No. 69.950-A/77 filed on Dec. 30, 1977 by the present applicant. All these modes, which are particularly useful in areas where a number of broadcasting stations can be received, require highly complex control equipment which many users may find difficulty in operating. This is even more so if, besides emitter selection and standard receiver adjustment controls (volume, brightness, colour, etc.), provision is also made for additional accessory functions such as a digital clock which requires additional setting controls. Provision of a character generator capable of displaying alpha numerical data on the television screen could prove beneficial in connection with this problem. The aim of the present invention is to provide a television receiver enabling the many functions described above to be effected simple and inexpensively with as little operating difficulty as possible on the part of the user.
BRIEF SUMMARY OF THE INVENTION
According to the present invention there is provided a television set including a picture display device, an alpha numerical character generating circuit connected to said device, a control device and means for determing analogue data relating to the operation of the set wherein means are provided for displaying on the picture device a combination of alpha numerical character, supplied by said character generating circuit, indicating the values of said analogue data.
BRIEF DESCRIPTION OF THE DRAWING
The invention will now be described by way of example only and with reference to the accompanying drawings, in which:
FIG. 1 shows the block diagram of part of a television receiver according to the present invention;
FIGS. 2, 3 and 4 show block diagrams of elementary logic functions performed by the circuits on the device according to the present invention;
FIGS. 5 and 6 show a number of FIG. 1 circuits in greater detail.
FIG. 7 shows the block diagram of an improved version of the FIG. 1 circuit-only the differing features are shown.
DETAILED DESCRIPTION OF THE INVENTION
Referring now to FIG. 1,
indicates a receiving aerial connected to varicap-diode tuner 2 at the output of which a signal converted to intermediate frequency IF is available. The tuner is the known type and consists essentially of a selective amplifier stage, a mixer circuit and local oscillator circuit.
One output on the local oscillator circuit is connected to a first frequency-divider circuit 3 which divides by a fixed number N1 and whose output is connected to the signal input of a second divider 4 which divides by a variable number N with 12-bit programming, which means it can divide by any number from 1 to 212.
The output of divider 4 is connected to a first input of phase-frequency comparator circuit 5 to whose second input a reference signal generated by quartz generator 6 is sent via a third frequency-divider circuit 7. The output of comparator circuit 5 is connected to the tuner circuit varicap diode voltage control input via amplifier and filtering circuit 8.
Number 10 indicates a control unit consisting of a keyboard which, besides the control keys not shown, such as the on/off switch and volume, brightness, contrast and color adjustment controls, also contains 10 number keys marked 0 to 9 (or letter keys marked A, B, C, D, E, F, G, H, I, L) and 7 auxiliary keys marked +, -, T, C, OR, M, CT (or +, -, R1, R2, R3, R4, CT).
This control unit is connected to a first group of eight input-output terminals of processing unit 11 and to the address inputs of memory circuit 12. The processing unit 11 also has a second set of eight input-output terminals connected to the data input-output terminals of memory circuit 12 and the inputs of character generator circuit 16. This, in turn, is connected to display device 9 (including the kinescope on the set) while a third group of 16 terminals is connected to:
12 programming inputs of 12-bit divider 4;
2 band-switch inputs (U and BIII) of tuner 2;
1 control input of character generator circuit 16;
a first input of combiner circuit 14.
Memory circuit 12 has further control terminals connected to the output of combiner circuit 14 which receives a signal from circuit 11 at a second input and a signal from on-detector circuit 15 at a third. Circuit 15 receives a signal from the power mains the television set is connected to and also has its output connected to a RESET input of circuit 11. Memory 12 and the low-current-absorption CMOS combiner circuit 14 are connected to a local battery supply source 13. The circuit operates as follows:
Circuits 3, 4, 5 and 8, together with the varicap-diode-controlled local oscillator (VCO) in tuner 2, form a phase lock loop controlled by the reference signal generated by quartz generator 6 and divided by divider 7 according to the known technique.
The function of divider circuit 3 is to reduce the frequencies involved to more easily processable levels while programmable divider 4 enables locking to be affected for a number of local oscillator frequencies, that is, it acts as a frequency synthesizer circuit.
In fact, after selecting division number N for divider circuit 4, phase-frequency comparator 5 supplies circuit 2, via amplifier 8, with voltage for obtaining the following condition: f6/N2 =f2/N1.N (1)
or f2=P.N (2)
in which f2 is the oscillation frequency of the local oscillator circuit in tuner 2, f6 is the oscillation frequency of reference oscillator circuit 6, N2, N1 and N are the division ratios of dividers 3, 6 and 4 respectively, while P=f6 N1/N2 indicates the system pitch, that is, the amount by which local oscillator frequency varies alongside variations in number N.
The receiver must be capable of tuning into broadcasting stations of a given transmission standard, e.g. C.C.I.R./B-G, with channeling as agreed at the 1961 European Radio Broadcasting Conference in Stockholm, that is, broadcasting stations with one-step spacing between adjacent 7 MHz channels on the I and III (VHF) bands and 8 MHz channels on the IV and V (UHF) bands with a 5 MHz video signal band width. These broadcasting stations fall within television channels 2 and 69 (video carrier frequencies 48.25 and 855.25 MHz respectively) with 38.9 MHz intermediate frequency IF. This means the local oscillator on the tuner must be capable of generating frequencies ranging from 87.15 to 894.15 MHz. A 0.25 MHz pitch was selected which, according to equation 2 gives the following values for the two abovementioned channels: ##EQU1## By varying number N between this maximum and minimum, any television channel on the VHF and UHF bands can be tuned into with a maximum error of 125 KHz. Not all of this frequency range can be utilized so the tuner is provided with two band switch inputs U (UHF/VHF) and B (BIII/BI) to ensure only effective bands are covered. Divider 3 is a high-speed ECL type which divides by 64 (SP 8750). Divider 4 is a programmable TTL which can operate up to frequencies of about 15 MHz (3×SN74LS191). Circuits 5, 6 and 7 consist of an SP8760 integrated circuit with 250 KHz frequency quartz and N2 =64 division ratio so that comparator circuit 5 operates at 3906.25 Hz frequency which corresponds to a quarter of line frequency. The function of amplifier and filter 8 is to adapt the output level of comparator 5 (max. 5 V) to the requirements of tuner 2 (max. 30 V) and provide the best possible filtering and lock speed conditions.
Circuit 11, which consists of a microprocessor unit, is designed to generate, among other things, N numbers and bandswitch signals for tuning into specific television broadcasting stations on the basis of data relative to the signals being tuned into supplied by the user from control keyboard 10. The said circuit 11 is also capable of supplying or receiving signals from memory 12 and sending signals to character generating circuit 16. Number N is calculated using the following equation: N=(KF+C)4+S (1)
The operations shown are performed by means of a series of elementary operations by an arithmetical-logic unit (ALU) on the basis of instructions contained in a (ROM) program memory contained in the said processing circuit 11 and performed, in this case, using an F8 microprocessor. Constant correction C and factor F depend on the band selected; K is the channel number according to the said standard and the S variable can be changed for performing fine tuning corrections.
If channel number K is changed, we only get the frequencies corresponding to standard channels with a pitch equal to F (8 MHz for UHF and 7 for VHF), whereas one-unit variation of S causes frequency shifts of 0.25 MHz. With appropriate control from the keyboard, various modes are possible for tuning into a given broadcasting station partly using known methods.
Whenever any one of the keys is pressed, processing unit 11 sends an ISO-coded 48-character sequence to character generator 16 which is displayed on the television screen in a three 16-character line arrangement.
This sequence always includes a time indication (hours, minutes, seconds). The remainder consists partly of fixed data from the ROM program memory (e.g. "CHANNEL" and "KEY" shown in FIG. 1) and partly of variable data depending on the controls activated by the user and the situation resulting from them which is memorized in a memory buffer inside unit 11 (e.g. the letter T indicating operation mode in the top right-hand corner of FIG. 1; FIGS. 21-01, also in FIG. 1 following the "CHANNEL" indication which show the channel number and tuning correction).
The time indication is corrected automatically each second even if no key is pressed. When one of the "T", "C", "OR" or "M" keys is pressed, the corresponding operation mode is set and memorized in the memory buffer of processing unit 11. At the same time, one or more question marks are entered into the buffer at appropriate points to guide the user on the next control operation. The content of the buffer is then transmitted, of course, to the character generator and displayed on the television screen.
A few examples will now be given to give a clearer idea of this point.
When key "T" is pressed, the display shows:
| ______________________________________ |
| OO:MM:SS T KEY ? |
| ______________________________________ |
In this way, the user is informed that he has selected mode "T" (memory selection) and that the device expects a number key to be pressed (that is, an emitter memory key number). N.B.: OO:MM:SS in the above example stands for the time indication (hours, minutes, seconds).
When key "C" is pressed, the display shows:
| ______________________________________ |
| OO:MM:SS C CHANNEL ?? |
| ______________________________________ |
In this way, the user is informed that he has selected mode "C" (direct selection) and that the device expects two number keys to be pressed (required channel number).
If the number formulated by these two keys corresponds to a channel in the standard, the number will be displayed in place of the two question marks beside the "CHANNEL" indication. If the channel number does not correspond to one in the standard, the display shows:
| ______________________________________ |
| OO:MM:SS C CHANNEL ?? 88 |
| ______________________________________ |
In this way, the user is informed that the control set (channel 88 not covered by the C.C.I.R. standard) has not been performed and that the device is awaiting further instructions. When key "OR" is pressed, the display shows:
| ______________________________________ |
| ??:??:?? T CHANNEL 21+01 KEY O OR |
| ______________________________________ |
This tells the user that the television set is still set to mode "T", that it is tuned to channel 21 with a tuning correction equivalent to one frequency shift over 250 KHz, memorized on key 0, and that the device expects six number keys to be pressed one after the other corresponding to the hours, minutes and seconds the clock is to be reset to. As the said six keys are pressed, the corresponding number is displayed in place of the "OR" indication and pairs of numbers replace the "??" corresponding to the hours, minutes and seconds, provided the numbers are acceptable. In fact, the device checks the set numbers and, if the hour number is over 23 or the number corresponding to the tens of the minutes or seconds over 5, the two numbers (hours, minutes or seconds) are rejected and the two question marks are left displayed to inform the user that the device is waiting for another pair of acceptable numbers to be set. After the operation has been performed, the clock starts counting from the time set by the user. The device is so designed that, following a power cut, a series of zeros is displayed for the hours, minutes and seconds and the clock remains in this condition to inform the user that the power supply has temporarily been cut off.
When the "M" key is pressed, the display shows:
| ______________________________________ |
| OO:MM:SS T CHANNEL 21+01 KEY # ? M |
| ______________________________________ |
This tells the user that the television is still set to "T" mode, that it is tuned to channel 21 with +01 tuning and that the set is waiting for a number key to be pressed to memorise the channel tuned into. If key "0" is pressed, for example, the display shown in FIG. 1 appears and the said channel is associated with key "0" for memory selection. If key "+" is pressed, the display shows:
| ______________________________________ |
| OO:MM:SS T CHANNEL 21+02 KEY O |
| ______________________________________ |
This tells the user that the television is still set to "T" mode and the excess tuning corrections are being made, that is, towards the audio carrier of the received video signal. Circuit 11 supplies the programmable divider circuit, with a suitable modified number N and this tuning condition is automatically associated in the memory with key "0". Operation is similar when key "-" is pressed except for the direction of the tuning adjustment (towards the video). Once nominal tuning is obtained, the "+" sign and the following number are cancelled while, for more defective tuning conditions, the "-" sign appears followed by the number of displacements made. The system is so designed to limit maximum variations to the -16 to +15 range. Of course, the tuning correction can be made in the same way even with the set in the direct selection mode (mode "C").
In this case though the operation does not involve automatic memorization. For the channel and obtained tuning condition to be memorized, the "M" key must be pressed, followed by a number key.
When the "CT" (keyboard switch) key is pressed, the display shows:
| ______________________________________ |
| OO:MM:SS *T* CHANNEL 21+01 KEY O |
| ______________________________________ |
This tells the user ("*" beside the mode indication) that the device is set to perform a further series of functions corresponding to the second indication on each key. Following this operation, the processing circuit 11 supplies character generator 16 with a switch signal to switch the color of the writing on the screen or the background color so as to make it even more clear to the user that the controls available from that time on correspond to second key indications (this applies, of course, to color television sets).
If one of the keys marked "A" to "L" is pressed, the display shows:
| ______________________________________ |
| OO:MM:SS *C* CHANNEL A |
| ______________________________________ |
This tells the user that the television is set to mode "C" but, in this case, channels can be selected directly according to the Italian standard by pressing a single key with indication of the received channel.
When one of keys R1, R2, R3 or R4 is pressed, the display shows, for example:
| ______________________________________ |
| OO:MM:SS *1* CHANNEL 21+01 KEY O RA |
| ______________________________________ |
This tells the user that the set is performing an automatic scanning operation, for example type 1, or is scanning all the channels in the memory.
Scanning progresses automatically every two seconds with indications in each case of the key number and associated channel. At the same time, processing circuit 11 generates the relative N numbers for receiving the channel. Scanning stops when any other key is pressed. If the "+" or "-" key is pressed, the device remains set for manual advance or reversing (every time the "+" key is pressed, the key number is increased and decreased every time the "-" key is pressed). If the "CT" key is pressed, the device switches back to the first keyboard and awaits further instructions, in particular, tuning correction or memorization controls. Similarly, if key R2 is pressed after selecting the second keyboard using the "CT" key, this starts a type 2 scanning operation of all the standard channels (one switch per second). This can be stopped in the same way as type 1 scanning.
If key R3 is pressed, this starts a continuous scanning operation of the frequency band in 1 MHz steps, that is, 4 fine tuning switches per second, to detect any emitters operating over non-standard frequencies. The same type of scanning operation, though at reduced speed (one switch every two seconds), is started pressing key R4.
The "KEY" indication is not displayed during type 2, 3 and 4 scanning operations.
Display or omission of the fixed "CHANNEL" and "KEY" indications depends on whether the indication or blank sectors of the ROM memory are utilized. Circuit 11 also comprises a timer which, 15 seconds after the last key has been activated, supplies a switch signal (bit 6 port 1) to character generator 16 which reduces the display to one line and also halves the height of the characters (7 instead of 14 television lines) to reduce disturbance to the picture. This switch signal, of course, is not supplied during automatic scanning or clock adjustment.
To prevent memorized data being lost during a power cut, provision is made for a battery-supplied outside RAM memory 12. Whenever memorization operation is performed, processing unit 11 updates the information in the RAM memory. When power supply returns to normal, the same unit 11 calls up the data memorized in the RAM memory. "ON RESET" circuit 15 and combiner circuit 14 protect the data contained in RAM memory 12 during transient states between power supply failure and restoration.
Operation of processing unit 11 is shown more clearly in the elementary logic function block diagrams in FIGS. 2, 3 and 4.
FIG. 2 shows operation mode and relative indication selection;
FIG. 3 shows updating of the data in outside RAM memory 12;
FIG. 4 shows data being called up from the outside RAM memory following restoration of the power supply.
Number 20 in FIG. 2 indicates a timer which sets a switch circuit, 22, with its output usually towards bloc
k 23 and supplies an RTI signal to block 21 which reads the controls set on the keyboard. Block 21, via switch 22, supplies a signal to block 23 which ascertains the presence of a new order. The "NO" output supplies the RTI signal which reactivates reading block 21 while the "YES" output activates block 24 which ascertains whether the key pressed was a mode key. The "NO" output of block 24 activates block 25 which examines the operation mode selected and, in turn, activates block 26 which, depending on the mode chosen, combines and supplies the indication sequence to the character generator for display. Block 26 then activates block 27 which examines the number keys pressed and activates block 28 which ascertains whether the corresponding order is feasible.
The "NO" output of the said block 28 (control not feasible, e.g. the number does not correspond to a standard number channel) activates a following block 34 which inserts question marks at appropriate points in the buffer to inform the user that the control is not feasible and transmits them to character generator 16 (FIG. 1). Block 34 then supplies an RTI signal to block 21 which reads the keyboard once more awaiting further instructions.
The "YES" output of block 28 activates block 29 which sends the channel or key members to the buffer, usually the numbers of the order received, transmits the numbers to the character generator and, finally, activates block 30 which calculates number N according to equation (3) and sends this number to programmable divider 4 (FIG. 1) to obtain the required tuning. Finally, block 30 supplies the RTI signal to block 21.
The "YES" output of block 24 activates block 36 which inserts the indications and question marks in the buffer and transmits them to the character generator (as described already). Block 36 then supplies block 21 with the RTI signal. After a set length of time (about 4 milliseconds), depending on circuit 20, switch 22 positions itself with its output towards count circuit 31 which, after a set number of pulses (about 250) per second, supplies a signal to block 32 which updates the clock numbers in the buffer and activates block 33 which sends the data contained in the buffer to the character generator and then supplies an RTI signal to block 21. Number 40 in FIG. 3 indicates a block for ascertaining whether the operation selected involves memorization. The "NO" output supplies a signal which activates block 25 (FIG. 2) while the "YES" output activates in turn:
block 41, which examines the number of the key pressed;
block 42, which memorises the channel number and tuning in the registers corresponding to the said key;
block 43, which supplies an enabling signal (C.E.) and a first address for the outside memory circuit 12;
block 44, which supplies the channel number data and a memorizing pulse (WRITE) to the same circuit 12;
block 45, which supplies the new address;
block 46, which supplies the tuning data and memorizing pulse to memory 12.
Number 50 in FIG. 4 indicates a block which, following an "ON RESET" signal from circuit 15 in FIG. 1, supplies an output enabling (O.E.) signal to memory 12 as well as a signal for activating in turn:
block 51, which supplies the address to memory 12;
block 52, which reads the data from memory 12 and loads it into the registers in unit 11 of FIG. 1;
block 53, which calculates the new address;
block 54, which ascertains whether all the cells in memory 12 have been read.
The "NO" output of block 54 supplies a signal for activating block 51 once more. The "YES" output activates block 55 which sets to mode "T" (memory selection) and key "O" and supplies an activation signal to block 25 of FIG. 2.
For further information concerning operation of the device, refer to Italian Patent Application n. 69950-A/77, already mentioned, which describes a device partly similar to the present one. On the actual device, a Fairchild F8 microprocessor unit was chosen for processing unit 11 which consists of a 3850 C.P.U., 3861 P.I.O., 3853 S.M.I. and two PROM F93448 memories. Each of the said two PROM memories consists essentially of a connection matrix with a 512×8 format, input and address decoding circuits and output buffer circuits.
Each connection may be open or closed and represents permanent elementary data (bit) 1 or 0 respectively. Each group of 8 connections, addressed by one of the 512 address input combinations, represents an elementary 8-bit instruction or word (byte). By applying all the possible address combinations at the input, all the data contained in the ROM can be obtained at the output in word form.
These connections are described in the following tables for the circuit. The left-hand columns show the addresses, using hexadecimal notation, and the right-hand ones the connections of the corresponding memory cell. Number 1 refers to an open connection with logic 1 at the output while 0 refers to a closed connection.
As each memory cell consists of 8 connections, this means it can be represented with a combination of 8 binary figures. For the sake of simplicity, the hexadecimal system was used on the following tables, so that, for example, EA for base 16, which corresponds to 11101100 of base 2, indicates that the corresponding memory cell has connections 1, 2, 3, 5 and 6 open and the rest closed.
| TABLE 1 |
| ______________________________________ |
| ADDRESS CODE ADDRESS CODE |
| ______________________________________ |
0000 70 000C 04 0001 B5 000D 6A 0002 B1 000E 7A 0003 B6 000F 5C 0004 BE 0010 6D 0005 BF 0011 5C 0006 B4 0012 7F 0007 65 0013 58 0008 6F 0014 18 0009 5E 0015 07 000A 8F 0016 67 000B FE 0017 5C 0018 66 0031 70 0019 5E 0032 BD 001A 8F 0033 5B 001B FE 0034 B5 001C 20 0035 90 001D 10 0036 12 001E 0B 0037 1B 001F 24 0038 A5 0020 90 0039 EB 0021 B5 003A 84 0022 A4 003B FD 0023 5C 003C 59 0024 0A 003D 21 0025 1F 003E 10 0026 25 003F 49 0027 28 0040 94 0028 94 0041 19 0029 F5 0042 EB 002A 7C 0043 5B 002B 06 0044 91 002C 15 0045 F3 002D 5A 0046 73 002E B1 0047 BE 002F 72 0048 1A 0030 BC 0049 67 004A 4B 0063 03 004B 21 0064 66 004C 1F 0065 6B 004D 59 0066 5C 004E 6F 0067 69 004F 25 0068 5C 0050 09 0069 29 0051 81 006A 02 0052 1A 006B 06 0053 25 006C 47 0054 0F 006D 56 0055 81 006E 49 0056 32 006F 57 0057 29 0070 5E 0058 02 0071 46 0059 03 0072 5D 005A 1A 0073 E8 005B EB 0074 84 005C 5B 0075 1D 005D 21 0076 66 005E 10 0077 6A 005F 20 0078 00 0060 FA 0079 CC 0061 94 007A 91 0062 02 007B 17 007C 7F 0095 25 007C 5C 0096 0D 007E 6E 0097 84 007F 03 0098 0A 0080 5D 0099 81 0081 5C 009A 23 0082 67 009B 25 0083 5E 009C 0F 0084 8F 009D 84 0085 FE 009E 40 0086 90 009F 29 0087 E2 00A0 01 0088 25 00A1 3B 0089 0B 00A2 67 008A 81 00A3 6C 008B 51 00A4 03 008C 06 00A5 5C 008D 03 00A6 7D 008E 5E 00A7 66 008F 5D 00A8 6A 0090 7F 00A9 06 0091 5E 00AA 55 0092 02 00AB 20 0093 67 00AC 10 0094 6F 00AD 52 00AE 20 00C7 E4 00AF D3 00C8 5C 00B0 5C 00C9 67 00B1 47 00CA 6C 00B2 E8 00CB 47 00B3 94 00CC 5C 00B4 03 00CD E8 00B5 57 00CE 84 00B6 56 00CF 9A 00B7 46 00D0 47 00B8 15 00D1 13 00B9 C7 00D2 24 00BA 51 00D3 10 00BB 90 00D4 0B 00BC 1D 00D5 4D 00BD 55 00D6 51 00BE 03 00D7 4C 00BF 5E 00D8 52 00C0 8F 00D9 29 00C1 FE 00DA 01 00C2 66 00DB 84 00C3 5E 00DC 90 00C4 5C 00DD 4A 00C5 6A 00DE 66 00C6 20 00DF 4C 00E0 E8 00F9 13 00E1 84 00FA B5 00E2 35 00FB 05 00E3 67 00FC 24 00E4 20 00FD 10 00E5 DD 00FE 0B 00E6 5C 00FF 72 00E7 6B 0100 59 00E8 4D 0101 41 00E9 CE 0102 5D 00EA 1F 0103 B4 00EB 84 0104 01 00EC 2B 0105 EA 00ED 20 0106 B5 00EE F3 0107 EA 00EF 5D 0108 B5 00F0 47 0109 1F 00F1 5C 010A B5 00F2 E8 010B 05 00F3 84 010C 42 00F4 31 010D 5C 00F5 A1 010E 39 00F6 EA 010F 94 00F7 B1 0110 F3 00F8 4C 0111 70 0112 B4 0113 B5 012C 52 0114 A1 012D 6B 0115 EA 012E 4E 0116 B1 012F C8 0117 70 0130 81 0118 57 0131 55 0119 45 0132 6C 011A 06 0133 70 011B 03 0134 CC 011C 67 0135 81 011D 6F 0136 BC 011E 5E 0137 70 011F 5C 0138 57 0120 6C 0139 90 0121 4C 013A 4A 0122 E8 013B 49 0123 94 013C 23 0124 60 013D 0E 0125 90 013E 94 0126 5B 013F 1E 0127 13 0140 20 0128 18 0141 E2 0129 24 0142 5E 012A 16 0143 20 012B C2 0144 DF 0145 5C 015E E8 0146 6B 015F 84 0147 4C 0160 21 0148 C8 0161 46 0149 91 0162 25 014A 04 0163 05 014B 03 0164 91 014C 5D 0165 0C 014D 5C 0166 00 014E 65 0167 24 014F 68 0168 03 0150 4A 0169 04 0151 04 016A 24 0152 7F 016B 65 153 5D 016C 0B 0154 5C 016D 46 0155 6B 016E 5D 0156 5D 016F 47 0157 5C 0170 5C 0158 6E 0171 7F 0159 5D 0172 57 015A 5D 0173 68 015B 90 0174 4D 015C 25 0175 15 015D 46 0176 CC 0177 25 0190 53 0178 23 0191 41 0179 91 0192 05 017A D4 0193 25 017B 90 0194 01 017C 05 0195 81 017D 7F 0196 E7 017E 66 0197 25 017F 5E 0198 79 0180 5C 0199 91 0181 29 019A E3 0182 02 019B F8 0183 06 019C 25 0184 67 019D 09 0185 6B 019E 91 0186 03 019F DE 0187 5E 01A0 70 0188 8F 01A1 CE 0189 FE 01A2 91 018A 66 01A3 04 018B 5E 01A4 03 018C 5D 01A5 5D 018D 67 01A6 5E 018E 70 01A7 66 018F 50 01A8 41 01A9 25 01C3 C9 01AA 69 01C4 51 01AB 81 01C5 25 01AC 0B 01C6 14 01AD F8 01C7 91 01AE 2A 01C8 4A 01AF 03 01C9 13 01B0 E0 01B1 8E 01CA C1 01B2 24 01CB 13 01B3 02 01CC C1 01B4 51 01CD 59 01B5 16 01CE 01 01B6 53 01CF 25 01B7 41 01D0 69 01B8 14 01D1 81 01B9 5D 01D2 07 01BA 13 01D3 03 01BB 59 01D4 5D 01BC 13 01D5 79 01BD 13 01D6 8E 01BE C9 01D7 16 01BF 59 01D8 5E 01C0 41 01D9 41 01C1 F8 01DA 25 01C2 5E 01DB 04 01DC 20 01EE 00 01DD 45 01EF 38 01DE 81 01F0 29 01DF 05 01F1 00 01E0 74 01F2 37 01E1 50 01F3 29 01E2 20 01F4 00 01E3 AF 01F5 48 01E4 C3 01F6 29 01E5 90 01F7 00 01E6 2A 01F8 A2 01E7 FF 01F9 29 01E8 FF 01FA 00 01E9 FF 01FB C9 01EA FF 01FC 29 01EB FF 01FD 01 01EX FF 01FE 84 01ED 29 01FF FF |
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| TABLE 2 |
| ______________________________________ |
| ADDRESS CODE ADDRESS CODE |
| ______________________________________ |
0200 29 0203 29 0201 02 0204 03 0202 DD 0205 26 0206 29 0220 20 0207 02 0221 52 0208 7A 0222 C9 0209 FF 0223 51 020A FF 0224 40 020B FF 0225 19 020C FF 0226 13 020D FF 0227 13 020E FF 0228 50 020F FF 0229 70 0210 90 022A C2 0211 11 022B 81 0212 20 022C 04 0213 20 022D 70 0214 C1 022E 90 0215 51 022F 07 0216 13 0230 25 0217 13 0231 20 0218 13 0232 81 0219 59 0233 03 021A 41 0234 20 021B 14 0235 20 021C 12 0236 52 021D 24 0237 41 021E 08 0238 14 021F 50 0239 12 0252 72 023A 12 0253 C9 023B C0 0254 18 023C 50 0255 B0 023D 41 0256 01 023E 13 0257 51 023F 13 0258 67 0240 C2 0259 68 0241 59 025A 03 0242 40 025B C2 0243 19 025C 84 0244 18 025D 1D 0245 B1 025E 50 0246 01 025F 20 0247 25 0260 FB 0248 70 0261 5C 0249 84 0262 81 024A 08 0263 08 024B 25 0264 20 024C 74 0265 FD 024D 84 0266 5C 024E 04 0267 40 024F 70 0268 18 0250 90 0269 1F 0251 02 026A 50 026B 20 0284 25 026C 67 0285 C9 026D 59 0286 91 026E 70 0287 12 026F D9 0288 84 0270 30 0289 04 0271 94 028A 29 0272 FD 028B 01 0273 69 028C ED 0274 59 028D 45 0275 14 028E 06 0276 5D 028F 70 0277 49 0290 57 0278 F8 0291 20 0279 5C 2092 FD 027A 7F 0293 54 027B 53 2094 03 027C A1 0295 67 027D 22 0296 6F 027E 40 0297 5E 027F B1 0298 5C 0280 28 0299 29 0281 02 029A 01 0282 9C 029B F0 0283 00 029C 2A 029D 03 02B6 CC 029E D0 02B7 81 029F 20 02B8 03 02A0 80 02B9 7A 02A1 B4 02BA 8E 02A2 65 02BB 66 02A3 68 02BC 6E 02A4 74 02BD 4C 02A5 59 02BE 24 02A6 7C 02BF 30 02A7 50 02C0 18 02A8 16 02C1 B4 02A9 B4 02C2 CA 02AA CA 02C3 B4 02AB B4 02C4 0A 02AC 39 02C5 1F 02AD 94 02C6 0B 02AE FA 02C7 30 02AF 0A 02C8 94 02B0 25 02C9 F4 02B1 34 02CA CA 02B2 94 02CB 84 02B3 0A 02CC 07 02B4 67 02CD 7B 02B5 70 02CE 59 02CF 75 02E7 20 02D0 50 02E8 67 02D1 90 02E9 DC 02D2 D6 02EA 5E 02D3 B4 02EB 14 02D4 33 02EC CC 02D5 81 02ED 5D 02D6 06 02EE 25 02D7 53 02EF 05 02D8 A1 02F0 81 02D9 21 02F1 1C 02DA BF 02F2 70 02DB B1 02F3 5E 02DC 1C 02F4 5C 02DD 34 02F5 6C 02DE 94 02F6 39 02DF 41 02F7 94 02E0 72 02F8 EF 02E1 59 02F9 69 02E2 20 02FA 20 02E3 FE 02FB 67 02FC DC 02E4 54 02FD 5E 02E5 65 02FE 14 02E6 6F 02FF CC 0300 5D 0319 20 0301 25 031A F3 0302 01 031B 91 0303 81 031C 05 0304 09 031D 28 0305 4C 031E 02 0306 25 031F 9C 0307 03 0320 03 0308 81 0321 05 0309 04 0322 71 030A 70 0323 04 030B 5E 0324 1B 030C 5D 0325 0C 030D 4C 0326 4B 030E F8 0327 F8 030F 5C 0328 06 0310 6F 0329 25 0311 4C 032A 09 0312 21 032B 81 0313 01 032C 62 0314 CB 032D 03 0315 21 032E 6C 0316 1F 032F 5C 0317 25 0330 6F 0318 1C 0331 5E 0332 20 034B 5C 0333 E2 034C 25 0334 5D 034D 02 0335 02 034E 84 0336 13 034F 11 0337 18 0350 91 0338 24 0351 28 0339 16 0352 47 033A 25 0353 C0 033B FE 0354 81 033C 91 0355 02 033D 08 0356 79 033E 02 0357 25 033F 55 0358 09 0340 20 0359 81 0341 D1 035A 02 0342 5C 035B 70 0343 71 035C 57 0344 04 035D 29 0345 50 035E 01 0346 66 035F F9 0347 6A 0360 20 0348 45 0361 10 0349 24 0362 52 034A F5 0363 70 0364 C0 037D 81 0365 91 037E 05 0366 03 037F 20 0367 24 0380 1C 0368 66 0381 90 0369 D1 0382 E0 036A 25 0383 25 036B 01 0384 1C 036C 92 0385 81 036D 03 0386 04 036E 20 0387 70 036F 79 0388 90 0370 25 0389 D9 0371 79 038A 52 0372 81 038B 41 0373 02 038C 90 0374 72 038D DD 0375 51 038E 57 0376 29 038F 77 0377 01 0390 56 0378 FC 0391 5C 0379 40 0392 29 037A 13 0393 01 037B 13 0394 F6 037C C2 03B0 DF 03C9 DF 03B1 CE 03CA C7 03B2 EF 03CB FE 03B3 DF 03CC DF 03B4 DF 03CD DF 03B5 CA 03CE DF 03B6 ED 03CF DF 03B7 DF 03D0 DF 03B8 FC 03D1 DF 03B9 FE 03D2 DF 03BA F1 03D3 DF 03BB FE 03D4 FF 03BC F3 03D5 FF 03BD FA 03D6 FF 03BE DF 03D7 FF 03BF DF 03D8 FF 03C0 C7 03D9 FF 03C1 FE 03DA FF 03C2 DF 03DB FF 03C3 EB 03DC FF 03C4 FE 03DD FF 03C5 EC 03DE FF 03C6 EB 03DF FF 03C7 F0 03E0 05 03C8 DF 03E1 07 03E2 14 03EB D2 03E3 00 03EC D3 03E4 01 03ED D4 03E5 03 03EE D5 03E6 05 03EF D6 03E7 07 03F0 D7 03E8 07 03F1 D8 03E9 07 03F2 D9 03EA D1 03F3 DC |
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The above tables contain, in coded form, one possible sequence of elementary operations for performing, via the microprocessor system indicated, the functions shown in the block diagrams and foregoing description.
FIG. 5 shows a more detailed representation of the block diagram of character generator 16 in FIG. 1.
Number 60 in FIG. 5 indicates a character count circuit for supplying the addresses to character memory 61. This has a 48×6 format for containing the 48 characters transmitted periodically by processing unit 11.
The six INPUT/OUTPUT terminals of the said memory are connected to six output terminals of PORT 71 of processing unit 11. These are also connected to six inputs of character ROM 62.
This may be a Fairchild 3258 type, for memorizing 64 characters for each of which it supplies an image consisting of a 5×7 point matrix. Each character is separated vertically from the next by two lines of blanks.
A built-in counter, which receives a clock signal with horizontal scanning frequency FH from the television circuits and a reset signal R1 from circuit 60, scans the following point lines of the said matrix.
The five outputs of the said ROM 62 are connected to a parallel-series converter circuit 63 which transforms the 5 signals received from the said 5 outputs into a series signal. It also adds a suitable number of blanks (e.g. 3) on to the end of the said 5 signals to separate the characters horizontally.
Circuit 63 receives a clock signal from oscillator circuit 66 the frequency of which determines the width of each of the characters displayed on the screen. It also receives a LOAD signal "L" for each character (every 5+3=8 clock cycles in the example shown) from divider circuit 67 which, in turn, receives the clock signal from oscillator circuit 66. The signal thus appearing at the output of converter 63 is sent to combiner circuit 64 consisting of known logic elements (e.g. three 2-input AND gates each with a first input connected to the output of circuit 63 and a second connected to one of the outputs of circuit 65) which sends the said signal to one or more of its three outputs, marked R, G and B in the Figure, in response to the same number of control signals supplied by control circuit 65. The said outputs R, G and B are connected, in the known way, to the amplifier circuits of the color signals on the set so that the signals supplied by circuit 64 are added to the 
video ones of the received television signal.
Depending on the instructions received from circuit 65, it is possible to obtain the indications in any one of the three primary color combinations.
In FIG. 5, the control circuit 65 receives a control signal from an output of circuit 71-port 4 of unit 11-(FIG. 1) so that the indications are displayed in green when the system is set to the first keyboard and yellow when it is set to the second.
Numbers 68, 69 and 70 indicate three switch circuits, similar to one another, controlled in parallel by a control signal DT supplied by a bit of port 1 of processing unit 11 in FIG. 1. Depending on the DT signal, these three switch circuits enable the FIG. 5 circuits to be set so as to load the data in memory 61 when the DT signal is present (high) and, vice versa, to set the same circuits for transmitting the data from the said memory to outputs R, G and B when the DT signal is absent (low) or when unit 11 is not transmitting characters to memory 61 (for display updating). To do this, when the DT signal is present, switches 68, 69 and 70 are positioned as shown by letter A in FIG. 5. This causes a reset pulse to be applied to terminals R2 and R3 of count circuit 60 and memory 61 is set to INPUT by the same DT signal applied to the input-output I/O control terminal.
Count circuit 60 receives clock pulses DC from an output terminal of processing unit 11 of FIG. 1 (port 4) via switch circuit 68. The same DC signal is also applied to the write control input "W" of memory 61.
In this way, for each clock pulse it receives, counter 60 supplies RAM memory 61 with addresses 0 to 47. At the same time, unit 11 supplies the 48 signals (at port 4) received at the data input of the same memory so that they are memorized in the corresponding cells as a result of the "W" pulses.
When the DT signal is absent
, on the other hand, (switches in position B), character counter 60 receives clock signals from circuit 66 via divider 67, reset signals with vertical scanning frequency FV at terminal R2, reset signals with horizontal scanning frequency FH at terminal R3 and a formatchange signal "F" from processing unit 11. In this way, it supplies memory 61 with suitable addresses for arranging the 48 display characters in three 16-character lines, should signal "F" be present, or else it supplies the said memory with only the first sixteen addresses for displaying a single 16-character line when signal "F" is absent. Counter 60 also supplies combiner circuit 64 with a disabling circuit for deactivating it during the remaining television picture time. In this way, only a certain part of the screen is displayed, e.g. the top left-hand corner. If needed, the same disabling signal can be used for supplying a blank signal at an appropriate point in the television video amplification chain so as to blacken the background of the display to make the characters more visible.
A further output of circuit 71 (port 4 of unit 11) controls a switch, 72, between a BIP signal (which can be picked up at an appropriate point on the circuit, e.g. at the output of divider 7 of FIG. 1) and a first input of an adding circuit, 73, whose second input receives the audio B.F. signal of the received television signal picked up downstream from the manual volume adjuster. The output of the said adding circuit is connected to the input of the B.P. amplifier, 74, on the set which pilots the loudspeaker 75. In this way, under given circumstances, the processing unit 11 can control the sounding of an alarm for warning the user. The said circumstances may be:
when the "M" memory key is pressed. The alarm reminds the user that the key has been pressed so as to prevent him from altering the content of the memory by mistake;
when an unperformable instruction is given (e.g. the number of a non-existent channel or time) etc.
when the maximum allowable limits have been reached for certain adjustments such as fine tuning corrections.
FIG. 6 gives a more detailed view of parts of circuits 12, 13, 14 and 15 in FIG. 1 showing memorization of the channels in the outside memory and maintenance of data
during temporary power cuts. The said circuits 12, 13, 14 and 15 roughly correspond to the blocks marked 113, 100, 105 and 80 in FIG. 6.
Block 80 comprises a Zener diode, 83, connected between a +12 output of a supply circuit ("AC" voltage input, transformer 81 and rectifier 82) and a grounded resistor 84. The signal present at the resistor terminals is sent to an integrator circuit consisting of resistor 86, diode 87 and condenser 85.
The signal made available here, and inverted by inverter 88, is sent to inverter circuit 95 via integrator assembly consisting of resistor 93 and condenser 94, and also to the base of common-emitter transistor 90 via coupling resistor 89. The collector of transistor 90 is connected to a +5 supply voltage through resistor 92 and grounded through push-button switch 91 and supplies a reset signal to processing unit 11 (FIG. 1).
The +12 voltage is also supplied to the input of a stabilizer circuit 96 at the output of which, filtered by condenser 97, is made available the +5 supply voltage for supplying other circuits not shown in the Figure. The output of inverter 95 is connected to a first input of NAND gates 107 and 109 and to both inputs of NAND gate 106 which acts as an inverter. The output of the said gate 106 is connected to a reset input R4 of separator circuit 112 which receives the output signal of gate 107 at its disabling input C.D. via inverter circuit 110. Gate 107 receives a conditioning signal C.S. from processing unit 11 of FIG. 1 at its second input. The output of gate 107 is also connected to a deactivating input C.D. of memory 113. A READ signal from processing unit 11 of FIG. 1 is sent via NAND gate 108, which acts as an inverter, to the read disabling "NR" input of memory 113. This input is also connected to a second input of gate 109 the output of which is connected to a write disabling "NW" input of the same memory 113.
The +5 voltage is also supplied to the anode of diode 101 at the cathode of which is connected a condenser, 104, the second terminal of which is grounded. Resistor 102 and 3 Volt battery 103, connected in series, are also connected parallel to condenser 104. The voltage available at the terminals of condenser 104 supplies memory 113, separator 112 and the 4 gates 106, 107, 108 and 109 contained in a single semiconductor body (CHIP).
Separator 112 has 5 inputs connected to 5 outputs of control circuit 111 (keyboard or remote-control receiver) and 5 outputs connected to 5 terminals of circuit 114 (port 5 of processing unit 11 in FIG. 1).
The same 5 outputs are also connected to 5 address inputs of memory 113.
The circuit described above operates as follows:
The function of block 100 is to generate a permanent supply voltage to keep memory 113 activated. In the event of a power cut, battery 103 supplies sufficient current to maintain the data in the memory through resistor 102. Vice versa, when power is being supplied from the mains, the +5 voltage is supplied to the memory via diode 101 and, at the same time, the battery is recharged slightly through resistor 102.
By means of Zener diode 83 and the integrator circuit comprising elements 85, 86 and 87, block 80 supplies a signal, at the output of inverter 95, after the +5 voltage, when the power supply is restored, and in advance of the said voltage when the power supply is cut off. In this way, the signals supplied by processing unit 11 to memory 113 cannot reach the memory during a power cut or during transient states.
Under the above conditions, gates 107, 108 and 109 are conditioned so as to protect memory 113 whereas gates 106 and 110 force separator 112 to supply a series of zeros at the output to prevent the memory from receiving chaotic address signals.
Block 80 also supplies, at the output of transistor 90, a signal similar to the one supplied by inverter 95 to keep processing unit 11 inactive during transient states and thus prevent uncontrolled operation. Push-button 91, however, enables a reset signal to be supplied manually to the said unit to commence the operation sequence from a preset point.
FIG. 7 shows a possible variation of one part of the circuit shown in FI
G. 1. FIG. 7 only illustrates the parts which differ from FIG. 1 or which are connected differently.
Number 120 in FIG. 7 indicates a control keyboard which, besides the keys shown in FIG. 1 and not repeated here, comprises 6 keys marked "V+", "V-", "L+", "L-", "C+" and "C-". The outputs of the said keyboard are connected to a group of input-output terminals 5 of processing unit 121 which is essentially the same as unit 11 in FIG. 1 from which it differs, among other things, by the provision of a further group of output terminals (ports) 6.
Six terminals of the said group are connected to six inputs of a digital/analogue converter 123 of the known type (e.g. consisting of a known network of R/2R resistors). The analogue output of the said converter is supplied to a switch circuit 124 with three outputs marked V, L and C in the Figure which are connected to three storage condensers 125, 126 and 127 respectively. Switch 124 also has two control input terminals connected to the remaining two output terminals of port 6 of unit 121 which receive the respective control signals for forwarding the analogue signal to one or other of condensers 125, 126 or 127.
The group of terminals or port 4 is connected to 8 input/output terminals of a RAM memory circuit 122. This replaces memory 12 of FIG. 1 from which it differs by the number of 8-bit cells (10×5 instead of 10×2). This memory also receives six address bits (instead of 5) from six output terminals (port 5) of unit 121.
The FIG. 7 circuit operates as follows:
When one of the six keys mentioned above is pressed (e.g. key "V+"), unit 121 supplies the character generating circuit with a combination of symbols which may be:
VVVVVVVV . . .
LLLLLL . . .
CCCCCCCCCCC . . .
The line of symbols corresponding to the pressed key (V, L, C) is displayed with a different color from the rest. The number of characters per line is proportional to the corresponding analogue signal level (V, L, C) at that time. Whenever one of the + keys is pressed, the corresponding analogue level is increased 1/64 of maximum value. When an operation involving memorization is performed (e.g. whenever "KEY" operation mode is adjusted or the "M" key pressed), processing unit 121 transmits the relative data in digital form to memory 122 and has it memorized with much the same procedure already described and shown in FIG. 3. This means the data memory 122 is called upon to memorize for each of the 10 "KEYS" is of 5 types: channel, tuning, volume, brightness and color. For the sake of uniformity; the memory accepts 8-bit data whereas, for analogue adjustments, 6 bits (64 levels) are more than enough so two bits are ignored.
Other ways exist of displaying analogue levels on the television screen using the character generator and circuit arrangement described in the present invention. Besides the one described above, the display could show any one of the following:
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| V******* < L***** C********** or : VOLUME 40 ? BRIGHTNESS 30 colour 50 or : V+++++ L C-- |
| ______________________________________ |
In the first, the number of asterisks is proportional to the relative analogue signal level and the adjustment being made indicated by the symbol ">". In the second, the level is indicated by the number to the side of the adjustment item while the adjustment being made is indicated by the question mark. In the third, the number of "+" (or "-") signs is proportional to the increase (or decrease) made to the preset nominal level. Of course, the preselected, memorized levels are preserved in memory 122, even in the event of a power cut, thanks to the precautions already described which also apply to the FIG. 7 case.
It may prove useful to apply the sound alarm described in FIG. 5 for analogue adjustments too, for example, when the maximum level is reached.
The advantages of the present invention will be clear from the foregoing description. However, a number of variations can be made. For example, in the description, it was supposed a particular type of 8-bit microprocessor system was used with a separate CPU and ROM. It is possible, and even convenient, to use other types of microprocessors with a higher number of internal RAM registers (e.g. 128) or a so-called monochip containing an internal RAM and timer circuit, besides the ROM, or a 16-bit microprocessor. It may even prove useful to fit the receiver with a remote-control. In this case, a keyboard similar to the one described is combined on the portable transmitter part of the remote-control system. A further variation, to avoid duplicating the control keyboard, could be to provide accommodation in the receiver housing with electric contacts in which to connect the transmitter part for operating the local control.
Many other variations can be made without, however, departing from the scope of the present invention.
For example, besides the key arrangement in FIG. 1 for controlling channel selection or FIG. 7 for controlling analogue levels (V, L, C), a number of different combinations can be used even using other control components different from keys or push-buttons.
Walker, "For TV Tuners a Digital Look", Electronics, Jun. 26, 1975, pp. 65-66.
Evans et al., "Direct Address Television Tuning and Display System Using Digital MOS Large Scale Integration", IEEE Transactions on Consumer Electronics, vol. CE-22, No. 4, pp. 267-288, Nov. 1976.
Electronics, vol. 48, No. 24, Nov. 27, 1975, "Philips TV Set Indicates Station Tuning and Color Settings on Screen", pp. 6E and 8E.
Werner, "Linear Color Bar Display for CTV Sets", Radio Mentor Electronic, vol. 41, No. 9, pp. 350-351, Sep. 1975.
GALAXI MOD. GALAXONE 27" CHASSIS GF77/M1702 ULTRASONIC REMOTE CONTROL RECEIVER:
An ultrasonic remote control receiver wherein an incoming ultrasonic signal is converted to square wave pulses of the same frequency by a Schmitt trigger circuit; digital circuits are thereafter used to count pulses resulting from the incoming signal over a predetermined period of time; a decoder activates one of a plurality of outputs in dependance to the number of pulses counted, provision is made to prevent interference signals from producing undesired control outputs.
1. An ultrasonic remote control receiver for applying a control signal to a selected one of a plurality of control channels in response to and dependent on the frequency of a received ultrasonic signal comprising:
2. An ultrasonic remote control receiver comprising:
3. An ultrasonic remote control receiver comprising:
4. The ultrasonic remote control receiver as defined in claim 3, wherein said means producing square pulses is a Schmitt trigger circuit and said means providing a signal input to said sequence controller is a retriggerable monostable multivibrator.
5. An ultrasonic remote control receiver comprising:
6. An ultrasonic remote control receiver comprising:
7. An ultrasonic remote control receiver as defined in claim 6 further comprising a monostable multivibrator between the output of said Schmitt trigger circuit and the remaining elements of said receiver.
8. An ultrasonic remote control receiver as defined in claim 6 further comprising a bistable multivibrator between the output of said Schmitt trigger circuit and the remaing elements of said receiver.
9. The ultrasonic remote control receiver as defined in claim 7 wherein the hold period of said monostable multivibrator is slightly less than one half the period of said square wave pulses from said Schmitt trigger circuit.
To obtain the simplest possible transmitter construction in ultrasonic remote control, modulation of the emitted ultrasonic frequencies is not employed; to control different operations different frequencies are emitted which must be recognized in the receiver and evaluated for carrying out the different functions associated therewith. Presently, to recognize the different frequencies, use is made of resonant circuits, each of which contains one or more coils tuned in each case together with a capacitor to one of the useful frequencies.
These hitherto known receivers have numerous disadvantages. Thus, for example, before starting operation of the receiver a time-consuming alignment procedure must be carried out with which the resonant frequencies of the individual resonant circuits are set. Since it is inevitable that with time the resonant circuits become detuned, it may be necessary to repeat the alignment procedure.
A further disadvantage is that the known receivers cannot be made by integrated techniques because the coils used therein are not suitable for such techniques.
The problem underlying the invention is thus to provide an ultrasonic remote control receiver of the type mentioned at above which is extremely simple to set and in addition can be made by integrated techniques.
To solve this problem, according to the invention an ultrasonic remote control receiver of the type mentioned above contains a counter for counting the useful frequency oscillations received during a fixed measuring time, a sequence control device which determines the measuring time and which is started on receipt of a useful frequency, and a decoder comprising several outputs which is connected to the outputs of the counter, said decoder emitting a control signal at the output associated with the count reached at the end of the measuring time.
In the receiver constructed according to the invention the frequency emitted by the transmitter is identified by counting the oscillations received during a measuring time. The evaluation of the count reached at the end of the measuring time takes place in a decoder which emits a control signal at a certain output according to the count. The measuring time is fixed by a sequence control device which is set in operation on receipt of useful frequency signals.
In such a receiver the only quantity which has to be exactly fixed is the measuring time; it is therefore no longer necessary to align components to certain frequencies. Since no coils are required, the novel receiver can also be made up of integrated circuits.
A further development of the invention resides in that an interference identifying device is provided which on receipt of interference frequencies differing from the useful frequencies interrupts the operation of the sequence control device.
Hitherto known ultrasonic remote control receivers respond to any oscillation received if the frequency thereof has a value which excites a resonant circuit in the receiver. There is no way of distinguishing between oscillations received from the remote control transmitter and from interference sources.
Interfering ultrasonic oscillations may be due to many different causes. For example, noises such as hand clapping, rattling of short keys such as safety keys, operating cigarette lighters, rattling of crockery and the like cover a frequency spectrum reaching from the audio frequency range far into the ultrasonic region. The ultrasonic components may have the effect of simulating a useful frequency and cause an erroneous function in the receiver.
The interference identifying device according to the further development is constructed in such a manner that it recognizes oscillations having frequencies deviating from the useful frequencies and as a result of this recognition switches off the sequence control device. This switching off prevents the counter state reached from being passed to the decoder and consequently the latter cannot emit an erroneous control signal.
With this furthe
Examples of embodiment of the invention are illustrated in the drawings, wherein:
FIG. 1 shows a block circuit diagram of a remote control receiver according to the invention;
FIG. 2 is a diagram explaining the mode of operation of the circuit according to FIG. 1;
FIG. 3 shows another embodiment of the invention;
FIG. 4 is a diagram explaining the mode of operation of the circuit according to FIG. 3;
FIG. 5 is a diagram illustrating interference frequency identification in the circuit according to FIG. 3;
FIG. 6 shows a block circuit diagram of another embodiment of part of the circuit according to FIG. 3;
FIG. 7 is a diagram explaining the mode of operation of the embodiment according to FIG. 6;
FIG. 8 is a block circuit diagram of a further embodiment of a part of the circuit according to FIG. and, an
FIG. 9 is a diagram explaining the mode of operation of the embodiment according to FIG. 8.
The ultrasonic remote control receiver shown in FIG. 1 comprises an input 1 which is connected to an ultrasonic microphone intended to receive ultrasonic signals coming from a remote control transmitter. For each function to be performed by the receiver the remote control transmitter emits one of several unmodulated different useful frequencies which are spaced from each other a constant channel spacing Δ f and which all lie within a useful frequency band.To obtain a signal which is as free as possible from noise at the input 1, a band filter and a limiting amplifier are preferably incorporated between the ultrasonic microphone and the input 1. The band filter may be made up of two active filters whose resonant frequencies are offset with respect to each other so that a pass band curve in the useful frequency band is obtained which is as flat as possible.
The input 1 leads to a Schmitt trigger 2 which converts the electrical signal applied thereto with the frequency of the ultrasonic signal to a sequence of rectangular pulses. The output 3 of the Schmitt trigger 2 is connected to the input 6 of a frequency divider 7 which is in operation for the duration of a control pulse applied to its control input 8 and divides the recurrence frequency of the pulses supplied thereto at the input 6 thereof in a constant division ratio. The output 9 of the frequency divider 7 is connected to the input 10 of a counter 11 which counts the pulses coming from the frequency divider 7. The counter 11 is a four-stage binary counter whose stage outputs are connected to the inputs of a store (register) 12 which is so constructed that on application of a control pulse to the input 12 thereof it takes on the counter state in the counter 11 and stores said counter state until the next pulse at the input 13. The stage outputs of the store 12 are fed to the inputs of a decoder 14 which decodes the counter state contained in the store 12 in such a manner that a control signal is emitted at that one of its outputs D0 to D9 which is associated with the decoded counter state.
The output 3 of the Schmitt trigger 2 is also connected to the input 4 of a monoflop 5 which is brought into its operating state by each pulse at the output 3 of the Schmitt trigger. It returns from this operating state to its quiescent state after expiration of a hold time depending on its intrinsic time constant if it does not receive a new pulse prior to expiration of this hold time. It is held in the operating state by each pulse received during the hold time until it finally flops back into the quiescent state when the interval between two successive pulses is greater than its hold time.
The output 15 of the monoflop circuit 5 is connected to the input 16 of a sequence control device 17 which is set in operation by the signal emitted in the operating state of the monoflop 5. Supplied to the sequence control device by 17 via a Schmitt trigger 18 at a control input 19 are pulses having a recurrence frequency derived from oscillations of the same frequency, for example, twice the mains frequency of 100 c/s, applied to the input 20. The sequence control device 17 is so constructed that in a cyclically recurring sequence in time with the pulses supplied to it at the input 19 it emits pulses at the outputs 21, 22 and 23 whose duration is equal to the period of the oscillation applied to the input 20. The output 21 of the sequence control device 17 is connected to the control input 8 of the frequency divider 7, the output 22 is connected to the control input 13 of the store 12 and the output 23 thereof is connected to the reset input 24 of the counter 11.
The mode of operation of the circuit of FIG. 1 will now be explained with the aid of the diagram of FIG. 2
which shows the variation with time of the signals at the output 3 of the Schmitt trigger 2 and at the inputs 16 and 19 as well as the outputs 21, 22 and 23 of the sequence control device 17.It will be assumed that a useful frequency oscillation is being received at the input 1. The Schmitt trigger 2 then emits at the output 3 rectangular pulses whose recurrence frequency is equal to the frequency of said useful frequency oscillation. The first pulse emitted by the Schmitt trigger 2 puts the monoflop 5 into its operating state. The hold time of the monoflop 5 is so dimensioned that for all useful frequencies occurring it is longer than the recurrence period of the rectangular pulses emitted at the output 3. The monoflop 5 therefore remains in its operating state for as long as the useful frequency oscillation is applied to the input 1 and supplies to the control input 16 of the sequence control device 17 a control signal throughout this time.
Due to the control signal applied to the input 16 the sequence control device 17 emits at its outputs 21, 22 and 23 in time with the pulses supplied to it via the Schmitt trigger 18 at the input 19 mutually offset control pulse sequences, the duration of the control pulses being equal to the time interval of the leading edges of the pulses supplied at the input 19 and thus equal to the period of the oscillation applied to the input 20 and the pulse sequences being offset with respect to each other by one pulse duration. The control pulses emitted by the sequence control device 17 perform the following functions:
a. The first control pulse appearing at the output 21 sets in operation for its duration via the input 8 the frequency divider 7 so that the latter divides the recurrence frequency of the pulses supplied thereto from the Schmitt trigger 2 and thus the frequency of the useful frequency oscillations received in a constant ratio and passes counting pulses to the input 10 of the counter 11 with a correspondingly reduced recurrence frequency.
b. Via the input 13 the second pulse occurring at the output 22 causes the store 12 to take on and to store the count of the counter 11 reached at the end of the first control pulse.
c. The third control pulse appearing at the output 23 resets the counter 11 via the reset input 24.
COntrol pulse sequences continue to be emitted for as long as the monoflop 5 remains in its operating state.
Since the stage outputs of the store 12 are permanently connected to the inputs of the decoder 14, the store content is continuously being decoded. The decoder 14 therefore emits a control signal at the output which is associated with the count contained in the store.
During each group of three offset control pulses of the three control pulse sequences emitted by the sequence control device 17, the counter 11 receives counting pulses from the frequency divider 8 only for the duration of the control pulse of the first control pulse sequence emitted at the output 21. The duration of this control pulse thus determines the measuring time during which the oscillations of the useful frequency signal received are counted. Since the duration of the control pulses emitted by the sequence control device 17 is however equal to the period of the oscillation applied to the input 20, the measuring time is fixed by the period of said oscillation.
The frequency divider 7 is connected in front of the counter 11 so that a small capacity of the counter 11 is sufficient to obtain a clear indication of the received frequency even when the measuring time is so long that a large number of periods of the useful frequency oscillation is received during the measuring time. This is for example, the case when the oscillation supplied to the input 20 has twice the mains frequency. Since the frequency divider 7 divides the frequency of the useful frequency oscillations received in the constant ratio k, the counter 11 need count only the oscillations having a correspondingly reduced frequency. If the division ratio k of the divider 7 is so set that it is equal to the product of the measuring time t and channel spacing Δ f, only a frequency which differs by at least the channel spacing Δ f from a previously received frequency will change the count of the counter 11.
The purpose of the monoflop 5 is to prevent interference frequencies supplied to the input 1 from producing at one of the outputs D0 to D9 of the decoder 14 a control signal which could lead to an erroneous function of the equipment being controlled. The interference sources usually encountered emit a frequency spectrum whose components lie predominantly in the audio region, i.e., below the ultrasonic region. If the hold time of the monoflop 5 is set to a value slightly greater than the period of the smallest useful frequency but smaller than the period of the highest interference frequency occurring, the monoflop 5 returns to its quiescent state before the end of the period of an interference frequency. Since in this state no signal is supplied to the control input 16 of the sequence control device 17, the latter is put out of operation and consequently the received signal cannot be evaluated because the count of the counter 11 is not transferred to the store 12 and thus no decoding takes place.
To facilitate understanding of the invention, the function of the circuit of FIG. 1 will now be explained numerically by way of example. The channel spacing Δ f will be taken as 1,200 c/s so that for a frequen
f = (k/t) . (n . Z + m + 0.5)
wherein
f = useful frequency received in c/s
t = measuring time in seconds
k = division ratio of the frequency divider 7
Z = capacity of the counter 11
n = number of count cycles passed through (integral)
m = count
The term 0.5 in brackets is a correction factor which ensures that a new count is reached whenever the received frequency differs at least by half the channel spacing Δf from the channel center frequency of the neighboring channel. With a channel spacing Δ of 1,200 c/s, a measuring time t of 10 ms, a division ratio k of the frequency divider 7 of 12, a capacity Z of the counter 11 of 10 and an input frequency f of 33 k c/s, the count 7 is for example reached after two complete count cycles. This is because the input frequency of 33 k c/s is first divided by 12 by the frequency divider 7 so that pulses having a recurrence frequency of 2.750 k c/s reach the input 10 of the counter 11. Since the frequency divider 7 emits counting pulses only during the measuring time of 10 ms, during said time only 27.5 pulses reach the input 10 of the counter 11. For this number of pulses the counter thus runs through two complete cycles and finally stops at the count 7. Similarly, for an input frequency of 39 k c/s the counter stops at the count 2 after passing through three complete counter cycles. With the numerical values given up to 10 different frequencies may be received without any ambiguity occurring in the evaluation.
FIG. 3 illustrates a further embodiment of an ultrasonic remote control receiver which differs from the embodiment described above primarily in that to fix the measuring time it is not necessary to supply a reference frequency.
In the illustration of FIG. 3 the same reference numerals as in FIG. 1 are used for identical circuit components. The part of the circuit enclosed in the dashed line represents the sequence control device 17' which emits at its outputs 21', 22', 23' control signals which have substantially the same functions as the control signals emitted at the outputs 21, 22 and 23 of the sequence control device 17 of FIG. 1.The useful frequency signal received is again supplied to the input 1. The input 1 is connected to the input of the Schmitt trigger 2 which again converts the input useful frequency oscillations into a sequence of pulses whose recurrence frequency is equal to the input useful frequency. The output 3 of the Schmitt trigger 2 is connected to the input B1 of a monoflop 25 which is contained in the sequence control device 17' and which is so constructed that it is switched to its operating state by a pulse received at the input B1 but during its hold time cannot be tripped again by any further pulse. The output 3 of the Schmitt trigger 2 is also connected to the input 26 of an AND gate 27 whose other input 28 is connected to that output 21' of the sequence control device 17' which is directly connected to the output Q1 of the monoflop 25. The output Q1 of the monoflop 25 which emits the signal complementary to the signal at the output Q1 is connected to the input B2 of a further monoflop 29 whose output Q2 is connected to the input A1 of the monoflop 25. The input 10 of the counter 11 is connected to the output of the AND gate 27. The stage outputs of the counter 11 are connected to the inputs of a gate circuit 30 which on receipt of a control pulse at its input 31 transfers the count contained in the counter 11 to the decoder 14 connected to its outputs. In the decoder 14 the count is then decoded in the manner already explained in conjunction with FIG. 1 so that a control signal is emitted at the output corresponding to the transferred count.
The output 3 of the Schmitt trigger 2 is further connected to the input 32 of an AND gate 33 which is contained in the sequence control circuit 17' and the other input 34 of which is connected to the output of a NOR gate 35. The output Q1 of the monoflop 25 is directly connected to one input 36 of the NOR gate 35 and is connected to the other input 37 via a delay member 38 and an inverter 39.
The output of the AND gate 33 represents the output 22' of the sequence control circuit 17' which is directly connected to the control input 31 of the gate circuit 30. In addition, the output of the AND gate 33 is directly connected to one input 40 of a NOR gate 41 and to the other input 42 thereof via a delay member 43 and an inverter 44. The outpu
The mode of operation of the circuit of FIG. 3 is explained in FIG. 4. Since the measuring time in the arrangement of FIG. 3 is substantially shorter than in the arrangement of FIG. 1, the time scale in FIG. 4
has been enlarged compared with FIG. 2 in order to clarify the illustration. When useful frequency oscillations are supplied to the input 1 of the receiver, pulses whose recurrence frequency is equal to the useful frequency appear at the output 3 of the Schmitt trigger 2. It will be assumed that the presence of a pulse corresponds to the logical signal value 1 whereas a pulse space represents the logical signal value 0. The leading edge of the first pulse at the output 3 puts the monoflop 25 into its operating state in which it emits the signal value 1 for the duration of its hold time at its output Q1, resulting in the control pulse at the output 21', which passes to the input 28 of the AND gate 27. Since the other input 26 of the AND gate 27 is directly connected to the output 3 of the Schmitt trigger 2, for the duration of each pulse at the output 3 the signal value 1 is also applied to the input 26 of the AND gate 27. Thus, the pulses occurring at the output 3 of the Schmitt trigger 2 are transferred for the duration of the control pulse at the output 21', i.e. during the hold time of the monoflop 25, as count pulses to the counter 11 and counted by the latter. The hold time of the monoflop 25 thus determines the measuring time; the capacity of the counter 11 must be greater than the number of pulses received during the measuring time for the greatest useful frequency. The count of the counter 11 reached at the end of the measuring time is then a clear indication of the received useful frequency.When the monoflop 25 flops back into the quiescent state at the end of its hold time, it applies the signal value 0 via its output Q1 to the input 28 of the AND gate 27 so that no further count pulses can enter the counter 11. At the same time there appears at the output Q1 of the monoflop 25 the signal value 1 which at the input B2 puts the monoflop 29 into the operating state. In this state the monoflop 29 emits at its output Q2 the signal value 1 which blocks the monoflop 25 via the input A1 for the duration of the hold time of the monoflop 29 in such a manner that it cannot be switched into the operating state by pulses at the input B1. This is necessary to enable the sequence control device 17' to have sufficient time to generate the control pulses appearing at the outputs 22' and 23' for the transfer of the count or resetting of the counter.
With the return of the monoflop 25 to its quiescent state, the signal value 0 passes to the input 26 of the NOR gate 35 directly connected to the output Q1. During the operating state of the monoflop 25 the signal value 0 is applied with a delay determined by the delay member 38 via the inverter 39 to the input 37 of the NOR gate 35, said signal value 0 being replaced by the signal value 1 only after the delay time of the delay member 38 and not simultaneously with the flop back of the monoflop 25. Thus, for the duration of this delay time the signal value 0 is applied to both inputs 36 and 37 of the NOR gate 35 and consequently for this period of time the signal value 1 appears at the output of the NOR gate 35. The circuits 35, 38, 39 thus effect the generation of a short pulse which immediately follows the return of the monoflop 25 and the duration of which is determined by the delay of the delay member 38. This pulse is applied to the input 34 of the AND gate 33 (FIG. 4). The same effect could obviously alternatively be obtained with a monoflop which is tripped by the signal at the output Q1 changing from the value 1 to the value 0.
Now, if during this time a pulse is emitted at the output 3 of the Schmitt trigger 2, i.e., a signal value 1 is at the input 32 of the AND gate 33, said gate supplies to the control input 31 of the gate circuit 30 a control pulse for the duration of the delay of the delay member 38. This control pulse opens the gate circuit so that it allows the count reached at the end of the hold time of the monoflop 25 to pass to the decoder 14. The latter then emits a control signal at the output associated with this count. The signal value 1 present at the output of the AND gate 33 during the delay of the delay member 38 also passes directly to the input 40 of the NOR gate 41, at the other input 42 of which the signal value 0 is applied for the duration of the same pulse but with a delay determined by the delay member 43. Thus, in a manner similar to the circuits 35, 38, 39 the circuits 41, 43, 44 produce a short pulse which immediately follows the end of the output pulse of the AND gate 33 and appears at the output 23' of the sequence control circuit and is applied to the reset input 24 of the counter 11 (FIG. 4). This pulse resets the counter 11.
The hold time of the monoflop 29 is so set that it flops back into its quiescent state again only when the transfer process from the counter to the decoder via the gate circuit and the resetting of the counter has been effected. When the monoflop 29 returns to its quiescent state, it emits at its output Q2 the signal value 0 which brings the monoflop 25 via the input A1 thereof into such a condition that it can again be brought into its operating state by a pulse at the output 3 of the Schmitt trigger 2. In this manner the measuring and evaluating periods can be repeated for as long as useful frequency oscillations are supplied to the input 1.
In the circuit according to FIG. 3, interference frequencies are suppressed by setting a certain hold time of the monoflop 25. It is apparent from the above description of the function that the transfer of the count of the counter 11 to the decoder 14 takes place immediately following the end of the hold time of the monoflop 25, i.e., immediately following the end of the measuring time. However, a control signal initiating the transfer can be applied by the AND gate 33 to the control input 31 of the gate circuit 30 only when simultaneously with the end of the measuring time a pulse, i.e., the signal value 1, is present at the output 3 of the Schmitt trigger 2. Now, if the hold time of the monoflop 25 is made equal to the reciprocal of the channel spacing Δf, this coincidence at the AND gate 33 at the end of the measuring time occurs only when quite definite frequencies are applied to the input 1; these frequencies lie only within frequency bands which in the example described here, in which the output pulses of the Schmitt trigger 2 have a pulse duty factor of 1:2, have the width of half a channel spacing. These frequency bands each contain one of the useful frequencies. Between these frequency bands there are gaps having the width of half the channel frequency and frequencies falling in these gaps do not produce coincidence at the AND gate 33 and consequently cannot be evaluated by transfer of the count of the counter 11 to the decoder 14. Thus, frequency windows are formed over the entire frequency range which can occur at the input 1 and only frequencies lying within these windows are treated by the circuit according to FIG. 3 as useful frequencies. All intermediate frequencies are recognized as interference frequencies and excluded from evaluation.
If the measuring time is made exactly equal to the reciprocal of the channel spacing the frequency bands in which evaluation takes place are such that the rated frequencies of the signals transmitted by the transmitter are disposed at the lower end of the frequency bands. Thus, in this case only frequencies starting from a rated frequency in each case and extending up to the frequency in the center between two channels would be evaluated as useful frequencies. Since the frequency of the signals emitted by the transmitter can however also fluctuate below the rated frequency, it is desirable to place the frequency bands in which evaluation takes place so that the rated frequencies lie substantially in the center of the bands. To achieve this, the hold time of the m
To facilitate understanding of the type of interference identification just outlined attention is drawn to FIG. 5;
the latter shows at Q1 the output signal of the monoflop 25 determining the measuring time, at 3-F1, 3-F2, 3-F3 the pulse sequences appearing at the output 3 of the Schmitt trigger 2 for three different useful frequencies F1, F2, F3 and at 3-FS the pulse sequence which appears at the output 3 when an interference frequency FS is received which lies between the useful frequencies F2 and F3. It is apparent from this diagram that at the end of the measuring time a pulse is present at the output 3 of the Schmitt trigger only when useful frequencies are being received and that when an interference frequency is applied there is a pulse space at the end of the measuring time. Thus, at the AND gate 33 the presence of a pulse at the end of the measuring time is employed as criterion for the receipt of a useful frequency. It is also apparent from FIG. 5 that with the useful frequency F1 the counter 11 counts 4 pulses, with the useful frequency F2 up to 5 pulses and with the useful frequency F3 6 pulses.Isolated short interference pulses which could reach the input 1 of the circuit of FIG. 3 between two useful pulses and undesirably increase the count may be made ineffective by inserting a flip-flop circuit 45 between the output 3 of the Schmitt trigger 2 and the rest of the circuit as illustrated in FIG. 6.
The mode of operation of this flip-flop circuit 45 will be explained with the aid of FIG. 7, which shows the signals at the output 3 of the Schmitt trigger 2 and at the output 3a of the flip-flop circuit 45 firstly without interference and secondly with interference. The flip-flop circuit 45 is tripped by the leading edge of each output pulse of the Schmitt trigger 2. If a short interference pulse is received, the flip-flop circuit 45 supplies at its output 3a the signal value 0 for example on receipt of the useful pulse preceding the interference pulse, the signal value 1 on receipt of the interference pulse and the signal value 0 on receipt of the next useful pulse. If no interference pulse had occurred, the flip-flop circuit would not have been switched to the signal value 1 at the output until receipt of the next useful pulse. The flip-flop circuit thus effects on receipt of an interference pulse (and in general on receipt of an odd number of interference pulses) between two useful pulses a reversal of the signal values so that at the end of the measuring time coincidence is not reached at the gate 33 although a useful frequency was received. Without the flip-flop circuit 45 the count would be transferred, although because of the interference pulse received it would not correspond to the useful frequency received.The embodiment of FIG. 3 differs from the embodiment of FIG. 1 also in that instead of the store (register) 12 the gate circuit 30 is used that allow the count to be evaluated to pass briefly only once in a measuring and evaluating time. Thus, at the output of the decoder 14, instead of a uniform signal as in the case of the embodiment of FIG. 1, a series of pulses appears with the spacing of the control signals at the input 31 of the gate circuit 30. The use of a gate circuit instead of a store is suitable in applications where the equipment to be controlled must be actuated with control pulses and not with a uniform signal.
The immunity to interference may be further increased if in accordance with FIG. 8
a further monoflop 46 which cannot be triggered again during its hold time is inserted between the output 3 of the Schmitt trigger 2 (or the output 3a of the flip-flop circuit 45 of FIG. 6) and the remainder of the circuit. This hold time is set to half the period of the highest useful frequency. This modification is effective against a particular type of interferences, i.e., cases where an amplitude break occurs within an oscillation at the input 1 of the Schmitt trigger 2; this break would lead at the output 3 of the Schmitt trigger to the emission of two pulses instead of the single pulse per oscillation emitted in the normal case. These two pulses give the same effect as the receipt of a frequency which is twice as high and consequently without the additional monoflop 46 erroneous evaluations could arise. However, the monoflop 46 prevents the two pulses from becoming separately effective because it always emits pulses having the duration of its hold time; short double pulses which can arise due to amplitude breaks in the received signal thus cannot have any effect. FIG. 9 shows the action of the monoflop 46 when an amplitude break occurs at the input 1 of the Schmitt trigger 2 which produces a double pulse at the output 3 of the Schmitt trigger. As is apparent, the pulses at the output 3b of the monoflop 46 are not affected by this double pulse.One embodiment of the remote control receiver may also reside in that a sequence control counter fed by the pulses at the output of the Schmitt trigger 18 is used for the sequence control device 17 of FIG. 1; the stage outputs of said counter are connected to a decoder which is so designed that it activates one after the other one of its outputs for each count. Thus, for example, this decoder may have 10 outputs which are activated successively in each counting period of the sequence control counter. Since in accordance with the description of the example of embodiment of FIG. 1 a total of three control signals are required for the evaluation of the frequency received, the output signals at the fourth, fifth and seventh outputs may be used respectively for activating the frequency divider 7, opening the store 12 and resetting the counter 11. Since in this case the evaluation of the received frequency by the control pulses emitted from the output of the decoder of the sequence control device does not begin until the decoder emits a signal at its fourth output, there is an evaluation delay which has the advantage that short interference pulses produce no response in the receiver.
The advantageous formation of frequency band windows are used in the embodiment of FIG. 3 can also be applied in the embodiment of FIG. 1 if instead of the retriggerable monoflop 5 a monoflop is used which has no dead time and which is not retriggerable again during its hold time which as in the monoflop 35 of FIG. 3 is made equal to the reciprocal of the channel spacing Δ f. This monoflop thus always flops back into i
The ultrasonic remote control receiver described above can be used not only to control television sets, radio sets and the like but is particularly suitable also for industrial use in which high immunity to interference is very important. It may, for example, be used for remote control of cranes on large building sites, where there are a great number of different interference sources. The ultrasonic remote control receiver according to the above description is so immune to interference that it operates satisfactorily even under the difficult conditions encountered in the aforementioned use.
The following table provides examples of integrated circuits from Texas Instruments Incorporated which may be used in the foregoing invention.
______________________________________ Schmitt-triggers 2 and 18 SNX 49713 Monoflops 25, 29 and 46 SN 74121 Monoflop 5 SN 74122 Frequency divider 7 SN 7492 Counter 11 SN 7490 Store 12 SN 7475 Control 17 SN 7476 Gate 30 SN 7432 Decoder 14 SN 7442 ______________________________________
INTEGRAL THYRISTOR-RECTIFIER DEVICE
A semiconductor switching device comprising a silicon controlled rectifier (SCR) and a diode rectifier integrally connected in parallel with the SCR in a single semiconductor body. The device is of the NPNP or PNPN type, having gate, cathode, and anode electrodes. A portion of each intermediate N and P region makes ohmic contact to the respective anode or cathode electrode of the SCR. In addition, each intermediate region includes a highly conductive edge portion. These portions are spaced from the adjacent external regions by relatively low conductive portions, and limit the conduction of the diode rectifier to the periphery of the device. A profile of gold recombination centers further electrically isolates the central SCR portion from the peripheral diode portion.
GALAXI MOD. GALAXONE 27" CHASSIS GF77/M1702 LINE / HORIZONTAL DEFLECTION WITH THYRISTOR SWITCH TECHNOLOGY OVERVIEW.
Horizontal deflection circuit
(Thyristor Horizontalsteuerung)
Description:
1. A horizontal deflection circuit for generating the deflection current in the deflection coil of a television picture tube wher
The present invention relates to a horizontal deflection circuit for generating the deflection current in the deflection coil of a television picture tube wherein a first switch controls the horizontal sweep, and wherein a second switch in a so-called commutation circuit with a commutating inductor and a commutating capacitor opens the first switch and, in addition, controls the energy transfer from a dc voltage source to an input inductor.
German Aus
legeschrift (DT-AS) No. 1,537,308 discloses a horizontal deflection circuit in which, for generating a periodic sawtooth current within the respective deflection coil of the picture tube, in a first branch circuit, the deflection coil is connected to a sufficiently large capacitor serving as a current source via a first controlled, bilaterally conductive switch which is formed by a controlled rectifier and a diode connected in inverse parallel. The control electrode of the rectifier is connected to a drive pulse source which renders the switch conductive during part of the sawtooth trace period. In that arrangement, the sawtooth retrace, i.e. the current reversal, also referred to as "commutation", is initiated by a second controlled switch.
The first controlled switch also forms part of a second branch circuit where it is connected in series with a second current source and a reactance capable of oscillating. When the first switch is closed, the reactance, consisting essentially of a coil and a capacitor, receives energy from the second current source during a fixed time interval. This energy which is taken from the second current source corresponds to the circuit losses caused during the previous deflection cycle.
As can be seen, such a circuit needs two different, separate inductive elements, it being known that inductive elements are expensive to manufacture and always have a certain volume determined by the electrical properties required.
The object of the invention is to reduce the amount of inductive elements required.
The invention is characterized in that the input inductor and the commutating inductor are combined in a unit designed as a transformer which is proportioned so that the open-circuit inductance of the transformer is essentially equal to the value of the input inductor, while the short-circuit inductance of the transformer is essentially equal to the value of the commutating inductor, and that the second switch is connected in series with the dc voltage source and a first winding of the transformer.
This solution has an added advantage in that, in mass production, both the open-circuit and the short-circuit inductance are reproducible with reliability.
According to another feature of the invention, the electrical isolation between the windings of the transformer is such that the transformer operates as an isolation transformer between the supply and the subcircuits connected to a second winding or to additional windings of the transformer. In this manner, the transformer additionally provides reliable mains isolation.
According to a further feature of the invention, the second switch is connected between ground and that terminal of the first winding of the transformer not connected to the supply potential. This simplifies the control of the switch.
According to a further feature of the invention, to regulate the energy supply, the second winding of the transf
ormer is connected in series with the first switch, the commutating capacitor, and a third, bipolar switch controllable as a function of the value of a controlled variable developed in the deflection circuit.
The advantage gained by this measure lies in the fact that the control takes place on the side separated from the mains, so no separate isolation device is required for the gating of the third switch. Further details and advantages will be apparent from the following description of the accompanying drawings and from the claims. In the drawings,
FIG. 1 is a basic circuit diagram of the arrangement disclosed in German Auslegeschrift (DT-AS) No. 1,537,308;
FIG. 2 shows a first embodiment of the horizontal deflection circuit according to the invention, and
FIG. 3 shows a development of the horizontal deflection circuit according to the invention.
FIG. 1 shows the essential circuit elements of the horizontal deflection circuit known from the German Auslegeschrift (DT-AS) No. 1,537,308 referred to by way of introduction.
Connected in series with a dc voltage source UB is an input inductor Le and a bipolar, controlled switch S2. In the following, this switch will be referred to as the "second switch"; it is usually called the "commutating switch" to indicate its function.
In known circuits, the second switch S2 consists of a controlled rectifier and a diode connected in inverse parallel.
The second switch S
2 also forms part of a second circuit which contains, in addition, a commutating inductor Lk, a commutating capacitor Ck, and a first switch S1. The first switch S1, controlling the horizontal sweep, is constructed in the same manner as the above-described second switch S2, consisting of a controlled rectifier and a diode in inverse parallel. Connected in parallel with this first switch is a deflection-coil arrangement AS with a capacitor CA as well as a high voltage generating arrangement (not shown). In FIGS. 1, 2, and 3, this arrangement is only indicated by an arrow and by the reference characters Hsp. The operation of this known horizontal deflection circuit need not be explained here in detail since it is described not only in the German Auslegeschrift referred to by way of introduction, but also in many other publications.
FIGS. 2 and 3 show the horizontal deflection circuit modified in accordance with the present invention. Like circuit elements are designated by the same reference characters as in FIG. 1.
FIG. 2 shows the basic principle of the invention. The two inductors Le and Lk of FIG. 1 have been replaced by a transformer U. To be able to serve as a substitute for the two inductors Le and Lk, the transformer must be proportioned in a special manner. Regardless of the turns ratio, the open-circuit inductance of the transformer is chosen to be essentially equal to the value of the input inductor Le, and the short-circuit inductance of the transformer is essentially equal to the value of the commutating inductor Lk.
To permit the second switch S2 to be utilized for the connection of the dc voltage source UB, it is included in the circuit of that winding U1 of the transformer connected to the dc voltage UB.
In principle, it is of no consequence for the operation of the switch S2 whether it is inserted on that side of the winding U1 connected to the positive operating potential +UB or on the side connected to ground. In practice, however, the solution shown in FIGS. 2 and 3 will be chosen since the gating of the controlled rectifier is less problematic in this case.
In compliance with pertinent safety regulations, the transformer U may be designed as an isolation transformer and can thus provide mains separation, which is necessary for various reasons. It is known from German Offenlegungschrift (DT-OS) No. 2,233,249 to provide dc isolation by designing the commutating inductor as a transformer, but this measure is not suited to attaining the object of the present invention.
If the energy to be taken from the dc voltage source is to be controlled as a function of the energy needed in the horizontal deflection circuit and in following subcircuits, the embodiment of the horizontal deflection circuit of FIG. 3 may be used.
The circuit including the winding U2 of the transformer U contains a third controlled switch S3, which, too, is inserted on the grounded side of the winding U2 for the reasons mentioned above. This third switch S3, just as the second switch S2, is operated at the frequency of a horizontal oscillator HO, but a control circuit RS whose input l is fed with a controlled variable is inserted between the oscillator and the switch S3. Depending on this controlled variable, the controlled rectifier of the third switch S3 can be caused to turn on earlier. A suitable controlled variable containing information on the energy consumption is, for example, the flyback pulse capable of being taken from the high voltage generating circuit (not shown). Details of the operation of this kind of energy control are described in applicant's German Offenlegungsschrift (DT-OS) No. b 2,253,386 and do not form part of the present invention.
With mains isolation, the additional, third switch S3 shown here has the advantage of being on the side isolated from the mains and eliminates the need for an isolation device in the control lead of the controlled rectifier.
As an isolation transformer, the transformer U may also carry additional windings U3 and U4 if power is to be supplied to the audio output stage, for example; in addition, the first switch S1 may be gated via such an additional winding.
The points marked at the windings U1 and U2 indicate the phase relationship between the respective voltages. Connected in parallel with the winding U1 and the second switch S2 is a capacitor CE which completes the circuit for the horizontal-frequency alternating current; this serves in particular to bypass the dc voltage source or the electrolytic capacitors contained therein.
If required, a well-known tuning coil may be inserted, e.g. in series with the second winding U2, without changing the basic operation of the horizontal deflection circuit according to the invention.
GALAXI MOD. GALAXONE 27" CHASSIS GF77/M1702 Electron beam deflection circuit including thyristors Further Discussion and deepening of knowledge, Thyristor horizontal output circuits: (ZEILEN ABLENKUNG MIT THYRISTOR SCHALTUNG)
2. A deflection circuit as claimed in claim 1, wherein said amount of additional current is greater than or equal to 5 per cent of the peak-to-peak value of the current flowing through the deflection winding.
3. A deflection circuit as claimed in claim 1, wherein said means for drawing a substantial amount of additional current through said first switching means comprises a resistor connected in parallel to said first capacitor.
4. A deflection circuit as claimed in claim 1, wherein said means for drawing an additional current is formed by connecting said first and second energy sources in series so that the current charging said reactive circuit means forms the said additional current.
5. A deflection circuit as claimed in claim 1, further including a series combination of an autotransformer winding and a second high-value capacitor, said combination being connected in parallel to said first switching means, wherein said autotransformer comprises an intermediate tap located between its terminals respectively connected to said first switching means and to said second capacitor, said tap delivering, during said trace portion, a suitable DC supply voltage lower than the voltage across said second capacitor; and wherein said means for drawing a substantial amount of additional current comprises a load to be fed by said supply voltage and having one terminal connected to ground; and further controllable switching means controlled to conduct during at least part of said trace portion and to remain cut off during said retrace portion, said further switching means being connected between said tap and the other terminal of said load.
The present invention constitutes an improvement in the circuit described in U.S. Pat. No. 3,449,623 filed on Sept. 6, 1966, this circuit being described in greater detail below with reference to FIGS. 1 and 2 of the accompanying drawings. A deflection circuit of this type comprises a first thyristor switch which allows the conenction of the horizontal deflection winding to a constant voltage source during the time interval used for the transmisstion of the picture signal and for applying this signal to the grid of the cathode ray tube (this interval will be termed the "trace portion" of the scan), and a second thyristor switch which provides the forced commutation of the first one by applying to it a reverse current of equal amplitude to that which passes through it from the said voltage source and thus to initiate the retrace during the horizontal blanking interval.A undirectional reverse blocking triode type thyristor or silicon controlled rectifier (SCR), such as that used in the aformentioned circuit, requires a certain turn-off time between the instant at which the anode current ceases and the instant at which a positive bias may be applied to it without turning it on, due to the fact that there is still a high concentration of free carriers in the vicinity of the middle junction, this concentration being reduced by a process of recombination independently from the reverse polarity applied to the thyristor. This turn-off time of the thyristor is a function of a number of parameters such as the junction temperature, the DC current level, the decay time of the direct current, the peak level of the reverse current applied, the amplitude of the reverse anode to cathode voltage, the external impedance of the gate electrode, and so on, certain of these varying considerably from one thyristor to another.
In horizontal deflection circuits for television receivers, the flyback or retrace time is limited to approximately 20 percent of the horizontal scan period, the retrace time being in the case of the CCIR standard of 625 lines, approximately 12 microseconds and, in the case of the French standard of 819 lines, approximately 9 microseconds. During this relatively short interval, the thyristor has to be rendered non-conducting and the electron beam has to be returned to the origin of the scan. The first thyristor is blocked by means of a series resonant LC circuit which is subject to a certain number of restrictions (limitations as to the component values employed) due to the fact that, inter alia, it simultaneously determines the turn-off time of the circuit which blocks the thyristor and it forms part of the series resonant circuit which is to carry out the retrace. To obtain proper operation of the deflection circuit of the aforementioned Patent, especially when used for the French standard of 819 lines per image, the values of the components used have to subject to very close tolerances (approximately 2%), which results in high costs.
The improved deflection circuit, object o
According to the invention, there is provided an electron beam deflection circuit for a cathode ray tube with electromagentic deflection by means of a sawtooth current waveform having a trace portion and a retrace portion, said circuit comprising: a deflection winding; a first source of electrical energy formed by a first capacitor; first controllable switching means comprising a parallel combination of a first thyristor and a first diode, connected together to conduct in opposite directions, for connecting said winding to said first source during said trace portion when said first switching means is turned on; a second source of electrical energy including a first inductive energy storage means coupled to a voltage supply; reactive circuit means including a combination of inductive and capacitive reactances for storing the energy supplied by the said second source; a second controllable switching means, substantially identical with the first one, for completing a circuit including said reactive circuit means and said first switching means, when turned on, so as to pass through said first thyristor an oscillatory current in the opposite direction to that which passes through it from said first source and to turn it off after these two currents cancel out, the oscillatory current then flowing through said first diode for an interval termed the circuit turn-off time which has to be greater than the turn-off time of said first thyristor; and means for drawing duing at least a part of said trace portion a substantial amount of additional current from said first switching means in the direction of conduction of said first diode, whereby said circuit turn-off time is lengthened in proportion to the amount of said additional current, without altering the values of the reactances in the reactive circuit by shifting the waveform of the current flowing through said first switching means towards the negative by an amount equal to that of said additional current.
A further object of the invention consists in using the supplementary current in the recovery diode of the first switching means to produce a DC voltage which may be used as a power supply for the vertical deflection circuit of the television receiver, for example.
The invention will be better understood and other features and advantages thereof will become apparent from the following description and the accompanying drawings, given by way of example, and in which:
FIG. 1 is a schematic circuit diagram partially in bloc diagram form of a prior art deflection circuit according to the aforementioned Patent;
FIG. 2 shows waveforms of currents and voltages generated at various points in the circuit of FIG. 1;FIG. 3 is a schematic diagram of a deflection circuit according to the invention which allows the principle of the improvement to be explained;
FIG. 4 is a diagram of the waveforms of the current through the first switching means 4, 5 of the circuit of FIG. 3;
FIG. 5 is a circuit diagram of another embodiment of the circuit according to the invention;
FIG. 6 is a schematic representation of the preferred embodiment of the circuit according to the invention; and
FIG. 7 shows voltage waveforms at various points of the high voltage autotransformer 21 of FIG. 6.
In all these Figures the same reference numerals refer to the same components.
FIG. 1 shows the horizontal deflection circuit described and claimed in the U.S. Pat. No. 3,449,623 mentioned above, which comprises a first source of electrical energy in the shape of a first capacitor 2 having a high capacitance C 2 for supplying a substantially constant voltage Uc 2 across its terminals. A first terminal of the first capacitor 2 is connected to ground, whilst its second terminal which supplies a positive voltage is connected to one of the terminals of a horizontal deflection winding shown as a first inductance 1. A first switching means 3, consisting of a first reverse blocking triode thyristor 4 (SCR) and a first recovery diode 5 in parallel, the two being interconnected to conduct current in opposite directions, is connected in parallel with the series combination formed by the deflection winding 1 and the first capacitor 2. The assembly of components 1, 2, 4 and 5 forms the final stage of the horizontal deflection circuit in a television receiver using electromagnetic delfection.The deflection circuit also includes a drive stage for this final stage which here controls the turning off of the first thyristor 4 to produce the retrace or fly-back portion of the scan during the line-blanking intervals i.e. while the picture signal is not transmitted. This driver stage comprises a second voltage source in the shape of a DC power supply 6 which delivers a constant high voltage E. The negative terminal of the power supply 6 is connected to ground and its positive terminal to one of the terminals of a second inductance 7 of relatively high value, which draws a substantially lineraly varying current from the power supply 6 to avoid its overloading. The other terminal of th
The respective values of the third inductance 8 (L 8 ) and of the second capacitor 9 (C 9 ) are principally selected so that, on the one hand, one half-cycle of oscillation of the first series resonant circuit L 8 - C 9 , (i.e. π √ L 8 . C 9 ) is longer than the turn-off time of the first thyristor 4, but still is as short as possible since this time interval determines the speed of the commutation of the thyristor 4, and, on the other hand, one half-cycle of oscillation of another series resonant circuit formed by L 1 , L 8 and C 9 , i.e. π √ (L 1 + L 8 ) . C 9 , is substantially equal to the required retrace time interval (i.e. shorter than the horizontal blanking interval).
The gate (control electrode) of the second thyristor 11 is coupled to the output of the horizontal oscillator 13 of the television receiver by means of a first pulse transformer 14 and a first pulse shaping circuit 15 so that it is fed short triggering pulses which are to turn it on.
The gate of the first thyristor 4 fed with signals of a substantially rectangular waveform which are negative during the horizontal blanking intervals, is coupled to a winding 16 by means of a second pulse shaping circuit 17, the winding 16 being magnetically coupled to the second inductance 7 to make up the secondary winding of a transformer of which the inductance 7 forms the primary winding. It will be noted here that it is also possible to couple the secondary winding 16 magnetically to a primary winding connected to a suitable output (not shown) of the horizontal oscillator 13.
The operation of a circuit of this type will be explained below with reference to FIG. 2 which shows the waveforms at various points in the circuit of FIG. 1 during approximately one line period.
FIG. 2 is not to scale since one line period (t 7 - t 0 ) is equal to 64 microseconds in the case of 625 lines and 49 microseconds in the case of 819 lines, while the durations of the respective horizontal blanking intervals are approximately 12 and 9.5 microseconds.Waveform A shows the form of the current i L1 passing through deflection winding 1, this current having a sawtooth waveform substantially linear from t 0 to t 3 and from t 5 to t 7 , and crossing zero at time instants t 0 and t 7 , and reaching values of + I 1m and - I 1m , at time instants t 3 and t 5 respectively, these being its maximum positive and negative amplitudes.
During the second half of the trace portion of the horizontal deflection cycle, that is to say from t 0 to t 3 , the thyristor 4 of the first switching means 3 is conductive and makes the high value capacitor 2 discharge through the deflector winding 1, which has a high inductance, so that current i L1 increases linearly.
A few microseconds (5 to 8 μ s) before the end of the trace portion, i.e. at time instant t 1 , the trigger of the second thyristor 11 receives a short voltage pulse V G11 which causes it to turn on as its anode is at this instant at a positive potential with respect to ground, which is due to the charging of the second capacitor 9 through inductances 7 and 8 by the voltage E from the power supply 6.
When thyristor 11 is made conductive at time t 1 , on the one hand, inductance 7 is connected between ground and the voltage source 6 and a linearly increasing current flows through it and, on the other hand, the reactive circuit 8, 9 forms a loop through the second and first switching means 10 and 3, thus forming a resonant circuit which draws an oscillatory current i 8 ,9 of frequency ##EQU1##
This oscillatory current i 8 ,9 will pass through the first switching means 3, i.e. thyristor 4 and diode 5, in the opposite direction to that of current i L1 . Since the frequency f 1 is high, current i 8 ,9 will increase more rapidly than i L1 and will reach the same level at time t 2 , that is to say i 8 ,9 (t 2 ) = -i L1 (t 2 ) and these currents will cancel out in the thyristor 4 in accordance with the well known principle of forced commutation. After time instant t 2 , current i 8 ,9 continues to increase more rapidly than i L1 , but the difference between them (i 8 ,9 - i L1 ) passes the diode 5 (see wave form B) until it becomes zero at time instant t 3 which is the turn off time instant of the first switching means 3, at which the retrace begins.
The interval between the time instant t 2 and t 3 , i.e. (t 3 -t 2 ), during which diode 5 is conductive and the thyristor is reverse biased will be termed in what follows the circuit turn-off time and it should
At time instant t 3 , the switching means 3 is opened (i 4 and i 5 are both zero -- see waveforms B and C) and the reactive circuit 8, 9 forms a loop through capacitor 2 and the deflection coil 1 and thus a series resonant circuit including (L 1 + L 8 ) and C 9 , C 2 being of high value and representing a short circuit for the flyback frequency ##EQU2## thus obtained.
The retrace which stated at time t 3 takes place during one half-cycle of the resonant circuit formed by reactances L 1 , L 8 and C 9 , i.e. during the interval between t 3 and t 5 . In the middle of this interval i.e. at time instant t 4 , both i L1 (waveform A) and i 8 ,9 (waveform D) pass through zero and change their sign, whereas the voltage at the terminals of the first switching means 3 (V 3 , waveform E) passes through a maximum. Thus, from t 4 onwards, thyristor 11 will be reverse biased and diode 12 will conduct the current from the resonant circuit 1, 8 and 9 in order to turn the second thyristor 11 off.
At time instant t 5 , when current i L1 has reached - I 1m and when voltage v 3 falls to zero, diode 5 of the first switching means 3 becomes conductive and the trace portion of scan begins.
Current i 8 ,9 nevertheless continues to flow in the resonant circuit 8, 9 through diodes 5 and 12, which causes a break to appear in waveform D at t 5 , and a negative peak to appear in waveform D and a positive one in waveform B in the interval between t 5 and t 6 , these being principally due to the distributed capacities of coil 1 or to an eventual capacitor (not shown) connected in parallel to the first switching means 3.
At time instant t 6 , diode 12 of the second switching means 10 ceases to conduct after having allowed thyristor 11 time to become turned off completely.
The level of current i 8 ,9 at time instant t 5 (i.e. I c ) as well as the negative peak I D12 in i 8 ,9 and the positive peak I D5 in i 5 depend on the values of L 8 and C 9 in the same way as does the turn-off time of the circuit (t 3 - t 2 ). If, for example, L 8 and C 9 , are increased I D5 increases towards zero and this could cause diode 5 to be cut off in an undesirable fashion. I c also increases towards zero, which is liable to cause diode 12 to be blocked and thyristor 11 to trigger prematurely.
From the foregoing it can be clearly seen that the choice of values for L 8 and C 9 is subject to four limitations which prevent the values from being increased to lengthen the turn-off time of the driver circuit of first switching thyristor 4 so as to forestall its spurious triggering.
Waveform F shows the voltage v G4 obtained at the gate of thyristor 4 from the secondary winding 16 coupled to the inductor 7. This voltage is positive from t 0 to t 1 and from t 6 to t 7 and is negative between t 2 and t 6 i.e. while the second switching means 10 is conducting.
The present invention makes the lengthening of the turn-off time of thyristor 4 possible without altering the parameters of the circuit such as inductance 8 and capacitor 9.
In the circuit shown in FIG. 3, which illustrates the principle of the present invention, means are added to the circuit in FIG. 1 which enable the turn-off time to be lengthened by connecting a load to diode 5 so as to increase the current which flows through it during the time that it is conductive. These means are here formed by a resistor 18 connected in parallel with a capacitor 20 (which replaces capacitor 2) which is of a higher capacitance so that, in practice, it holds its charge during at least one half of the line period. FIG. 4, which shows the waveform of the current in the first switching means 3 for a circuit as shown in FIG. 3, makes it possible to explain how this lenthening of the turn-off time is achieved.In FIG. 4, the broken lines show the waveform of the current in the first switch device 3 in the circuit of FIG. 1, this waveform being produced by adding waveforms B and C of FIG. 2. The current i 4 above the axis flows through thyristor 4 and current i 5 below the axis flows through diode 5. When the capacitance C 20 of the capacitor in series with the deflector coil is increased to some tens of microfarads (C 2 having been of the order of 1 μ F) and when there is connected in parallel with capacitor 20 a resistor 18 the value of which is calculated to draw a strong current I R18 from capacitor 20, that is to say a current at least equal to 0,1 I m (I m being of the order of some tens of amperes), current I R18 is added to that i 5 which flows through diode 5 without in any way altering the linearity of the trace portion nor the oscillatory commutation of thyristor 4 which is brought about by the resonant circuit L 8 , C 9 .
It can thus be seen in FIG. 4 that the circuit turn-off time T R of a circuit according to the invention and illustrated by FIG. 3 is distinctly longer than that T r of the circuit in FIG. 1. This increase in the turn-off time (T R - T r ) depends on the current I R18 and increases therewith.It should be noted at this point that the current I R18 produces a voltage drop at the terminals of the resistor the only effect of which is to heat up the resistor since the level of this voltage (40 to 60 volts) does not necessarily have a suitable value to be used as a voltage supply for other circuits in an existing transistorised television receiver.
In accordance with one embodiment of the invention, illustrated in FIG. 5, an application is proposed for the additional current which is to be drawn through diode 5. In FIG. 5, the positive terminal of capacitor 20 is connected by a conductor 19 to the negative pole of the power supply 6 and the voltage at the terminals of capacitor 20 is thus added to that E from the source 6.
In the preferred embodiment of the present invention, which is shown in FIG. 6, it is possible to cause a supplementary current of a desired value to flow through the first diode 5 while obtaining a voltage which has a suitable value for use in another circuit in the television receiver.
If the voltage at the terminals of capacitor 20 in FIG. 3 is not a usable value, it is possible to connect in parallel with the series circuit comprising the deflector coil 1 and the capacitor 2 in FIG. 1, i.e. in parallel with the terminals of the first switching means 3, a series combination of an autotransformer 21 and a high value capacitor 22 (comparable with capacitor 20 in FIGS. 3 and 5). The autotransformer 21 has a tap 23 is suitably positioned between the terminal connected to capacitor 22 at the tap 24 connected to the first switching means 3. This autotransformer 21 may be formed by the one conventionally used for supplying a very high voltage to the cathode ray tube, as described for example in U.S. Pat. No. 3,452,244; such a transformer comprises a voltage step-up winding between taps 24 and 25, which latter is connected to a high voltage rectifier (not shown).
The waveform of the voltage at the various points in the autotransformer is shown in FIG. 7, in which waveform A shows the voltage at the terminals of capacitor 22, waveform B the voltage at tap 24 and waveform C the voltage at tap 23 of the autotransformer 21.
The voltage V c22 at the terminals of capacitor 22 varies slightly about a mean value V cm . It is increasing while diode 5 is conducting and decreasing during the conduction of the thyristor 4.
The voltage v 24 at tap 24 follows substantially the same curve as waveform E in FIG. 2, that is to say that during the retrace time interval from t 13 to t 5 to a positive pulse called the flyback pulse is produced and, during the time interval while the first switching means 3 is conducting, the voltage is zero. The mean valve of the voltage v 24 at tap 24 of the auto-transformer 21 is equal to the mean value V cm of the voltage at the terminals of capacitors 2 and 22.
Thus, there is obtained at tap 23 a waveform which is made up, during the retrace portion, of a positive pulse whose maximum amplitude is less than that of v 24 at tap 24 and, during the trace portion, of a substantially constant positive voltage, the level V of which is less than the mean value V cm of the voltage v c22 at the terminals of capacitor 22. By moving tap 23 towards terminals 24 the amplitude of the pulse during fly-back increases while voltage V falls and conversely by moving tap 23 towards capacitor 22 voltage V increases and the amplitude of the pulse drops.
In more exact terms, the voltage V at tap 23 is such that the means value of v 23 is equal to V cm . It has thus been shown that by choosing carefully the position of tape 23, a voltage V may be obtained during the trace portion of the scan, which may be of any value between V cm and zero.
It may easily be seen that the DC collector/emitter current in transistor 26 flows through the first diode 5 of the first switching means 3 via a resistor 28 and the part of the winding of auto-transformer 21 located between taps 23 and 24.
Experience has shown that a circuit as shown in FIG. 6 can supply 24 volts with a current of 2 amperes to the vertical deflection circuit of the same television set, the voltage at the terminals of capacitor 22 being from 50 to 60 volts.
It should be mentioned that, when the circuit which forms the load of the controlled rectifier 26, 27 does not draw enough current to sufficiently lengthen the circuit turn-off time T R , an additional resistor (not shown) may be connected between the emitter of transistor 26 and ground or in parallel to capacitor 22, which resistor will draw the additional current required.
In a television deflection system
1. In a television deflection system in which a first switching means couples a deflection winding across a source of energy during a trace interval of each deflection cycle and a second switching means replenishes energy to said source of energy during a commutation interval of each deflection cycle, a gating circuit for said first switching means, comprising:
capacitive voltage divider means coupled in parallel with said second switching means for developing gating signals proportional to the voltage across said second switching means; and
means for coupling said voltage divider means to said first switching means to provide for conduction of said first switching means in response to said gating signals.
2. A gating circuit according to claim 1 wherein said voltage divider includes first and second capacitors coupled in series and providing said gating signals at the common terminal of said capacitors. 3. A gating circuit according to claim 2 wherein said first and second capacitors are proportional in value to provide for the desired magnitude of gating signals. 4. A gating circuit according to claim 3 wherein said means for coupling said voltage divider means to said first switching means includes an inductor. 5. A gating circuit according to claim 4 wherein said inductor and said first and second capacitors comprise a resonant circuit having a resonant frequency chosen to shape said gating signal to improve switching of said first switching means.BACKGROUND OF THE INVENTION
This invention relates to a gating circuit for controlling a switching device employed in a deflection circuit of a television receiver.
Various deflection system designs have been utilized in television receivers. One design employing two bidirectional conducting switches and utilizing SCR's (thyristors) as part of the switches is disclosed in U.S. Pat. No. 3,452,244. In this type deflection system, a first
SCR is
employed for coupling a deflection winding across a source of energy during a trace interval of each deflection cycle, and a second SCR is employed for replenishing energy during a commutation interval of each deflection cycle. The first SCR is commonly provided with gating voltage by means of a separate winding or tap of an input reactor coupling a source of B+ to the second SCR.
Various regulator system designs have been utilized in conjunction with the afore described deflection system to provide for uniform high voltage production as well as uniform picture width with varying line voltage and kinescope beam current conditions.
One type regulator system design alters the amount of energy stored in a commutating capacitor coupled between the first and second SCR's during the commutating interval. A regulator design of this type may employ a regulating SCR and diode for coupling the input reactor to the source of B+. With this type regulator a notch, the width of which depends upon the regulation requirements, is created in the current supplied through the reactor and which notch shows up in the voltage waveform developed on the separate winding or tap of the input reactor which provides the gating voltage for the first SCR. The presence of the notch, even though de-emphasized by a waveshaping circuit coupling the gating voltage to the first SCR, causes erratic control of the first SCR.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the invention, a gating circuit of a television deflection system employing a first switching means for coupling a deflection winding across a source of energy during a trace interval of each deflection cycle and a second switching means for replenishing energy to said source of energy during a commutation interval of each deflection cycle includes a voltage divider means coupled in parallel with the second switching means for developing gating signals proportional to the voltage across the second switching means. The voltage divider means are coupled to the first switching means to provide for conduction of the first switching means in response to the gating signals.
A more detailed description of a preferred embodiment of the invention is given in the following description and accompanying drawing of which:
FIG. 1 is a schematic diagram, partially in block form, of a prior art SCR deflection system;
FIG. 2 is a schematic diagram, partially in block form, of an SCR deflection system of the type shown in FIG. 1 including a gating circuit embodying the invention;
FIG. 3 is a schematic diagram, partially in block form, of one type of a regulator system which employs an SCR as a control device and which is suitable for use with the SCR deflection system of FIG.2;
FIG. 4 is a schematic diagram, partially in block form, of another type of a regulator system suitable for use with the deflection circuit of FIG. 2; and
FIG. 5 is a schematic diagram, partially in block form, of still another type of a regulator system suitable for use with the SCR deflection system of FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 is a schematic diagram, partially in block form, of a prior art deflection system of the retrace driven type similar to that disclosed in U.S. Pat. No. 3,452,244. This system includes a commutating switch 12, comprising a silicon controlled rectifier (SCR) 14 and an oppositely poled damper diode 16. The commutating switch 12 is coupled between a winding 18a of an input choke 18 and ground. The other terminal of winding 18a is coupled to a source of direct current voltage (B+) by means of a regulator network 20 which controls the energy stored in the deflection circuit 10 when the commutating switch is off, during an interval T3 to T0' as shown in curve 21 which is a plot of the voltage level at the anode of SCR 14 during the deflection cycle. A damping network comprising a series combination of a resistor 22 and a capacitor 23 is coupled in parallel with commutating switch 12 and serves to reduce any ringing effects produced by the switching of commutating switch 12. Commutating switch 12 is coupled through a commutating coil 24, a commutating capacitor 25 and a trace switch 26 to ground. Trace switch 26 comprises an SCR 28 and an oppositely poled damper diode 30. An auxiliary capacitor 32 is coupled between the junction of coil 24 and capacitor 25 and ground. A series combination of a horizontal deflection winding 34 and an S-shaping capacitor 36 are coupled in parallel with trace switch 26. Also, a series combination of a primary winding 38a of a horizontal output transformer 38 and a DC blocking capacitor 40 are coupled in parallel with trace switch 26.
A secondary of high voltage winding 38b of transformer 38 produces relatively large amplitude flyback pulses during the retrace interval of each deflection cycle. This interval exists between T1 and T2 of curve 41 which is a plot of the current through windings 34 and 38a during the deflection cycle. These flyback pulses are applied to a high voltage multiplier (not shown) or other suitable means for producing direct current high voltage for use as the ultor voltage of a kinescope (not shown).
An auxiliary winding 38c of transformer 38 is coupled to a high voltage sensing and control circuit 42 which transforms the level of flyback pulses into a pulse width modulated signal. The control circuit 42 is coupled to the regulator network 20.
A horizontal oscillator 44 is coupled to the gate electrode of commutating SCR 14 and produces a pulse during each deflection cycle slightly before the end of the trace interval at T0 of curve 21 to turn on SCR 14 to initiate the commutating interval. The commutating interval occurs between T0 and T3 of curve 21. A resonant waveshaping network 46 comprising a series combination of a capacitor 48 and an inductor 50 coupled between a winding 18b of input choke 18 and the gate electrode of trace SCR 28 and a damping resistor 52 coupled between the junction of capacitor 48 and inductor 50 and ground shapes the signal developed at winding 18b (i.e. voltage waveform 53) to form a gating signal voltage waveform 55 to enable SCR 28 for conduction during the second half of the trace interval occurring between T2 and T1' of curve 41.
The regulator network 20, when of a type to be described in conjunction with FIG. 3, operates in such a manner that current through winding 18a of input choke 18 during an interval between T4 and T5 (region A) of curves 21, 53 and 55 is interrupted for a period of time the duration of which is determined by the signal produced by the high voltage sensing and control circuit 42. During the interruption of current through winding 18a a zero voltage level is developed by winding 18b as shown in interval T4 to T5 of curve 53. The resonant waveshaping circuit 46 produces the shaped waveform 55 which undesirably retains a slump in region A corresponding to the notch A of waveform 53. The slump in waveform 55 applied to SCR 28 occurs in a region where the anode of SCR 28 becomes positive and where SCR 28 must be switched on to maintain a uniform production of the current waveshape in the horizontal deflection winding 34 as shown in curve 41. The less positive amplitude current occurring at region A of waveform 55 may result in insufficient gating current for SCR 28 and may cause erratic performance resulting in an unsatisfactory raster.
FIG. 2 is a schematic diagram, partially in block form, of a deflection system 60 embodying the invention. Those elements which perform the same function in FIG. 2 as in FIG. 1 are labeled with the same reference numerals. FIG. 2 differs from FIG. 1 essentially in that the signal to enable SCR 28 derived from sampling a portion of the voltage across commutating switch 12 rather than a voltage developed by winding 18b which is a function of the voltage across winding 18a of input choke 18 as in FIG. 1. This change eliminates the slump in the enabling signal during the interval T4 to T5 as shown in curve 64 since the voltage across the commutating switch 12 is not adversely effected by the regulator network 20 operation.
A series combination of resistor 22, capacitor 23 and a capacitor 62 is coupled in parallel with commutating switch 12, one terminal of capacitor 62 being coupled to ground. The junction of capacitors 23 and 62 is coupled to the gate electrode of SCR 28 by means of the inductor 50. The resistor 52 is coupled in parallel with capacitor 62.
Capacitors 23 and 62 form a capacitance voltage divider which provides a suitable portion of the voltage across commutating switch 12 for gating SCR 28 via inductor 50. The magnitude of the voltage at the junction of capacitors 23 and 62 is typically 25 to 35 volts. It can, therefore, be seen that the ratio of values of capacitors 23 and 62 will vary depending on the B+ voltage utilized to energize the deflection system. Capacitors 23 and 62 and inductor 50 form a resonant circuit tuned in a manner which provides for peaking of the curve 64 between T4 and T5. This peaking effect further enhances gating of SCR 28 between T4 and T5.
Since the waveshape of the voltage across commutating switch 12 (curve 21) is relatively independent of the type of regulator system employed in conjunction with the deflection system, the curve 64 also is independent of the type of regulator system.
When commutating switch 12 switches off during the interval T3 to T0' curve 21, the voltage across capacitor 62 increases and the voltage at the gate electrode of SCR 28 increases as shown in curve 64. As will be noted, no slump of curve 64 occurs between T3 and T5 because there is no interruption of the voltage across commutating switch 12.
FIG. 3 is a schematic diagram, partially in block form, of one type of a regulator system which may be used in conjunction with the invention. B+ is supplied through a regulator network 20 which comprises an SCR 66 and an oppositely poled diode 68. The diode is poled to provide for conduction of current from B+ to the horizontal deflection circuit 60 via winding 18a of input choke 18. Current flows through the diode during the period T3 to T4 of curve 21 FIG. 1 after which current tries to flow through the SCR 66 from the horizontal deflection circuit to B+ since the commutating capacitor 25 is charged to a voltage higher than B+.
The horizontal deflection circuit 60 produces a flyback pulse in winding 38a of the flyback transformer 38 which is coupled to winding 38c. The magnitude of the pulse on winding 38c determines how long the signal required to switch SCR 66 on is delayed after T4 curve 21 FIG. 1. If the flyback pulse is greater than desirable, the SCR 66 turns on sooner than if the flyback pulse is less than desirable and provides a discharge path for current in commutating capacitor 25 back to the B+ supply. In this manner a relatively constant amplitude flyback pulse is maintained.
FIG. 4 is a schematic diagram, partially in block form, of another well-known type of a regulator system which may be used in conjunction with the invention shown in FIG. 2. B+ is coupled through winding 18a of input choke 18 and through a series combination of windings 70a and 70b of a saturable reactor 70 and a parallel combination of a diode 72 and a resistor 74 to the horizontal deflection circuit 60. Diode 72 is poled to conduct current from the horizontal deflection circuit 60 to B+.
Flyback pulse variations are obtained from winding 38c of the horizontal output transformer 38 and applied to a voltage divider comprising resistors 76, 78 and 80 of the high voltage sensing and control circuit 42. A portion of the pulse produced by winding 38c is selected by the position of the wiper terminal on potentiometer 78 and coupled to the base electrode of a transistor 82 by means of a zener diode 84. The emitter electrode of transistor 82 is grounded and a DC stabilization resistor 85 is coupled in parallel with the base-emitter junction of transistor 82. When the pulse magnitude on winding 38c exceeds a level which results in forward biasing the base-emitter junction of transistor 82, current flows from B+ through a resistor 86, a winding 70c of saturable reactor 70 and transistor 82 to ground. Due to the exponential increase of current in winding 70c during the period of conduction of transistor 82, the duration of conduction of transistor 82 determines the magnitude of current flowing in winding 70c and thus the total inductance of windings 70a and 70b. The current in winding 70c is sustained during the remaining deflection period by means of a diode 88 coupled in parallel with winding 70c and poled not to conduct current from B+ to the collector electrode of transistor 82. A capacitor 90 coupled to the cathode of diode 88 provides a bypass for B+. Windings 70a and 70b are in parallel with input reactor 18a and thereby affect the total input inductance of the deflection circuit and thereby controls the transfer of energy to the deflection circuit. The dotted waveforms shown in conjunction with a curve 21' indicate variations from a nominal waveform provided at the input of horizontal deflection circuit 60 by the windings 70a and 70b.
FIG. 5 is a schematic diagram of yet another type of a regulator system which may be used in conjunction with the invention. B+ is coupled through a winding 92a and a winding 92b of a saturable reactor to the horizontal deflection circuit 60. Windings 92a and 92b are used to replace the input choke 18 shown in FIGS. 1 and 2 while also providing for a regulating function corresponding to that provided by regulating network 20.
Flyback pulse variations are obtained from winding 38c and applied to the high voltage sensing and control circuit 42 as in FIG. 4. Current flows from B+ through resistor 86, a winding 92c and transistor 82 to ground. As in FIG. 4 the duration of the conduction of transistor 82 determines the energy stored in winding 92c and thus the total inductance of windings 92a and 92b which control the amount of energy transferred to the deflection circuit during each horizontal deflection cycle. The variations in waveforms of curve 21', shown in conjunction with FIG. 4, are also provided at the input of horizontal deflection circuit 60 by windings 92a and 92b.
For various reasons including cost or performance, a manufacturer may wish to utilize a particular one of the regulators illustrated in FIGS. 3, 4 and 5. Regardless of the choice, the gating circuit according to the invention may be utilized therewith advantageously by providing improved performance and the possibility of cost savings by eliminating taps or extra windings on the wound components which heretofore normally provided a source of SCR gating waveforms.
GALAXI MOD. GALAXONE 27" CHASSIS GF77/M1702 E/W CORRECTION CIRCUIT WITH SATURABLE REACTOR FOR CORRECTING RASTER DISTORTION:
1. Saturable reactor apparatus comprising a ferrite core including a central part and a shaft extending in opposite directions therefrom and flanges on the shaft defining spaces on opposite sides of the central part, primary and secondary windings on the shaft in each of said spaces and in close coupling relationship, the secondary windings being oppositely wound, permanent magnets at opposite ends of the shaft to generate flux in said core, and means to control the thusly generated flux. 2. Apparatus as claimed in claim 1 wherein said means includes means to vary the position of the permanent magnets relative to said shaft. 3. Apparatus as claimed in claim 1 wherein said means includes a further permanent magnet adjacent the core and rotatable about an axis perpendicular to said shaft. 4. Apparatus as claimed in claim 1 wherein said magnets are of plate-form. 5. Apparatus as claimed in claim 1 comprising horizontal and vertical deflection deflection television-receiver circuits generating horizontal and vertical deflection currents, and means for respectively coupling the currents to said primary and secondary windings. 6. Apparatus as claimed in claim 3 wherein said further magnet is of circular form and has peripheral magnetic poles therein. 7. Apparatus as claimed in claim 2 wherein the latter said means includes threaded rods.
A saturable reactor comprised of a cross-shaped core having a yoke on the center portion thereof and protrusions at right angles to the yoke and two coils wound on the yoke. Each coil of the said two coils is divided into two coil parts which are wound on the right and left yoke arms. The first pair of the said two coils is constituted so as to be identical as to the direction of the magnetic generation as is the pair of coils wound on the right and left yoke arms. The second pair of coils is constituted so as to be opposite to each other as to the direction of magnetic flux generation as is the pair of coils wound on the right and left yoke arms.
The present invention relates to a reactor for controlling or modifying "pincushion" type distortion in cathode ray tube displays. It is particularly well suited for use in conjunction with color display tubes.
One approach, which has been adopted in connection with the correction of pincushion distortion in color displays involves modulation or variation of one of the sweep currents in such a manner as to produce the desired results.
In the arrangement for correction of raster distortion occurring in the vertical direction (e.g., top and bottom pincushion distortion), the cyclically varying vertical scanning current must be modulated at a higher horizontal rate, such as by adding a horizontal rate correction current alternated parabolically to the vertical deflection current.
In the arrangement for the correction of raster distortion occurring in the horizontal direction (e.g., side pincushion distortion), the cyclically varying horizontal scanning must be varied at a lower vertical rate, since the magnitude of a horizontal scanning must be varied at a lower vertical rate, since the magnitude of a horizontal scanning current is parabolical.
It has further been suggested in the prior art that this modulation be accomplished electromagnetically using a combination of magnetic and electrical circuitry which works on the principle of magnetic saturability.
In general, nominal correction can be produced by this means. There are many kinds of saturable reactor device and circuit connections for correcting pincushion distortion such as those described in U.S. Pats. No. 2,906,919, No. 3,346,765, and No. 3,444,422.
The existing reactor, as seen in the aforementioned U.S. patents, is composed of a core that mutually couples the two ends of three parallel yokes, a coil is shunt-wound on the two yokes on both sides of the said core in opposite winding direction and is connected in series, and another coil is wound on the center of the said core. Since the vertical deflection current has been applied to one of the above-mentioned coils and the horizontal deflection current has been applied to the other coil, the device has disadvantages as described herein.
In the manufacture of a reactor, coils are fitted to respective yokes of an E-shaped core, and I-shaped cores are coupled on the free ends of the yokes of the E-shaped core in order to magnetically couple the yokes. Using this process, the manufacturing process has been time-consuming, making it unsuited to mass-production. Magnetic flux leakage has been small, since the yokes formed a closed magnetic path. However, since current magnetic flux density in the closed magnetic path varied markedly depending on the infinitesimal differences in the gaps in the magnetic path, the characteristics of individual products lost uniformity because of disparity in the gap arising in the coupled part of the E-shaped core and the I-shaped core.
The present invention offers saturable reactors extremely easy to assemble and manufacture and with uniform quality of individual products.
SUMMARY
FRAME DEFLECTION INTEGRATED CIRCUIT
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit a
BACKGROUND OF THE INVENTION
The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.
The TDA2530 is an integrated RGB -matrix preamplifier for colour television receivers,
incorporating a matrix preamplifier for RGB cathode drive of the picture tube with
clamping circuits.
The three channels have the same layout to ensure identical frequencybehaviour.
This integrated circuit has been designed to be driven from the TDA2522 Synchronous
demodulator and oscillator IC.
TDA2522 PAL TV CHROMA DEMODULATOR COMBINATION
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION- The TDA2522 is a monolithic integrated circuit designed as
a synchronous demodulator for PAL color television receivers. It includes an 8,8 MHz
oscillator and divider to generate two 4.4 MHz reference signals and provides color difference outputs.
PACKAGE OUTLINE 9B
The TDA2522 is Intended to Interface directly with the TDA2560 with a minimum oF external components. The TDA2530 may be added if RGB drive is required. The TDA2522
is constructed using the Fairchild Planar* process.
TDA2560 LUMINANCE AND CHROMINANCE CONTROL COMBINATION
The TDA2560 is a monolithic integrated circuit for use in decoding systems of COLOR
television receivers. The circuit consists of a luminance and chrominance amplifier.
The luminance amplifier has a low input impedance so that matching of the luminance
delay line is very easy.
It also incorporates the following functions:
- d.c. contrast control;
- d.c. brightness control;
- black level clamp;
- blanking;
- additional video output with positive-going sync.
The chrominance amplifier comprises:
- gain controlled amplifier;
- chrominance gain control tracked with contrast control;
- separate d.c. saturation control:
- combined chroma and burst output, burst signal amplitude not affected by contrast and
saturation control;
- the delay line can be driven directly ‘by the IC.
APPLICATION INFORMATION (continued)
The function is quoted against the corresponding pin number
Balanced chrominance input signal (in conjunction with pin 2)
This is derived from the chrominance signal bandpass filter, designed to provide a
push-pull input. A signal amplitude of at least 4 mV peak-to-peak is required
between pins l and 2. The chrominance amplifier is stabilized by an external feedback
loop from the output (pin 6) to the input (pins I and 2). The required level at pins l
and 2 will be 3 V.
All figures for the chrominance signals are based on a colour bar signal with 75%
saturation: i.e. burst-to-chrominance ratio of input signal is 1 1 2.
Chrominance signal input (see pin 1)
A. C.C. input
A negative-going potential, starting at +l,2 V, gives a 40 dB range of a. c. c.
Maximum gain reduction is achieved at an input voltage of 500 mV.
Chrominance saturation control
A control range of +6 dB to >-14 dB is provided over a range of d. c. potential on
pin 4 from +2 to +4 V. The saturation control is a linear function of the control
voltage.
Negative supply (earth)
Chro minance signal output
For nominal settings of saturation and contrast controls (max. -6 dB for saturation,
and max. -3 dB for contrast) both the chroma' and burst are available at this pin, and
in the same ratio as at the input pins 1 and 2. The burst signal is not affected by the
saturation and contrast controls. The a.c. c. circuit of the TDA2522 will hold
constant the colour burst amplitude at the input of the TDA2522. As the PAL delay
line is situated here between the TDA256O and TDA2522 there may be some variation
of the nominal 1 V peak-to-peak burst output of the TDA2560, according to the
tolerances of the delay line. An external network is required from pin 6 of the
TDA256O to provide d. c. negative feedback in the chroma channel via pins I and 2.
Burst gating and clamping pulse input
A two-level pulse is required at this pin to be used for burst gate and black level
clamping. The black level clamp is activated when the pulse level is greater than
7 V. The timing of this interval should be such that no appreciable encroachment
occurs into the sync pulse on picture line periods during normal operation of the
receiver. The burst gate, which switches the gain of the chroma amplifier to
maximum, requires that the input pulse at pin 7 should be sufficiently wide, at least
8 ps, at the actuating level of 2,3 V.
Correct operation occurs within the range 10 to 14 V. All signal and control levels
have a linear dependency on supply voltage but, in any given receiver design, this
range may be restricted due to considerations of tracking between the power supply
variations and picture contrast and chroma levels.
Flyback blanking input waveform
This pin is used for blanking the luminance amplifier. When the input pulse exceeds
the +2, 5 Vlevel, the output signal is blanked to a level of about 0 V. When the input
exceeds a +6 V level, a fixed level of about 1, 5 V is inserted in the output. This
level can be used for clamping purposes.
Luminance sigal output
An emitter follower provides a low impedance output signal of 3 V black-to-white
amplitude at nominal contrast setting having a black level in the range 1 to 3 V. An
external emitter load resistor is not required.
The luminance amplitude available for nominal contrast may be modified according
to the resistor value from pin 13 to the +12 V supply. At an input bias current
level shift more than 10 mV occurs at contrast control. When the input current
deviates from the quoted value the black level shift amounts to 100 mV/rnA.
Brightness control
The black level at the luminance output (pin 10) is identical to the control voltage
required at this pin, A range of black level from l to 3 V may be obtained.
Black level clamp capacitor
Luminance gain setting resistor
The gain of the luminance amplifier may be adjusted by selection of the resistor
value from pin 13 to +12 V. Nominal luminance output amplitude is then 3 V
black-to-white at pin 10 when this resistor is 2, 7.
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