INDESIT TYPE TC26SI CHASSIS B VV708 490-141-M INTERNAL VIEW.

The INDESIT CHASSIS VV708 was very reliable and gave few problems.

This is the last with DELTA GUN CRT TUBE TYPE and was first colot tv  chassis based on THYRISTOR horizontal deflection technology chassis by INDESIT CALLED  CHASSIS B replacing an earlyer INDESIT with tubes CALLED CHASSIS  A which have had deflection circuits with tubes (PL519....).

WAS even first INDESIT featuring Electronic Memory tuning system combined with ultrasonic remote control system. Earlyer models were only keyboard featured both mechanical and/or sensoric buttons.

TBA920 line oscillator combination
DESCRIPTION
The line oscillator combination TBA920 is a monolithic
integrated circuit intended for the horizontal deflection of the black and white
and colour TV sets
picture tube.

FEATURES:
SYNC-PULSE SEPARATION
OPTIONAL NOISE INVERSION
GENERATION OF A LINE FREQUENCY VOL-
TAGE BY MEANS OF AN OSCILLATOR
PHASE COMPARISON BETWEEN SYNC-
PULSE AND THE OSCILLATOR WAVEFORM
PHASE COMPARISON BETWEEN THE OS-
CILLATOR WAVEFORM AND THE MIDDLE OF
THE LINE FLY-BACK PULSE
AUTOMATIC SWITCHING OF THE VARIABLE
TRANSCONDUCTANCE AND THE VARIABLE
TIME CONSTANT TO ACHIEVE NOISE SUP-
PRESSION AND, BY SWITCHING OFF, POS-
SIBILITY OF TAPE-VIDEO-REGISTERED RE-
PRODUCTION
SHAPING AND AMPLIFICATION OF THE OS-
CILLATOR WAVEFORM TO OBTAIN PULSES
FOR THE CONTROL OF DRIVING STAGES IN
HORIZONTAL, DEFLECTION CIRCUITS
USING EITHER TRANSISTORS OR THYRISTORS,

INDESIT TYPE TC26SI CHASSIS VV708 490-141-M Amplifier suitable for use as a color kinescope driver:

A color kinescope matrix amplifier has a first input coupled through a capacitor to a source of color difference signals. Another input is coupled to a source of luminance signals. The matrix amplifier includes a cascode output stage direct current coupled to a cathode of a kinescope. A portion of a direct voltage developed at the cascode output amplifier is coupled to one input of a comparator circuit. The other input of the comparator circuit is coupled to a temperature compensated direct voltage reference source. The comparator is rendered operative during horizontal retrace intervals to provide a current to either charge or discharge the input capacitor in accordance with the difference between the voltage at the output of the cascode output amplifier and the reference voltage to compensate for voltage variations at the output of the cascode amplifier due to power supply variations and the like. To compensate for droop caused by the discharge of the input capacitor during the scanning interval, one input of a differential amplifier is included between the input capacitor and the input of the cascode output stage. Negative signal feedback is provided from the output stage to the other input of the differential amplifier via a capacitor arranged to be charged during the horizontal retrace interval. The two capacitors discharge at substantially the same rates during the scanning interval. By virtue of the common mode operation of the differential amplifier droop effects are minimized.


1. In a tel

evision receiver including an image reproducing device, a source of chrominance signals, a source of luminance signals and a source of horizontal blanking pulses, said horizontal blanking pulses occurring during the time interval during which said image reproducing device is horizontally retraced, the apparatus comprising:
amplifying means for combining said chrominance signals and said luminance signals, said amplifying means including first and second input terminals and an output terminal, said output terminal being direct current coupled to said image reproducing device, said second input terminal being direct current coupled to said source of said luminance signals;
first capacitive means for coupling said chrominance signals to said first input terminal;
comparator means having first and second input terminals for comparing voltages applied thereto, said comparator means being normally inoperative;
a relatively low level stabilized reference voltage source coupled to said first input terminal of said comparator means;
means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal;
means for selectively rendering said comparator operative in response to said horizontal blanking pulses; and
current converting means coupled to said comparator and to said first capacitive means for charging and discharging said capacitive means to a direct voltage level in relation to the difference in voltage between said first and second input terminals of said comparator means so as to counteract the changes of the voltage developed at said output terminal.
2. The apparatus recited in claim 1 wherein said amplifying means includes:
a differential amplifier having first and second input terminals and an output terminal, said first input terminal being coupled to sai

d first input terminal of said amplifying means, said output terminal of said differential amplifier being coupled to said output terminal of said amplifying means;
second capacitive means coupled to said second input terminal of said differential amplifier; and
means for selectively charging said second capacitive means during said horizontal retrace interval, said first and second capacitive means being selected to have substantially equal discharging rates during the time intervals between said horizontal retrace intervals.
3. The apparatus recited in claim 2 wherein said second capacitive means is coupled between said output terminal of said amplifying means and said second input terminal of said differential amplifier. 4. The apparatus recited in claim 3 wherein said amplifying means includes a cascode amplifier coupled between the output of said differential amplifier and said output terminal of said amplifying means. 5. The apparatus recited in claim 3 wherein said amplifying means includes first and second transistors, the emitter of said first transistor being direct current coupled to the collector of said second transistor, the base of said first transistor being coupled to said first input terminal of said amplifying means, the base of said second transistor being coupled to said second input terminal of said amplifying means, the emitter of said first transist

or being coupled to said first input terminal of said differential amplifier. 6. The apparatus recited in claim 3 wherein said means for selectively charging said second capacitive means includes means for clamping the second input terminal of said differential amplifier to a predetermined voltage during said horizontal retrace interval. 7. The apparatus recited in claim 3 wherein means are provided for adjusting the portion of the voltage developed at said output terminal of said amplifying means which is coupled to said second capacitive means. 8. The apparatus recited in claim 1 wherein said means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal of said amplifying means includes means for adjusting the voltage coupled to said second input terminal of said comparator means. 9. The apparatus recited in claim 1 wherein said comparator means includes:
a differential amplifier having two input terminals and two output terminals, one of said input terminals being coupled to said reference voltage source, the other of said input terminals being coupled to said output terminal of said amplifier means; and
a current mirror circuit having an input and an output, one of said output terminals of said differential amplifier being coupled to said input terminal of said current mirror circuit, the other of said output terminals of said differential amplifier being coupled to the output of said current mirror circuit and to said first capacitor means.
10. The apparatus recited in claim 1 wherein said voltage reference source is temperature compensated. 11. In a television receiver including a color kinescope leaving a plurality of electron beam forming apparatus, a source of luminance signals, a source of a plurality of color difference signals, and a source of horizontal blanking pulses, said horizontal blanking pulses corresponding to the time interval during which said electron beams are horizontally retraced, the apparatus comprising:
a plurality of amplifiers, each of said amplifiers including
amplifying means for com

bining one of said plurality of color difference signals with said luminance signals, said amplifying means including first and second input terminals and an output terminal, said output terminal being direct current coupled to a respective one of said plurality of electron beam forming apparatus, said second input terminal being direct current coupled to said source of said luminance signals, capacitive means for coupling said one of said plurality of color difference signals to said first input terminal,
comparator means having first and second input terminals for comparing voltages applied thereto, said comparator means being normally inoperative,
means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal,
means for selectively rendering said comparator operative in response to said horizontal blanking pulses, and
current converting means coupled to said comparator and to said capacitive means for charging and discharging said capacitive means to a direct voltage level in relation to the difference in voltage between said first and second input terminals of said comparator means so as to counteract the changes of the voltage developed at said output terminal; and a relatively low level stabilized reference
voltage source coupled to said first input terminals of each of said plurality of comparator means.

Description:

The present invention is directed to the field of amplifiers and is particularly directed to the field of amplifier arrangements utilized to drive color image reproducing devices such as kinescopes.
The electron guns of a color kinescope are typically driven by separate amplifier stages. Variations of the operating conditions of an amplifier stage, such as variations of the stage's supply voltage, tend to produce variations in the brightness of a reproduced image. Furthermore, because each of the stages tends to operate at different power dissipation levels the operating conditions of the stages vary with respect to each other and hence color imbalances may occur.
Athou
gh supply voltage regulators and high level clamping circuits have been employed in conjunction with kinescope amplifier stages to inhibit the aformentioned problems, it is desirable to provide kinescope driver amplifier arrangements which maintain their operating point stability with variations in operating conditions such as power supply variations without the need of supply voltage regulators or high level clamping circuits.

Furthermore, it is desirable, because of the trend toward miniaturization in electronic art, that at least a portion of the kinescope amplifier driver should be able to be constructed in integrated circuit form.
It is also desirable to provide kinescope driver amplifier arrangements which include independent controls for adjusting the DC level and the AC amplitude of the signals coupled to the kinescope. This is particularly desirable where "precision-in-line" kinescopes or the like, in which the electron guns have common control electrodes, are employed since, in these types of kinescopes, it is difficult to independently adjust the operating conditions associated with the respective guns because of the commonality of control electrodes.
Furthermore, it is desirable that a kinescope driver amplifier which is to be utilized with a precision-in-line type of kinescope provide a relatively wide bandwidth without the requirement of high frequency peaking coils. Peaking coils tend to be bulky. In addition, undesirable voltages may be developed across a peaking coil due to the large magnetic fields which may be produced by the yokes associated with a precision-in-line kinescope. These undesirable voltages may produce disconcerting brightness and/or hue changes.
In accordance with the present invention, one input terminal of amplifying means is coupled to a source of chrominance signals through capacitive means. A second input of the amplifying means is direct current coupled to a source of luminance signals. The output terminal of the amplifying means is direct current coupled to a color image reproducing device such as a precision-in-line kinescope of the like. The amplifying means includes means for combining the luminance and chrominance signals to provide the image reproducing device with color signals. The amplifying means also includes comparator means for comparing the voltage developed at the output terminal to a reference voltage to generate a current to control the charging of the capacitive means in a manner so as to counter-act the changes of the voltage developed at the output due, for example, to changes in the power supply voltage. The comparator means is arranged to be normally inoperative and is selectively rendered operative during the horizontal retrace interval.
In accordance with another aspect of the present invention, the amplifying means includes a differential amplifier having first and second input terminals and an output terminal. The output terminal of the differential amplifier is coupled to the output terminal of the amplifying means. The first input terminal of the differential amplifier is coupled to the input terminal of the amplifying means. The second input terminal of the differential amplifying means is coupled to a second capacitive means. Means are provided for selectively charging the second capacitive means during the horizontal retrace interval. The first and second capacitive means are selected to have substantially equal discharging rates so as to compensate for any decrease in the DC content (i.e., droop) at the output terminal of the amplifying means during the scanning interval.
In accordance

with still another feature of the present invention, the second capacitive means is coupled to the output terminal of the amplifying means in a manner so as to allow adjustment of the AC gain of the amplifying means. The DC conditions of the output of the amplifying means may be controlled by controlling the portion of the voltage developed at the output terminal coupled to the comparator means.
The present invention may best be understood by reference to the following detailed description and accompanying drawing which shows, partially in block diagram form and partially in schematic form, the general arrangement of a color television receiver employing a kinescope driver amplifier arrangement constructed in accordance with the present invention .
The color television receiver includes a video signal processing unit 141 responsive to radio frequency (RF) signals, received by an antenna, for receiving in a known manner, a composite video signal comprising chrominance, luminance, sound and synchronizing signal components.
The output of video processing unit 141 is coupled to a chrominance channel 142 including a chrominance processing unit 143 and a color demodulator 144. Chrominance processing unit 143 separates chrominance signals from the composite video signal. Color demodulator 144 derives signals of the appropriate polarity representing, for example, R-Y, G-Y and B-Y color difference signal information from the chrominance signals. The TAA630 integrated circuit or similar circuit is suitable for use as color demodulator 144.
The output of video processing unit 141 is also coupled to a luminance channel 145 including a luminance processing unit 146 which amplifies and processes luminance components of the composite signal to form an output signal of the appropriate polarity representing luminance, Y, information. A brightness control unit 147 to control the DC content of luminance signal Y and a contrast control unit 148 to control the amplitude of luminance signal Y are coupled to processing unit 146.
The composite video signal is also coupled to a sync separator 149 which, in turn, is coupled to a horizontal deflection unit 151 and a vertical deflection unit 152. Horizontal deflection unit 151 is also coupled to a high voltage unit 154 which generates operating voltages for kinescope 153. Outputs from horizontal deflection unit 151 and vertical deflection unit 152 are coupled to luminance processing unit 146 to inhibit or blank luminance signal Y during the horizontal and vertical retrace intervals. Similarly, an output from horizontal deflection unit 151 may be coupled to chroma processing unit 143 or color demodulator 144 to inhibit the color difference signals during the horizontal retrace interval. Furthermore, first and second signals including positive going pulses, the pulses of each signal being coincident with the horizontal retrace or blanking interval, are coupled to matrix unit 100 to control its operation, as will appear below, via conductors 159 and 167, respectively.
The R-Y output signal and luminance signal Y are coupled to a matrix unit 100 where they are combined to form a color signal representing red (R) information. Similarly, the B-Y and G-Y color difference signals are respectively coupled to matrix-driver units 150 and 157, similar to the combination of matrix unit 100 and kinescope driver 199, where they are matrixed with luminance signal Y to produce color signals representing blue (B) and green (G) information. Since the matrix units for the various color difference signals are similar, only matrix unit 100 will be described in detail.
Matrix unit 100, enclosed within dotted line 160, is suitable for construction as an integrated circuit. The R-Y color difference signal is coupled through a capacitor 110 to the base of an NPN transistor 101 which is a

rranged as a common collector amplifier for color difference signals. Transistor 101, NPN transistor 102, resistors 178 and 184 form a summing circuit 161 for the color difference signal and luminance signal Y, the latter being direct current coupled to the base of transistor 102. The combined output of circuit 161, taken at the collector of transistor 102, is coupled to the base of an NPN transistor 105. Transistor 105 and an NPN transistor 106 form a differential amplifier 162 to which bias current is supplied from a current source including a suitably biased transistor 182. The output of differential amplifier 162, taken at the collector of transistor 105, is coupled through a level shifter, shown as the series connection of a zener diode 163, and a diode 165 to a kinescope 199. Bias current is provided for zener diode 163 and diode 165 through a resistor 183, which serves as the load resistor of transistor 105, and resistors 176 and 177.
Kinescope driver 199 comprises a cascode amplifier 164 including NPN transistors 120 and 119. The output of matrix unit 100 is coupled to the base of transistor 119 while a positive supply voltage (e.g. +12 volts) is coupled to the base of transistor 120. The output of kinescope driver 199, taken at the collector of transistor 120 is direct current coupled through a resistor 179 to the red (R) cathode of kinescope 153. The collector of transistor 120 is coupled to a source of supply voltage B+ through a load resistor 165. Supply voltage B+ is a relatively high voltage, typically, in the order of 200 to 300 vdc.
The collector of transistor 120 is also coupled to a series combination of a resistor 166 and a black level setting potentiometer 167, the latter being returned to ground. A direct voltage proportional to that at the collector of transistor 120 is developed at the wiper arm of potentiometer 167 and is coupled to one input of a voltage comparator circuit 168. Comparator 168 comprises NPN transistors 103 and 104 coupled as a differential amplifier. A second input of comparator 168, at the base of transistor 103, is coupled to a temperature compensated voltage reference (TCVR) unit 169. Voltage reference unit 169, which may, for example, be similar to that employed in the CA3085 integrated circuit manufactured by RCA Corporation, supplies a regulated reference voltage of approximately 1.6 vdc.
Voltage reference unit 169 is also coupled to the matrix portions of units 150 and 157 via conductor 155 so that a common reference voltage is coupled to the respective comparators of units 100, 150 and 157. It is noted that matrix unit 100 and the matrix portions of units 150 and 153 may be constructed as a single integrated circuit.
A current source including an NPN transistor 170 is coupled to the jointly connected emitters of transistors 103 and 104. The first horizontal blanking pulse signal generated by horizontal deflection unit 151 is coupled to the base of transistor 170 via conductor 159.
The output of differential amplifier 168 provided at the collector of NPN transistor 103 is converted to a bidirectional current by means of a current mirror circuit 180 comprising a diode-connected PNP transistor 172 and a PNP transistor 173. The collector of transistor 173 is coupled to the collector of transistor 104 and to the base of transistor 101.
The junction of resistors 166 and 167 is coupled to a signal feedback circuit comprising a series connection of a potentiometer 174 and a resistor 175. Feedback voltage developed at the wiper arm of potentiometer 174 is coupled through a capacitor 120 to the base of transistor 106 (i.e., one input of differential amplifier 162). The base of transistor 106 is returned to ground through resistor 181 and the collector-emitter junction of a transistor 108. The base of transistor 108 is coupled to horizontal deflection unit 151 to receive the first horizontal blanking pulse signal via conductor 159. An NPN transistor 107, the emitter of which is coupled to the base of transistor 106, is arranged together with resistor 181 and the collector-emitter junction of transistor 108 as an emitter follower. The base of transistor 107 is coupled to horizontal deflection unit 151 to receive the second horizontal blanking pulse signal via conductor 167. It is noted that this signal may also be generated within the IC device.
Kinescope 153 may be a precision-in-line kinescope such as the RCA type 15VADTCO1. As is described in U.S. Pat. No. 3,817,397, issued May 21, 1974, there is no provision for separate adjustment of red, green and blue gun screen and grid potentials and only the cathodes of the three guns of such a kinescope are available for separate adjustment of the cut off point of the guns. As will become apparent in the following description, matrix unit 100 and kinescope driver 199 are particularly suited to a kinescope of the precision-in-line type but it should be appreciated that they may be utilized for other types of kinescopes such as delta-gun, shadow mask or other slotted mask types.
In operation, the signal supplied to the base of transistor 107 during the scanning interval by horizontal deflection unit 151 is of sufficiently low amplitude (e.g., less than +4vdc) in relationship to the voltage at its emitter (controlled by the charge on capacitor 120 as will be explained) that it is non-conductive. Because of relatively low voltage applied to the bases of transistors 108 and 170 during the scanning interval, transistors 108, 170, 103 and 104 are also non-conductive and do not affect the operation of matrix circuit 100 during the scanning interval.
The signal -(R-Y), representing red color difference information, and the signal Y, representing luminance information, are coupled to amplifier 161 where they are combined in the emitter circuit of transistor 101 to form a signal -R, representing red information. The signal -R is further amplified and inverted twice by differential amplifier 162 and cascode amplifier 164 for application to kinescope 153.
It is noted that resistors 183, 176 and 177 should be selected so that zener diode 163 is biased well into its reverse breakdown region to inhibit noise.
The portion of the output signal of cascode amplifier 164 developed at the wiper arm of potentiometer 174, is capacitively fed back to one input of differential amplifier 162. This negative feedback arrangement, in conjunction with the use of cascode amplifier 199, provides for a relatively wide bandwidth, thereby eliminating the need for peaking coils or the like to improve high frequency response. The AC gain (or drive) of the matrix unit-kinescope driver arrangement may be adjusted by adjustment of the wiper arm of potentiometer 174 (normally a service or factory adjustment).
During the horizontal retrace interval, a relatively high voltage (e.g., approximately +6 vdc plus the base to emitter voltage of transistor 107 when transistor 107 is rendered conductive) is applied to the base of transistor 107 from horizontal deflection unit 151. Horizontal deflection unit 151 also applies a relatively high voltage to the bases of transistors 108 and 170. As a result transistors 107, 108, 170, 103 and 104 are rendered conductive and the base of transistor 106 is clamped to a voltage substantially equal to the voltage at the base of transistor 107 less the base emitter voltage of transistor 107 (e.g., +6 vdc). The voltage to which the base of transistor 106 is clamped is sufficiently lower than that at the base of transistor 105 so that transistor 106 will be rendered non-conductive and transistor 105 will be rendered fully conductive. Under these conditions, the voltage developed at the collector of transistor 120 will rise toward B+ to a voltage determined by t

he conduction of transistors 119 and 120 and the voltage division action of resistors 165, 166 and the impedance of potentiometer 167 in parallel combination with the series combination of potentiometer 174 and resistor 175.
While the base of transistor 106 is clamped to the voltage applied to the base of transistor 107 less the voltage developed between the base and emitter of transistor 107, the AC feedback provided by capacitor 120 is effectively disconnected and capacitor 120 is provided with a charging path including resistor 166 and a portion of potentiometer 174 by which it is rapidly charged to a voltage determined by the voltage at the emitter of transistor 107 and DC voltage developed at the collector of transistor 120.
The voltage developed at the wiper arm of potentiometer 167 is coupled to the base of transistor 104 and, during each horizontal retrace interval, is compared to the voltage developed at the base of transistor 103 by TCVR 169. A difference in voltage is converted by virtue of the current mirror configuration of transistors 172 and 173 into an error current at the junction of the collectors of transistors 104 and 173. The error current acts, depending on the relative levels at the bases of transistors 103 and 104, to charge or discharge capacitor 110.
Potentiometer 167 initially is adjusted to provide a voltage at the collector of transistor 120 sufficient to cut off the red gun of kinescope 153 when a black image signal is present. Therefore, it is desirable to select the values of resistors 165 and 166 and potentiometer 167 to ensure that the full range of black level control at the red cathode of kinescope 153 is available.
Matrix circuit 100 is arranged so that capacitor 110 will be charged or discharged in a manner to compensate for any change in B+. For example, if B+ decreases, the voltage developed at the base of transistor 104 will decrease relative to the stable reference voltage developed at the base of transistor 103. Therefore, the collector current of transistor 103 and the substantially equal currents flowing through the emitter-collector circuits of transistors 172 and 173 will increase, causing capacitor 110 to be charged. As a result, the voltage at the base of transistor 101 will increase, the voltage at the bas

e of transistor 105 will increase, the voltage at the collector of transistor 105 will decrease and the voltage at the collector of transistor 120 will increase.
It is noted that transistor 173 and transistor 104 operate in what may be termed a push-pull fashion in that the change in current flowing between the emitter and collector of transistor 173 is inversely related to the change in current flowing between the collector and the emitter of transistor 104. Thus, if the current flowing through the emitter-collector of transistor 104 increases, the current through the collector-emitter of transistor 173 decreases, so that capacitor 110 is discharged by the excess of current flowing through transistor 104 rather than being charged by current from transistor 173.
Thus, the feedback arrangement including TCVR 169 of matrix unit 100 adjusts the charge on capacitor 110 to compensate for, and therefore substantially eliminate, the effect on the direct voltage applied to the kinescope cathodes of variations in B+. Furthermore, it is noted that variations in other portions of the matrix amplifier driver arrangement (such as variations caused by temperature or component tolerance changes) affecting the DC conditions at the collector of transistor 120 will be compensated for by the arrangement in a similar manner.
The charge stored on capacitor 110 during the horizontal retrace interval serves to control the bias on cascode amplifier 164 during the succeeding scanning interval. It is noted that the charge on capacitor 110 is not affected by the color difference signals or luminance signals during the horizontal retrace interval, since these signals are arranged to be constant during the horizontal retrace interval.
After the horizontal retrace interval, transistors 103, 104, 170, 172, 173, 107 and 108 are rendered nonconductive (as previously described) and capacitors 110 and 120 begin to discharge. While capacitor 110 controls the bias voltage at the base of transistor 105, capacitor 120 controls the bias voltage at the base of transistor 106. Capacitors 110 and 120 and their associated discharging circuitry preferably are selected so that capacitors 110 and 120 discharge at substantially equal rates. The similar changes in voltage are applied to opposite sides of differential amplifier 162. The common mode rejection characteristics of differential amplifier 162 will prevent the discharging of capacitor 110 to be reflected in the DC conditions at the collector of transistor 120. This "droop" compensation feature provided by capacitor 120 in junction with differential amplifier 162 is desirable, since in its absence, capacitor 110 would have to be a relatively large value to prevent droop. This is especially undesirable if it is desired to construct matrix unit 100 as an integrated circuit because large currents, not compatible with integrated circuit technology, would be required to charge and discharge capacitor 110.
Typical values for the arrangement are shown on the accompanying drawing.
It should be noted that although the present invention has been described in terms of a particular configuration shown in the diagram, modifications may be made which are contemplated to be within the scope of the invention. For instance, cascode driver 199 may be placed with other driver stages well known in the art. Furthermore, the current mirror configuration comprising transistors 172 and 173 may be modified in accordance with other known current mirror configurations.

INDESIT TYPE TC26SI CHASSIS VV708 Circuit arrangement for obtaining a sawtooth current in a coil :
Indesit Industria Elettrodomestici Italiana S.p.A. (IT)

A circuit arrangement for obtaining a periodic sawtooth current in a coil, particularly in a deflection coil of a kinescope, is described. The circuit arrangement comprises a first, unidirectional conductivity device, disposed in parallel to a circuit branch comprising the deflection coil, and a second, controllable switching device, having a control electrode connected to a source of periodic pulses which render conductive the second device during a part of the period of the sawtooth. The main feature of the circuit arrangement is to comprise a resonant series circuit disposed in parallel to the second device; the second device and the resonant series circuit are connected to the deflection coil and to the first device at least through a third, unidirectional conductivity device.

1. Circuit arrangement for obtaining a periodic sawtooth current in a coil (10), particularly in a deflection coil of a kinescope, comprising:
(a) a first diode (13) connected in parallel to a first circuit branch including said coil;
(b) a controllable switching device (16) having a control electrode (17) coupled to a source of periodic pulses which render said switching device conductive in a given conductive direction during a portion of the trace period of said sawtooth current;
(c) a second diode (15) connected in series with said switching device (16) with a conductive direction the same as said given conductive direction to form a second circuit branch connected in parallel to said first diode (13) with a conductive direction opposite to said given conductive direction;
(d) a resonant series circuit (33, 34; 43, 45) connected in parallel to said switching device (16); and
(e) means (11) for supplying electrical energy, said energy supplying means having a first connection to the side of said switching device (16) remote from said second diode (15) and a second connection through a first receive means (12) to one side of said second diode (15).
2. The arrangement of claim 1, wherein in parallel to said second diode (15) is connected a second reactive means (41, 42, 43) which includes a capacitor (41). 3. The arrangement of claim 2, wherein said second reactive means further includes a coil (42) which forms together with said capacitor (41) a resonant circuit. 4. The arrangement of claim 3, wherein said resonant circuit has a resonance frequency substantially matching the repetition frequency of the sawtooth current. 5. The arrangement of claim 1, wherein said switching device (16) is a thyristor. 6. The arrangement of claim 1, wherein in said first circuit branch there is disposed in series to said coil (10) a correcting capacitor (35) for introducing an "S" correction into the sawtooth current during the trace period thereof. 7. The arrangement of claim 1, wherein said first diode (13), said switching device (16) and said second diode (15) are respectively rendered conductive in sequence in the trace period (t₀ ' - t₄ '; t₀ " - t₅ ") of each cycle of said sawtooth current. 8. The arrangement of claim 1, wherein the sawtooth current obtained in said coil (10) has a return period comprising a first part (t₄ ' - t₅ '; t₅ " - t₆ ") and a second part (t₅ ' - t₆ '; t₆ " - t₇ "), and wherein only said second diode (15) is rendered conductive during the first part of said return period and said first diode (13), said switching device (16) and said second diode (15) are rendered non-conductive during the second part of said return period. 9. The arrangement of claim 1, wherein said coil (10) conducts said sawtooth current continuously throughout five successive stages of the trace period (t₀ " - t₅ ") of said sawtooth current, said first diode (13) conducting in the first stage (t₀ " - t₁ "), said first diode (13) and said switching device (16) conducting in the second stage (t₁ " - t₂ "), said switching device (16) conducting in the third stage (t₂ " - t₃ "), said switching device (16) and said second diode (15) conducting in the fourth stage (t₃ " - t₄ "), and said second diode (15) and first diode (13) conducting in the fifth stage (t₄ " - t₅ ").

Description:

BACKGROUND OF THE INVENTION
The present invention relates to a circuit arrangement for obtaining a periodic sawtooth current in a coil, particularly in a coil intended to provide the deflection of an electronic ray in a cathode-ray tube; said circuit arrangement is of the type comprising a first, unidirectional conductivity device and a second, controllable switching device whose control electrode is connected to a source of periodic drive pulses which render conductive the switching device during part of the sawtooth period. In particular, the present invention relates to a circuit in which said controllable switching device comprises a thyristor.
Circuits of this type, which take advantage of the sturdiness and firing easiness of the thyristors, are known long since.
However, it is known that the thyristors have two weak points:
THEY HAVE TO BE EXTINGUISHED BY OUTER MEANS AT HIGH POWER LEVELS;
THEY REQUIRE A CERTAIN RECOVERY TIME BETWEEN THE EXTINCTION OF THE ANODE CURRENT AND THE APPLICATION OF A POSITIVE VOLTAGE TO THE ANODE.
The known circuits are of two types:

CIRCUITS IN WHICH THE EXTINCTION OF THE THYRISTOR IS PRODUCED BY A RESONANT CIRCUIT CONNECTED IN SERIES OR IN PARALLEL TO THE THYRISTOR USED AS UNIDIRECTIONAL SWITCH WHICH "CHARGES" THE COIL, WHICH COIL THEN DISCHARGES THROUGH A DIODE TO RETURN ENERGY TO THE SUPPLY SOURCE (SEE, FOR EXAMPLE, S. A. Schwartz and L. L. Ornik, I.E.E.E. Transactions on BTR, November 1963, pages 9 ÷ 22).
The circuits of this type require a reactive energy circulation which is four times as high as the normal one, and therefore they have generally a rather low efficiency;
CIRCUITS IN WHICH A SECOND THYRISTOR SERVES TO EXTINGUISH THE FIRST ONE, GIVING RISE TO A SUITABLE OSCILLATING CURRENT. (See, for instance, Italian Pat. No. 812,759).
Obviously, circuits of this second type are complex, inasmuch as they require, among other things, a duplication of the drive signals, with a suitable phase displacement of the latter.
Moreover, thyristors in the known circuits are allowed very short recovery times (3 to 5 microseconds) with respect to the sawtooth period, so that particularly fast thyristors are required.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a circuit arrangement for obtaining a sawtooth current in a coil, which will require the use of only one controllable switching device and grant to it relatively long recovery times with respect to the period of the sawtooth, and which, moreover, will be simple and such as not to have the described disadvantages of the known circuits.
Therefore, the object of the present invention is to provide a circuit arrangement for obtaining a periodic sawtooth current in a coil, particularly in a deflection coil of a kinescope, comprising: a first, unidirectional conductivity device, disposed in parallel to a circuit branch comprising said deflection coil; a second, controllable switching device, having a control electrode connected to a source of periodic pulses which render conductive said second device during a part of the period of said sawtooth; a resonant series circuit disposed in parallel to said second device; said second device and said resonant series circuit being connected to said deflection coil and to said first device at least through a third, unidirectional conductivity device.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in detail with reference to the accompanying drawings which are given by way of non limitative example only and in which:
FIG. 1 is a wiring diagram of a circuit arrangement for obtaining a sawtooth current in a coil, according to the principles of the invention;
FIG. 2 shows waveforms of some currents and of a voltage which are present in some points of the circuit of FIG. 1;
FIG. 3 shows a wiring diagram of a second circuit arrangement for obtaining a sawtooth current in a coil, according to the principles of the invention; and
FIG. 4 shows the behaviour of voltages and currents which are present in some points of the circuit of FIG. 3.
DETAILED DESCRIPTION OF THE INVENTION
In FIG. 1 there is shown a circuit according to the invention, for obtaining a sawtooth current in a coil 10.
A battery 11 is connected by its positive pole to an end of a supply decoupling coil (choke) 12. The other end of choke 12 is connected: to one end of coil 10, to the cathode of a diode 13, to one end of a capacitor 14 and to the anode of a diode 15. The cathode of diode 15 is connected to the anode of a thyristor (or SCR) 16, whose cathode is connected to the negative terminal of battery 11. Thyristor 16 is provided with a gate electrode 17 on which a conduction firing pulse from a source of pulses (not shown) is applied. Connected in parallel to thyristor 16 is the series of a coil 33 and a capacitor 34 which form a resonant series circuit. Connected to the other end of coil 10 is one end of a capacitor 35. The other end of capacitors 14, 34 and 35, the anode of the diode 13 and the cathode of the thyristor 16 are connected to the negative pole of battery 11.
The operation of the circuit shown in FIG. 1 will now be explained with reference to FIG. 2 in which there are shown, not to scale, the behaviours of some voltages and currents. FIG. 2 contains five superposed lines. On the first line there is shown the behaviour of the voltage V₁₄ at the ends of the capacitor 14; on the second line there is shown the behaviour of the current I₁₀ in the coil 10; on the third line there is shown the behaviour of the current I₁₃ in the diode 13; on the fourth line there is shown the behaviour of the anodic current I₁₆ of the thyristor 16; on the fifth line there is shown the behaviour of the current I₁₅ in the diode 15.
In the abscissa there are shown the times; seven successive instants are indicated: t₀ ', t₁ ' . . . t₆ '. The time interval from t₀ ' to t₆ ' corresponds to a complete cycle.
The operation of the circuit of FIG. 1 takes place as follows.
At the instant t₁ ' a suitable firing pulse arrives at the gate electrode 17 of the thyristor 16. Since capacitor 34 is charged, an oscillating current I₁₆ (see fourth line of FIG. 2) begins to flow within the circuit formed by thyristor 16, capacitor 34 and coil 33. However, diode 15 is open for the moment; ths sawtooth current I₁₀ which circulates in the coil 10 closes, in fact, through diode 13 (third line of FIG. 2). At the instant t₂ ' the current I₁₃ in diode 13 reaches the value zero, diode 13 is cut-off, whilst diode 15 becomes conductive; the current I₁₀ of the coil 10 circulates now in the diode 15 (fifth line of FIG. 2).
This behaviour continues up to the instant t₃ ', i.e. till the conduction within thyristor 16 extinguishes because the oscillating current I₁₆ passes through zero. At the instant t₃ ' the diode 13 becomes conductive again, thereby allowing the oscillating current in the branch formed by coil 33 and capacitor 34 to circulate in the reverse direction, and consequently capacitor 34 to recharge itself.
Finally, at the instant t₄ ' the diode 13 cuts off again thereby releasing the return oscillation which initially (interval t₄ ' - t₅ ') takes place according to the laws of the two-pole circuit formed by coils 10 and 33 and capacitors 14 and 34 (neglegting the capacitor 35 which has a much higher capacity and may, in first approximation, be considered a short circuit for the alternate currents).
The voltage V₁₄ at the ends of the capacitor 14 rises rapidly towards a maximum to return then to zero (see first line of FIG. 2). At a certain point (instant t₅ ') diode 15 is cut-off, thereby insulating the resonant circuit which comprises coil 33 and capacitor 34, and thus leaving charged capacitor 34 whilst capacitor 14 is discharged onto coil 10.
At the moment in which the voltage V₁₄ at the ends of capacitor 14 is reversed (instant t₆ '), diode 13 becomes conductive thereby terminating the return section and initiating the forward course of the scansion (instant t₀ ').
The circuit described is simple; it requires only one thyristor (16) and two diodes (13 and 15) for realizing an electronic bipolar switch which will allow to obtain the desired sawtooth current in a coil (coil 10).
Owing to the particular circuit arrangement the self-extinction of the thyristor 16 and the external synchronization of the repetition frequency are ensured. The time available for the recovery of the thyristor 16 (interval t₃ ' - t₄ ') is considerable (15 ➝ 20 microseconds).
Moreover, capacitor 35 avoids the presence of an undesirable component of direct current in coil 10 and originates the so-called "S" correction of the current I₁₀ in coil 10 to arrange that the current in coil 10 does not present a substantially linear behaviour (such correction is necessary if coil 10 is utilized to deflect an electronic ray of a kinescope having a substantially flat screen) in order to correct the so-called tangent error due to the fact that the centre of curvature of the screen and the deflection centre do not coincide.
The following Table shows the values of an embodiment of the circuit of FIG. 1 which has been experimented in practice:
Table of the values
coil 12: 5,2 mH
capacitor 14: 27 nF
deflection coil 10: 300 μH
coil 33: 430 μH
capacitor 34: 150 nF
capacitor 35: 1,8 μF.
FIG. 3 shows a different embodiment of the circuit according to the invention. In comparison with the circuit shown in FIG. 1, the cathode of diode 13 is connected to the anode of thyristor 16 also through the series of a capacitor 41 and two coils 42 and 43. The connection between coils 42 and 43 is connected to one end of a capacitor 45 whose other end is connected to the negative terminal of battery 11. Coil 12, one end of which is connected to the positive pole of the battery 11, has its other end connected to the cathode of the diode 15 and accordingly to the anode of the thyristor 16. Connected in parallel to thyristor 16 is the series of a resistor 46 with a capacitor 47.
To explain the operation of the circuit shown in FIG. 3 reference will be made to the waveforms represented to FIG. 4 which are not to scale.
FIG. 4 has five lines.
The first line shows the behaviour of the voltage V₁₄ at the ends of capacitor 14; the second line shows the behaviour of the voltage V₁₆ at the ends of the thyristor 16; the third line shows the behaviour of anodic current I₁₆ of thyristor 16; the fourth line shows the behaviour of the current I₁₅ in the diode 15; the fifth line shows the behaviour of the current I₁₃ in the diode 13.
In the abscissa in FIG. 4 there are shown the times. Eight successive instants are indicated therein, namely: t₀ ", t₁ " . . . t₇ ". The time interval from t₀ " to t₇ " corresponds to a complete cycle.
The circuit shown in FIG. 3 operates as follows.
At the instant t₀ " the diode 13 is conductive whilst diode 15 and thyristor 16 are not conductive.
In the circuit formed by the elements 10, 35 and 13 there circulates a sawtooth current which decreases in an approximately linear fashion. At the same time, an oscillating current circulates in the circuit formed by the elements 41, 42 and 45. Also this current passes into the diode 13 and superimposes to the sawtooth current from deflection coil 10. The behaviour of the current I₁₃ in the diode 13 can be seen on the fifth line of FIG. 4 between the instants t₀ " and t₂ ".
The behaviour of the voltage at the ends of capacitor 45 can be observed on the second line of FIG. 4 between instants t₀ " and t₁ "; in reality, on said line there is shown the voltage 16 on thyristor 16 which is a fraction, near to the unit, of the voltage on capacitor 45, owing to the division effected between coils 12 and 43.
At the instant t₁ " a firing pulse is applied to the electrode 17 of the thyristor 16.
Thyristor 16 is fired, the voltage V₁₆ on the anode drops suddenly almost to zero (FIG. 4, second line) and the current I₁₆ of the thyristor 16 initiates increasing (FIG. 4, third line); the current I₁₆ in the thyristor 16 is substantially the oscillating current which is produced in the resonant series circuit formed by elements 43 and 45. Said current I₁₆ has a substantially sinusoidal behaviour, reaches a maximum value and returns to zero at the instant t₄ ". In the meantime (instant t₂ "), current I₁₃ in the diode 13 has dropped to zero, so that the conduction in the diode 13 is interrupted; however, almost immediately after (instant t₃ "), diode 15 becomes conductive (FIG. 4, fourth line), so that the current of the coil 10 may continue flowing within elements 16 and 15.
At the instant t₄ " the oscillating current of the resonant series circuit formed by coil 43 and capacitor 45 inverts, so that the conduction in the thyristor 16 is interrupted, whilst diode 13 becomes conductive again and the current of said circuit formed by coil 43 and capacitor 45 flows within elements 35 and 13 (FIG. 4, fourth and fifth lines, instant from t₄ " to t₅ ").
At the instant t₅ " the current of the resonant series circuit formed by coil 43 and capacitor 45 inverts again, so that diode 13 cuts off. Since also thyristor 16 is cut off, for the first time from instant t₀ " there is no direct path for the current in the deflection coil 10.
Since diode 15 is still conductive and since we may in first approximation neglegt the branches represented by coil 12 and series circuit formed by coil 42 and capacitor 41, which has a high impedance with respect to the other circuits, the oscillating circuit, between the instants t₅ " and t₆ ", i.e. as long as diode 15 is conductive, results in being formed essentially by elements 10 and 14, which form a resonant parallel circuit, and by elements 43 and 45 which form a resonant series circuit.
This four element circuit has two poles; the voltage V₁₄ at the ends of the capacitor 14 rises rapidly towards a maximum (FIG. 4, first line) to drop then again; said voltage results essentially from the sum of two sinusoids having different frequency; said frequencies are just those of the poles of the circuit.
At the instant t₆ " the current I₁₅ in the diode 15 reaches the zero value; diode 15 cuts off and therefore the circuit again changes configuration. Whilst the voltage V₁₄ at the ends of the capacitor 14 shifts rapidly towards zero, the voltage on thyristor 16 rises again (because of the voltage which is present on capacitor 45), as can be seen in FIG. 4, second line, instant t₆ ".
This short stage from t₆ " to t₇ " is important because during said stage the deflection circuit (elements 10 and 14) receives from the remaining part of the circuit (elements 41, 42 and 45) the energy which is necessary to make up for the losses.
It is the coupling formed by the elements 41 and 42 which allows to let flow the current within diode 15 during the first stage of the return section (t₅ " - t₆ ") and to give energy to the deflection circuit (10, 14) during the second part of the return section.
It has been found that it is suitable for said coupling branch (comprising the elements 41 and 42) to be tuned approximately at the repetition frequency of the sawtooth current which it is desired to generate.
At the instant t₇ " when the voltage V₁₄ at the ends of the capacitor 14 inverts, diode 13 becomes conductive again; thus we have again the initial situation (instant t₀ ").
Resistor 46 and capacitor 47 form a network for the attenuation of the parassitic oscillations which would occur at the ends of thyristor 16 upon cutting-off of the diode 15 (instant t₆ ").
The following Table shows by way of information the values of the components of an embodiment of the circuit of FIG. 3 which has been experimented in practice.
Table of the values
coil 12: 1,8 mH
resistor 46: 560 ohm
coil 43: 0,2 mH
capacitor 47: 3,3 nF
coil 42: 1,8 mH
capacitor 45: 68 nF
capacitor 41: 39 nF
capacitor 14: 39 nF
deflection coil 10: 0,3 mH
capacitor 35: 1,8 μF
The circuit of FIG. 3, in addition to the advantages described for the circuit of FIG. 1 has the advantage that the maximum voltage on thyristor 16 is equal to the maximum voltage on deflection coil 10, and that the ratio between said maximum voltages and the supplying voltage of battery 11 may be varied within a wide range by acting for example on the value of the coil 42 and/or on the value of the capacitor 41.
With the values shown in the above Table said ratio is about three.
Since there are commonly available thyristors suitable for maximum voltages of 700 Volts and deflection coils arranged to operate with voltages of the same order, the circuit shown in FIG. 3 is fit for operating with a supply voltage of 220 Volts which is easily obtainable from the domestic distribution network.
From the foregoing description, the advantages of the circuit arrangement according to the present invention are clearly apparent. Also clearly apparent is that variations of the circuits described hereinabove by way of example only will be possible to those skilled in the art without departing from the principles of novelty of the inventive idea.

INDESIT TYPE TC26SI CHASSIS VV708 INTEGRAL THYRISTOR-RECTIFIER DEVICEA semiconductor switching device comprising a silicon controlled rectifier (SCR) and a diode rectifier integrally connected in parallel with the SCR in a single semiconductor body. The device is of the NPNP or PNPN type, having gate, cathode, and anode electrodes. A portion of each intermediate N and P region makes ohmic contact to the respective anode or cathode electrode of the SCR. In addition, each intermediate region includes a highly conductive edge portion. These portions are spaced from the adjacent external regions by relatively low conductive portions, and limit the conduction of the diode rectifier to the periphery of the device. A profile of gold recombination centers further electrically isolates the central SCR portion from the peripheral diode portion.

That class of thyristors known as controlled rectifiers are semiconductor switches having four semiconducting regions of alternate conductivity and which employ anode, cathode, and gate electrodes. These devices are usually fabricated from silicon. In its normal state, the silicon controlled rectifier (SCR) is non-conductive until an appropriate voltage or current pulse is applied to the gate electrode, at which point current flows from the anode to the cathode and delivers power to a load circuit. If the SCR is reverse biased, it is non-conductive, and cannot be turned on by a gating signal. Once conduction starts, the gate loses control and current flows from the anode to the cathode until it drops below a certain value (called the holding current), at which point the SCR turns off and the gate electrode regains control. The SCR is thus a solid state device capable of performing the circuit function of a thyratron tube in many electronic applications. In some of these applications, such as in automobile ignition systems and horizontal deflection circuits in television receivers, it is necessary to connect a separate rectifier diode in parallel with the SCR. See, for example, W. Dietz, U. S. Pat. Nos. 3,452,244 and 3,449,623. In these applications, the anode of the rectifier diode is connected to the cathode of the SCR, and the cathode of the rectifier is connected to the SCR anode. Thus, the rectifier diode will be forward biased and current will flow through it when the SCR is reverse biased; i.e., when the SCR cathode is positive with respect to its anode. For reasons of economy and ease of handling, it would be preferable if the circuit function of the SCR and the associated diode rectifier could be combined in a single device, so that instead of requiring two devices and five electrical connections, one device and three electrical connections are all that would be necessary. In fact, because of the semiconductor profile employed, many SCR's of the shorted emitter variety inherently function as a diode rectifier when reverse biased. However, the diode rectifier function of such devices is not isolated from the controlled rectifier portion, thus preventing a rapid transition from one function to the other. Therefore, it would be desirable to physically and electrically isolate the diode rectifier portion from that portion of the device which functions as an SCR.




INDESIT TYPE TC26SI CHASSIS VV708 LINE / HORIZONTAL DEFLECTION WITH THYRISTOR SWITCH TECHNOLOGY OVERVIEW.


Horizontal deflection circuit

(Thyristor Horizontalsteuerung)

Description:



1. A horizontal deflection circuit for generating the deflection current in the deflection coil of a television picture tube wher

ein a first switch controls the horizontal sweep, and wherein a second switch in a so-called commutation circuit with a commutating inductor and a commutating capacitor opens the first switch and, in addition, controls the energy transfer from a dc voltage source to an input inductor, characterized in that the input inductor (Le) and the commutating inductor (Lk) are combined in a unit designed as a transformer (U) which is proportioned so that the open-circuit inductance of the transformer is essentially equal to the value of the input inductor (Le), while the short-circuit inductance of the transformer (U) is essentially equal to the value of the commutating inductor (Lk), and that the second switch (S2) is connected in series with the dc voltage source (UB) and a first winding (U1) of the transformer (U). 2. A horizontal deflection circuit according to claim 1, characterized in that the transformer (U) operates as an isolation transformer between the supply (UB) and the subcircuits connected to a second winding. 3. A horizontal deflection circuit according to claim 1, characterized in that the second switch (S2) is connected between ground and that terminal of the first winding (U1) of the transformer (U) not connected to the supply potential (+UB). 4. A horizontal deflection circuit according to claim 1, characterized in that a capacitor (CE) is connected across the series combination of the first winding (U1) of the transformer and the second switch (S2). 5. A horizontal deflection circuit according to claim 1, characterized in that the second winding (U2) of the transformer (U) is connected in series with a first switch (S1), the commutating capacitor (Ck), and a third, bipolar switch (S3) controllable as a function of the value of a controlled variable developed in the deflection circuit. 6. A horizontal deflection circuit according to claim 5, characterized in that the third switch (S3) is connected between ground and the second winding (U2) of the transformer. 7. A horizontal deflection circuit according to claim 2, characterized in that the isolation transformer carries a third winding via which power is supplied to the audio output stage of the television set. 8. A horizontal deflection circuit according to claims 2, characterized in that the voltage serving to control the first switch (S1) is derived from a third winding of the transformer.

Description:

The present invention relates to a horizontal deflection circuit for generating the deflection current in the deflection coil of a television picture tube wherein a first switch controls the horizontal sweep, and wherein a second switch in a so-called commutation circuit with a commutating inductor and a commutating capacitor opens the first switch and, in addition, controls the energy transfer from a dc voltage source to an input inductor.
German Aus

legeschrift (DT-AS) No. 1,537,308 discloses a horizontal deflection circuit in which, for generating a periodic sawtooth current within the respective deflection coil of the picture tube, in a first branch circuit, the deflection coil is connected to a sufficiently large capacitor serving as a current source via a first controlled, bilaterally conductive switch which is formed by a controlled rectifier and a diode connected in inverse parallel. The control electrode of the rectifier is connected to a drive pulse source which renders the switch conductive during part of the sawtooth trace period. In that arrangement, the sawtooth retrace, i.e. the current reversal, also referred to as "commutation", is initiated by a second controlled switch.
The first controlled switch also forms part of a second branch circuit where it is connected in series with a second current source and a reactance capable of oscillating. When the first switch is closed, the reactance, consisting essentially of a coil and a capacitor, receives energy from the second current source during a fixed time interval. This energy which is taken from the second current source corresponds to the circuit losses caused during the previous deflection cycle.
As can be seen, such a circuit needs two different, separate inductive elements, it being known that inductive elements are expensive to manufacture and always have a certain volume determined by the electrical properties required.
The object of the invention is to reduce the amount of inductive elements required.
The invention is characterized in that the input inductor and the commutating inductor are combined in a unit designed as a transformer which is proportioned so that the open-circuit inductance of the transformer is essentially equal to the value of the input inductor, while the short-circuit inductance of the transformer is essentially equal to the value of the commutating inductor, and that the second switch is connected in series with the dc voltage source and a first winding of the transformer.
This solution has an added advantage in that, in mass production, both the open-circuit and the short-circuit inductance are reproducible with reliability.
According to another feature of the invention, the electrical isolation between the windings of the transformer is such that the transformer operates as an isolation transformer between the supply and the subcircuits connected to a second winding or to additional windings of the transformer. In this manner, the transformer additionally provides reliable mains isolation.
According to a further feature of the invention, the second switch is connected between ground and that terminal of the first winding of the transformer not connected to the supply potential. This simplifies the control of the switch.
According to a further feature of the invention, to regulate the energy supply, the second winding of the transf

ormer is connected in series with the first switch, the commutating capacitor, and a third, bipolar switch controllable as a function of the value of a controlled variable developed in the deflection circuit.

The advantage gained by this measure lies in the fact that the control takes place on the side separated from the mains, so no separate isolation device is required for the gating of the third switch. Further details and advantages will be apparent from the following description of the accompanying drawings and from the claims. In the drawings,
FIG. 1 is a basic circuit diagram of the arrangement disclosed in German Auslegeschrift (DT-AS) No. 1,537,308;
FIG. 2 shows a first embodiment of the horizontal deflection circuit according to the invention, and
FIG. 3 shows a development of the horizontal deflection circuit according to the invention.
FIG. 1 shows the essential circuit elements of the horizontal deflection circuit known from the German Auslegeschrift (DT-AS) No. 1,537,308 referred to by way of introduction.
Connected in series with a dc voltage source UB is an input inductor Le and a bipolar, controlled switch S2. In the following, this switch will be referred to as the "second switch"; it is usually called the "commutating switch" to indicate its function.
In known circuits, the second switch S2 consists of a controlled rectifier and a diode connected in inverse parallel.
The second switch S

2 also forms part of a second circuit which contains, in addition, a commutating inductor Lk, a commutating capacitor Ck, and a first switch S1. The first switch S1, controlling the horizontal sweep, is constructed in the same manner as the above-described second switch S2, consisting of a controlled rectifier and a diode in inverse parallel. Connected in parallel with this first switch is a deflection-coil arrangement AS with a capacitor CA as well as a high voltage generating arrangement (not shown). In FIGS. 1, 2, and 3, this arrangement is only indicated by an arrow and by the reference characters Hsp. The operation of this known horizontal deflection circuit need not be explained here in detail since it is described not only in the German Auslegeschrift referred to by way of introduction, but also in many other publications.
FIGS. 2 and 3 show the horizontal deflection circuit modified in accordance with the present invention. Like circuit elements are designated by the same reference characters as in FIG. 1.
FIG. 2 shows the basic principle of the invention. The two inductors Le and Lk of FIG. 1 have been replaced by a transformer U. To be able to serve as a substitute for the two inductors Le and Lk, the transformer must be proportioned in a special manner. Regardless of the turns ratio, the open-circuit inductance of the transformer is chosen to be essentially equal to the value of the input inductor Le, and the short-circuit inductance of the transformer is essentially equal to the value of the commutating inductor Lk.
To permit the second switch S2 to be utilized for the connection of the dc voltage source UB, it is included in the circuit of that winding U1 of the transformer connected to the dc voltage UB.
In principle, it is of no consequence for the operation of the switch S2 whether it is inserted on that side of the winding U1 connected to the positive operating potential +UB or on the side connected to ground. In practice, however, the solution shown in FIGS. 2 and 3 will be chosen since the gating of the controlled rectifier is less problematic in this case.
In compliance with pertinent safety regulations, the transformer U may be designed as an isolation transformer and can thus provide mains separation, which is necessary for various reasons. It is known from German Offenlegungschrift (DT-OS) No. 2,233,249 to provide dc isolation by designing the commutating inductor as a transformer, but this measure is not suited to attaining the object of the present invention.
If the energy to be taken from the dc voltage source is to be controlled as a function of the energy needed in the horizontal deflection circuit and in following subcircuits, the embodiment of the horizontal deflection circuit of FIG. 3 may be used.
The circuit including the winding U2 of the transformer U contains a third controlled switch S3, which, too, is inserted on the grounded side of the winding U2 for the reasons mentioned above. This third switch S3, just as the second switch S2, is operated at the frequency of a horizontal oscillator HO, but a control circuit RS whose input l is fed with a controlled variable is inserted between the oscillator and the switch S3. Depending on this controlled variable, the controlled rectifier of the third switch S3 can be caused to turn on earlier. A suitable controlled variable containing information on the energy consumption is, for example, the flyback pulse capable of being taken from the high voltage generating circuit (not shown). Details of the operation of this kind of energy control are described in applicant's German Offenlegungsschrift (DT-OS) No. b 2,253,386 and do not form part of the present invention.
With mains isolation, the additional, third switch S3 shown here has the advantage of being on the side isolated from the mains and eliminates the need for an isolation device in the control lead of the controlled rectifier.
As an isolation transformer, the transformer U may also carry additional windings U3 and U4 if power is to be supplied to the audio output stage, for example; in addition, the first switch S1 may be gated via such an additional winding.
The points marked at the windings U1 and U2 indicate the phase relationship between the respective voltages. Connected in parallel with the winding U1 and the second switch S2 is a capacitor CE which completes the circuit for the horizontal-frequency alternating current; this serves in particular to bypass the dc voltage source or the electrolytic capacitors contained therein.
If required, a well-known tuning coil may be inserted, e.g. in series with the second winding U2, without changing the basic operation of the horizontal deflection circuit according to the invention.

INDESIT TYPE TC26SI CHASSIS VV708 Electron beam deflection circuit including thyristors Further Discussion and deepening of knowledge, Thyristor horizontal output circuits: (ZEILEN ABLENKUNG MIT THYRISTOR SCHALTUNG)

1. An electron beam deflection circuit for a cathode ray tube with electromagnetic deflection by means of a sawtooth current waveform having a trace portion and a retrace portion, said circuit comprising: a deflection winding; a first source of electrical energy formed by a first capacitor; first controllable switching means comprising a parallel combination of a first thyristor and a first diode connected together to conduct in opposite directions, for connecting said winding to said first source during said trace portion, while said first switching means is turned on; a second source of electrical energy including a first inductive energy storage means coupled to a voltage supply; reactive circuit means including a combination of inductive and capacitive reactances for storing the energy supplied by said second source; second controllable switching means, substantially similar to said first one, for completing a circuit including said reactive circuit means and said first switching means, when turned on before the end of said trace portion, so as to pass through said first switching means an oscillatory current in opposite direction to that which passes through said first thyristor from said first source and to turn said first thyristor off after these two currents cancel out, the oscillatory current flowing thereafter through said first diode for an interval termed the circuit turn-off time, which has to be greater than the turn-off time of said first thyristor; wherein the improvement comprises: means for drawing, during at least a part of said trace portion, a substantial amount of additional current through said first switching means, in the direction of conduction of said first diode, whereby to perceptibly shift the waveform of the current flowing through said first switching means towards the negative values by an amount equal to that of said substantial additional current and to lengthen, in proportion thereto, said circuit turn-off time, without altering the values of the reactances in the reactive circuit which intervene in the determination of both the circuit turn-off and retrace portion time intervals.

2. A deflection circuit as claimed in claim 1, wherein said amount of additional current is greater than or equal to 5 per cent of the peak-to-peak value of the current flowing through the deflection winding.

3. A deflection circuit as claimed in claim 1, wherein said means for drawing a substantial amount of additional current through said first switching means comprises a resistor connected in parallel to said first capacitor.

4. A deflection circuit as claimed in claim 1, wherein said means for drawing an additional current is formed by connecting said first and second energy sources in series so that the current charging said reactive circuit means forms the said additional current.

5. A deflection circuit as claimed in claim 1, further including a series combination of an autotransformer winding and a second high-value capacitor, said combination being connected in parallel to said first switching means, wherein said autotransformer comprises an intermediate tap located between its terminals respectively connected to said first switching means and to said second capacitor, said tap delivering, during said trace portion, a suitable DC supply voltage lower than the voltage across said second capacitor; and wherein said means for drawing a substantial amount of additional current comprises a load to be fed by said supply voltage and having one terminal connected to ground; and further controllable switching means controlled to conduct during at least part of said trace portion and to remain cut off during said retrace portion, said further switching means being connected between said tap and the other terminal of said load.

Description:

The present invention relates to electron beam deflection circuits including thyristors, such as silicon controlled rectifiers and relates, in particular, to horizontal deflection circuits for television receivers.










The present invention constitutes an improvement in the circuit described in U.S. Pat. No. 3,449,623 filed on Sept. 6, 1966, this circuit being described in greater detail below with reference to FIGS. 1 and 2 of the accompanying drawings. A deflection circuit of this type comprises a first thyristor switch which allows the conenction of the horizontal deflection winding to a constant voltage source during the time interval used for the transmisstion of the picture signal and for applying this signal to the grid of the cathode ray tube (this interval will be termed the "trace portion" of the scan), and a second thyristor switch which provides the forced commutation of the first one by applying to it a reverse current of equal amplitude to that which passes through it from the said voltage source and thus to initiate the retrace during the horizontal blanking interval.

A undirectional reverse blocking triode type thyristor or silicon controlled rectifier (SCR), such as that used in the aformentioned circuit, requires a certain turn-off time between the instant at which the anode current ceases and the instant at which a positive bias may be applied to it without turning it on, due to the fact that there is still a high concentration of free carriers in the vicinity of the middle junction, this concentration being reduced by a process of recombination independently from the reverse polarity applied to the thyristor. This turn-off time of the thyristor is a function of a number of parameters such as the junction temperature, the DC current level, the decay time of the direct current, the peak level of the reverse current applied, the amplitude of the reverse anode to cathode voltage, the external impedance of the gate electrode, and so on, certain of these varying considerably from one thyristor to another.

In horizontal deflection circuits for television receivers, the flyback or retrace time is limited to approximately 20 percent of the horizontal scan period, the retrace time being in the case of the CCIR standard of 625 lines, approximately 12 microseconds and, in the case of the French standard of 819 lines, approximately 9 microseconds. During this relatively short interval, the thyristor has to be rendered non-conducting and the electron beam has to be returned to the origin of the scan. The first thyristor is blocked by means of a series resonant LC circuit which is subject to a certain number of restrictions (limitations as to the component values employed) due to the fact that, inter alia, it simultaneously determines the turn-off time of the circuit which blocks the thyristor and it forms part of the series resonant circuit which is to carry out the retrace. To obtain proper operation of the deflection circuit of the aforementioned Patent, especially when used for the French standard of 819 lines per image, the values of the components used have to subject to very close tolerances (approximately 2%), which results in high costs.

The improved deflection circuit, object o

f the present invention, allows the lengthening of the turn-off time of the circuit for turning the scan thyristor off, without altering the values of the LC circuit, which are determined by other criteria, and without impairing the operation of the circuit.

According to the invention, there is provided an electron beam deflection circuit for a cathode ray tube with electromagentic deflection by means of a sawtooth current waveform having a trace portion and a retrace portion, said circuit comprising: a deflection winding; a first source of electrical energy formed by a first capacitor; first controllable switching means comprising a parallel combination of a first thyristor and a first diode, connected together to conduct in opposite directions, for connecting said winding to said first source during said trace portion when said first switching means is turned on; a second source of electrical energy including a first inductive energy storage means coupled to a voltage supply; reactive circuit means including a combination of inductive and capacitive reactances for storing the energy supplied by the said second source; a second controllable switching means, substantially identical with the first one, for completing a circuit including said reactive circuit means and said first switching means, when turned on, so as to pass through said first thyristor an oscillatory current in the opposite direction to that which passes through it from said first source and to turn it off after these two currents cancel out, the oscillatory current then flowing through said first diode for an interval termed the circuit turn-off time which has to be greater than the turn-off time of said first thyristor; and means for drawing duing at least a part of said trace portion a substantial amount of additional current from said first switching means in the direction of conduction of said first diode, whereby said circuit turn-off time is lengthened in proportion to the amount of said additional current, without altering the values of the reactances in the reactive circuit by shifting the waveform of the current flowing through said first switching means towards the negative by an amount equal to that of said additional current.

A further object of the invention consists in using the supplementary current in the recovery diode of the first switching means to produce a DC voltage which may be used as a power supply for the vertical deflection circuit of the television receiver, for example.

The invention will be better understood and other features and advantages thereof will become apparent from the following description and the accompanying drawings, given by way of example, and in which:

FIG. 1 is a schematic circuit diagram partially in bloc diagram form of a prior art deflection circuit according to the aforementioned Patent;

FIG. 2 shows waveforms of currents and voltages generated at various points in the circuit of FIG. 1;

FIG. 3 is a schematic diagram of a deflection circuit according to the invention which allows the principle of the improvement to be explained;

FIG. 4 is a diagram of the waveforms of the current through the first switching means 4, 5 of the circuit of FIG. 3;

FIG. 5 is a circuit diagram of another embodiment of the circuit according to the invention;

FIG. 6 is a schematic representation of the preferred embodiment of the circuit according to the invention; and

FIG. 7 shows voltage waveforms at various points of the high voltage autotransformer 21 of FIG. 6.

In all these Figures the same reference numerals refer to the same components.

FIG. 1 shows the horizontal deflection circuit described and claimed in the U.S. Pat. No. 3,449,623 mentioned above, which comprises a first source of electrical energy in the shape of a first capacitor 2 having a high capacitance C ₂ for supplying a substantially constant voltage Uc ₂ across its terminals. A first terminal of the first capacitor 2 is connected to ground, whilst its second terminal which supplies a positive voltage is connected to one of the terminals of a horizontal deflection winding shown as a first inductance 1. A first switching means 3, consisting of a first reverse blocking triode thyristor 4 (SCR) and a first recovery diode 5 in parallel, the two being interconnected to conduct current in opposite directions, is connected in parallel with the series combination formed by the deflection winding 1 and the first capacitor 2. The assembly of components 1, 2, 4 and 5 forms the final stage of the horizontal deflection circuit in a television receiver using electromagnetic delfection.

The deflection circuit also includes a drive stage for this final stage which here controls the turning off of the first thyristor 4 to produce the retrace or fly-back portion of the scan during the line-blanking intervals i.e. while the picture signal is not transmitted. This driver stage comprises a second voltage source in the shape of a DC power supply 6 which delivers a constant high voltage E. The negative terminal of the power supply 6 is connected to ground and its positive terminal to one of the terminals of a second inductance 7 of relatively high value, which draws a substantially lineraly varying current from the power supply 6 to avoid its overloading. The other terminal of th

e second inductance 7 is connected, on the one hand, to the junction of the deflection winding 1 and the first switching means 3 by means of a second inductance 8 and a second capacitor 9 in series and, on the other hand, to one of the terminals of a second controllable bi-directionally conducting switching means 10, similar to the first one 3, including a parallel combination of a second thyristor 11 and a second recovery diode 12 also arranged to conduct in opposite directions.

The respective values of the third inductance 8 (L ₈ ) and of the second capacitor 9 (C ₉ ) are principally selected so that, on the one hand, one half-cycle of oscillation of the first series resonant circuit L ₈ - C ₉ , (i.e. π √ L ₈ ^. C ₉ ) is longer than the turn-off time of the first thyristor 4, but still is as short as possible since this time interval determines the speed of the commutation of the thyristor 4, and, on the other hand, one half-cycle of oscillation of another series resonant circuit formed by L ₁ , L ₈ and C ₉ , i.e. π √ (L ₁ + L ₈ ) ^. C ₉ , is substantially equal to the required retrace time interval (i.e. shorter than the horizontal blanking interval).

The gate (control electrode) of the second thyristor 11 is coupled to the output of the horizontal oscillator 13 of the television receiver by means of a first pulse transformer 14 and a first pulse shaping circuit 15 so that it is fed short triggering pulses which are to turn it on.

The gate of the first thyristor 4 fed with signals of a substantially rectangular waveform which are negative during the horizontal blanking intervals, is coupled to a winding 16 by means of a second pulse shaping circuit 17, the winding 16 being magnetically coupled to the second inductance 7 to make up the secondary winding of a transformer of which the inductance 7 forms the primary winding. It will be noted here that it is also possible to couple the secondary winding 16 magnetically to a primary winding connected to a suitable output (not shown) of the horizontal oscillator 13.

The operation of a circuit of this type will be explained below with reference to FIG. 2 which shows the waveforms at various points in the circuit of FIG. 1 during approximately one line period.

FIG. 2 is not to scale since one line period (t ₇ - t ₀ ) is equal to 64 microseconds in the case of 625 lines and 49 microseconds in the case of 819 lines, while the durations of the respective horizontal blanking intervals are approximately 12 and 9.5 microseconds.

Waveform A shows the form of the current i _L1 passing through deflection winding 1, this current having a sawtooth waveform substantially linear from t ₀ to t ₃ and from t ₅ to t ₇ , and crossing zero at time instants t ₀ and t ₇ , and reaching values of + I _1m and - I _1m , at time instants t ₃ and t ₅ respectively, these being its maximum positive and negative amplitudes.

During the second half of the trace portion of the horizontal deflection cycle, that is to say from t ₀ to t ₃ , the thyristor 4 of the first switching means 3 is conductive and makes the high value capacitor 2 discharge through the deflector winding 1, which has a high inductance, so that current i _L1 increases linearly.

A few microseconds (5 to 8 μ s) before the end of the trace portion, i.e. at time instant t ₁ , the trigger of the second thyristor 11 receives a short voltage pulse V _G11 which causes it to turn on as its anode is at this instant at a positive potential with respect to ground, which is due to the charging of the second capacitor 9 through inductances 7 and 8 by the voltage E from the power supply 6.

When thyristor 11 is made conductive at time t ₁ , on the one hand, inductance 7 is connected between ground and the voltage source 6 and a linearly increasing current flows through it and, on the other hand, the reactive circuit 8, 9 forms a loop through the second and first switching means 10 and 3, thus forming a resonant circuit which draws an oscillatory current i ₈ ,9 of frequency ##EQU1##

This oscillatory current i ₈ ,9 will pass through the first switching means 3, i.e. thyristor 4 and diode 5, in the opposite direction to that of current i _L1 . Since the frequency f ₁ is high, current i ₈ ,9 will increase more rapidly than i _L1 and will reach the same level at time t ₂ , that is to say i ₈ ,9 (t ₂ ) = -i _L1 (t ₂ ) and these currents will cancel out in the thyristor 4 in accordance with the well known principle of forced commutation. After time instant t ₂ , current i ₈ ,9 continues to increase more rapidly than i _L1 , but the difference between them (i ₈ ,9 - i _L1 ) passes the diode 5 (see wave form B) until it becomes zero at time instant t ₃ which is the turn off time instant of the first switching means 3, at which the retrace begins.

The interval between the time instant t ₂ and t ₃ , i.e. (t ₃ -t ₂ ), during which diode 5 is conductive and the thyristor is reverse biased will be termed in what follows the circuit turn-off time and it should

be greater than the turn-off time of the thyristor 4 itself since the latter will subsequently become foward biased (i.e. from t ₃ to t ₅ ) by the retrace or flyback pulse (see waveform E) which should not trigger it.

At time instant t ₃ , the switching means 3 is opened (i ₄ and i ₅ are both zero -- see waveforms B and C) and the reactive circuit 8, 9 forms a loop through capacitor 2 and the deflection coil 1 and thus a series resonant circuit including (L ₁ + L ₈ ) and C ₉ , C ₂ being of high value and representing a short circuit for the flyback frequency ##EQU2## thus obtained.

The retrace which stated at time t ₃ takes place during one half-cycle of the resonant circuit formed by reactances L ₁ , L ₈ and C ₉ , i.e. during the interval between t ₃ and t ₅ . In the middle of this interval i.e. at time instant t ₄ , both i _L1 (waveform A) and i ₈ ,9 (waveform D) pass through zero and change their sign, whereas the voltage at the terminals of the first switching means 3 (V ₃ , waveform E) passes through a maximum. Thus, from t ₄ onwards, thyristor 11 will be reverse biased and diode 12 will conduct the current from the resonant circuit 1, 8 and 9 in order to turn the second thyristor 11 off.

At time instant t ₅ , when current i _L1 has reached - I _1m and when voltage v ₃ falls to zero, diode 5 of the first switching means 3 becomes conductive and the trace portion of scan begins.

Current i ₈ ,9 nevertheless continues to flow in the resonant circuit 8, 9 through diodes 5 and 12, which causes a break to appear in waveform D at t ₅ , and a negative peak to appear in waveform D and a positive one in waveform B in the interval between t ₅ and t ₆ , these being principally due to the distributed capacities of coil 1 or to an eventual capacitor (not shown) connected in parallel to the first switching means 3.

At time instant t ₆ , diode 12 of the second switching means 10 ceases to conduct after having allowed thyristor 11 time to become turned off completely.

The level of current i ₈ ,9 at time instant t ₅ (i.e. I _c ) as well as the negative peak I _D12 in i ₈ ,9 and the positive peak I _D5 in i ₅ depend on the values of L ₈ and C ₉ in the same way as does the turn-off time of the circuit (t ₃ - t ₂ ). If, for example, L ₈ and C ₉ , are increased I _D5 increases towards zero and this could cause diode 5 to be cut off in an undesirable fashion. I _c also increases towards zero, which is liable to cause diode 12 to be blocked and thyristor 11 to trigger prematurely.

From the foregoing it can be clearly seen that the choice of values for L ₈ and C ₉ is subject to four limitations which prevent the values from being increased to lengthen the turn-off time of the driver circuit of first switching thyristor 4 so as to forestall its spurious triggering.

Waveform F shows the voltage v _G4 obtained at the gate of thyristor 4 from the secondary winding 16 coupled to the inductor 7. This voltage is positive from t ₀ to t ₁ and from t ₆ to t ₇ and is negative between t ₂ and t ₆ i.e. while the second switching means 10 is conducting.

The present invention makes the lengthening of the turn-off time of thyristor 4 possible without altering the parameters of the circuit such as inductance 8 and capacitor 9.

In the circuit shown in FIG. 3, which illustrates the principle of the present invention, means are added to the circuit in FIG. 1 which enable the turn-off time to be lengthened by connecting a load to diode 5 so as to increase the current which flows through it during the time that it is conductive. These means are here formed by a resistor 18 connected in parallel with a capacitor 20 (which replaces capacitor 2) which is of a higher capacitance so that, in practice, it holds its charge during at least one half of the line period. FIG. 4, which shows the waveform of the current in the first switching means 3 for a circuit as shown in FIG. 3, makes it possible to explain how this lenthening of the turn-off time is achieved.

In FIG. 4, the broken lines show the waveform of the current in the first switch device 3 in the circuit of FIG. 1, this waveform being produced by adding waveforms B and C of FIG. 2. The current i ₄ above the axis flows through thyristor 4 and current i ₅ below the axis flows through diode 5. When the capacitance C ₂₀ of the capacitor in series with the deflector coil is increased to some tens of microfarads (C ₂ having been of the order of 1 μ F) and when there is connected in parallel with capacitor 20 a resistor 18 the value of which is calculated to draw a strong current I _R18 from capacitor 20, that is to say a current at least equal to 0,1 I _m (I _m being of the order of some tens of amperes), current I _R18 is added to that i ₅ which flows through diode 5 without in any way altering the linearity of the trace portion nor the oscillatory commutation of thyristor 4 which is brought about by the resonant circuit L ₈ , C ₉ .

The fact of loading capacitor C ₂₀ by means of a resistor 18 thus has the effect of permanently displacing the waveform of the current in the negative direction by I _R18 . Thus, during the trace portion of the scan, the transfer of the current from the diode 5 to the thyristor 4 begins at time t ₁₀ instead of t ₀ , that is to say with a delay proportional to I _R18 . The effect of the triggering pulse delivered by the horizontal oscillator (13 FIG. 1) to the second thyristor 11 at time instant t ₁ , will be to start the commutation process of the first thyristor 4 when the current it draws is less by I _R18 than that i ₄ (t ₁ ) which it would have been drawing had there been no resistor 18. Because of this, the turn-off time of the thyristor 4 proper, which as has been mentioned increases with the maximum current level passing throught it, is slightly reduced. Moreover, because the oscillatory current i ₈ ,9 (FIG. 2) from circuit L ₈ , C ₉ which flows through thyristor 4 in the opposite direction is unchanged, it reaches a value equal to that of the current i _L1 (FIG. 1) flowing in the coil 1 in a shorter time, that is to say at time t ₁₂ . Diode 5 will thus take the oscillatory current i ₈ ,9 (FIG. 2) over in advance with respect ro time instant t ₂ and will conduct it until it reaches zero value at a time instant t ₁₃ later than t ₃ , the amounts of advance (t ₂ - t ₁₂ ) and delay (t ₁₃ - t ₃ ) being practically equal.

It can thus be seen in FIG. 4 that the circuit turn-off time T _R of a circuit according to the invention and illustrated by FIG. 3 is distinctly longer than that T _r of the circuit in FIG. 1. This increase in the turn-off time (T _R - T _r ) depends on the current I _R18 and increases therewith.

It should be noted at this point that the current I _R18 produces a voltage drop at the terminals of the resistor the only effect of which is to heat up the resistor since the level of this voltage (40 to 60 volts) does not necessarily have a suitable value to be used as a voltage supply for other circuits in an existing transistorised television receiver.

In accordance with one embodiment of the invention, illustrated in FIG. 5, an application is proposed for the additional current which is to be drawn through diode 5. In FIG. 5, the positive terminal of capacitor 20 is connected by a conductor 19 to the negative pole of the power supply 6 and the voltage at the terminals of capacitor 20 is thus added to that E from the source 6.

In the preferred embodiment of the present invention, which is shown in FIG. 6, it is possible to cause a supplementary current of a desired value to flow through the first diode 5 while obtaining a voltage which has a suitable value for use in another circuit in the television receiver.

If the voltage at the terminals of capacitor 20 in FIG. 3 is not a usable value, it is possible to connect in parallel with the series circuit comprising the deflector coil 1 and the capacitor 2 in FIG. 1, i.e. in parallel with the terminals of the first switching means 3, a series combination of an autotransformer 21 and a high value capacitor 22 (comparable with capacitor 20 in FIGS. 3 and 5). The autotransformer 21 has a tap 23 is suitably positioned between the terminal connected to capacitor 22 at the tap 24 connected to the first switching means 3. This autotransformer 21 may be formed by the one conventionally used for supplying a very high voltage to the cathode ray tube, as described for example in U.S. Pat. No. 3,452,244; such a transformer comprises a voltage step-up winding between taps 24 and 25, which latter is connected to a high voltage rectifier (not shown).

The waveform of the voltage at the various points in the autotransformer is shown in FIG. 7, in which waveform A shows the voltage at the terminals of capacitor 22, waveform B the voltage at tap 24 and waveform C the voltage at tap 23 of the autotransformer 21.

The voltage V _c22 at the terminals of capacitor 22 varies slightly about a mean value V _cm . It is increasing while diode 5 is conducting and decreasing during the conduction of the thyristor 4.

The voltage v ₂₄ at tap 24 follows substantially the same curve as waveform E in FIG. 2, that is to say that during the retrace time interval from t ₁₃ to t ₅ to a positive pulse called the flyback pulse is produced and, during the time interval while the first switching means 3 is conducting, the voltage is zero. The mean valve of the voltage v ₂₄ at tap 24 of the auto-transformer 21 is equal to the mean value V _cm of the voltage at the terminals of capacitors 2 and 22.

Thus, there is obtained at tap 23 a waveform which is made up, during the retrace portion, of a positive pulse whose maximum amplitude is less than that of v ₂₄ at tap 24 and, during the trace portion, of a substantially constant positive voltage, the level V of which is less than the mean value V _cm of the voltage v _c22 at the terminals of capacitor 22. By moving tap 23 towards terminals 24 the amplitude of the pulse during fly-back increases while voltage V falls and conversely by moving tap 23 towards capacitor 22 voltage V increases and the amplitude of the pulse drops.

In more exact terms, the voltage V at tap 23 is such that the means value of v ₂₃ is equal to V _cm . It has thus been shown that by choosing carefully the position of tape 23, a voltage V may be obtained during the trace portion of the scan, which may be of any value between V _cm and zero.

This voltage V is thus obtained by periodically controlled rectification during the trace portion of the scan. For this purpose an electronic switch is used to periodically connect the tap 23 of trnasformer winding 21 to a load. This switch is made up of a power transistor 26 whose collector is connected to tap 23 and the emitter to a parallel combination formed by a high value filtering capacitor 27 and the load which it is desired to supply, which is represented by a resistor 28. The base of the transistor 26 receives a control voltage to block it during retrace and to unblock it during the whole or part of the trace period. A control voltage of this type may be obtained from a second winding 29 magnetically coupled to the inductance 7 of the deflection circuit and it may be transmitted to the base of transistor 26 by means of a coupling capacitor 30 and a resistor 31 connected between the base and the emitter of transistor 26.

It may easily be seen that the DC collector/emitter current in transistor 26 flows through the first diode 5 of the first switching means 3 via a resistor 28 and the part of the winding of auto-transformer 21 located between taps 23 and 24.

Experience has shown that a circuit as shown in FIG. 6 can supply 24 volts with a current of 2 amperes to the vertical deflection circuit of the same television set, the voltage at the terminals of capacitor 22 being from 50 to 60 volts.

It should be mentioned that, when the circuit which forms the load of the controlled rectifier 26, 27 does not draw enough current to sufficiently lengthen the circuit turn-off time T _R , an additional resistor (not shown) may be connected between the emitter of transistor 26 and ground or in parallel to capacitor 22, which resistor will draw the additional current required.

INDESIT TYPE TC26SI CHASSIS VV708 Gating circuit for television SCR deflection system AND REGULATION / stabilization of horizontal deflection NETWORK CIRCUIT with Transductor reactor / Reverse thyristor energy recovery circuit.In a television deflection system

employing a first SCR for coupling a deflection winding across a source of energy during a trace interval of each deflection cycle and a second SCR for replenishing energy to the source of energy during a commutation interval of each deflection cycle, a gating circuit for triggering the first SCR. The gating circuit employs a voltage divider coupled in parallel with the second SCR which develops gating signals proportional to the voltage across the second SCR.


1. In a television deflection system in which a first switching means couples a deflection winding across a source of energy during a trace interval of each deflection cycle and a second switching means replenishes energy to said source of energy during a commutation interval of each deflection cycle, a gating circuit for said first switching means, comprising:
capacitive voltage divider means coupled in parallel with said second switching means for developing gating signals proportional to the voltage across said second switching means; and
means for coupling said voltage divider means to said first switching means to provide for conduction of said first switching means in response to said gating signals.
2. A gating circuit according to claim 1 wherein said voltage divider includes first and second capacitors coupled in series and providing said gating signals at the common terminal of said capacitors. 3. A gating circuit according to claim 2 wherein said first and second capacitors are proportional in value to provide for the desired magnitude of gating signals. 4. A gating circuit according to claim 3 wherein said means for coupling said voltage divider means to said first switching means includes an inductor. 5. A gating circuit according to claim 4 wherein said inductor and said first and second capacitors comprise a resonant circuit having a resonant frequency chosen to shape said gating signal to improve switching of said first switching means.

Description:

BACKGROUND OF THE INVENTION
This invention relates to a gating circuit for controlling a switching device employed in a deflection circuit of a television receiver.

Various deflection system designs have been utilized in television receivers. One design employing two bidirectional conducting switches and utilizing SCR's (thyristors) as part of the switches is disclosed in U.S. Pat. No. 3,452,244. In this type deflection system, a first SCR is

employed for coupling a deflection winding across a source of energy during a trace interval of each deflection cycle, and a second SCR is employed for replenishing energy during a commutation interval of each deflection cycle. The first SCR is commonly provided with gating voltage by means of a separate winding or tap of an input reactor coupling a source of B+ to the second SCR.

Various regulator system designs have been utilized in conjunction with the afore described deflection system to provide for uniform high voltage production as well as uniform picture width with varying line voltage and kinescope beam current conditions.
One type regulator system design alters the amount of energy stored in a commutating capacitor coupled between the first and second SCR's during the commutating interval. A regulator design of this type may employ a regulating SCR and diode for coupling the input reactor to the source of B+. With this type regulator a notch, the width of which depends upon the regulation requirements, is created in the current supplied through the reactor and which notch shows up in the voltage waveform developed on the separate winding or tap of the input reactor which provides the gating voltage for the first SCR. The presence of the notch, even though de-emphasized by a waveshaping circuit coupling the gating voltage to the first SCR, causes erratic control of the first SCR.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the invention, a gating circuit of a television deflection system employing a first switching means for coupling a deflection winding across a source of energy during a trace interval of each deflection cycle and a second switching means for replenishing energy to said source of energy during a commutation interval of each deflection cycle includes a voltage divider means coupled in parallel with the second switching means for developing gating signals proportional to the voltage across the second switching means. The voltage divider means are coupled to the first switching means to provide for conduction of the first switching means in response to the gating signals.
A more detailed description of a preferred embodiment of the invention is given in the following description and accompanying drawing of which:
FIG. 1 is a schematic diagram, partially in block form, of a prior art SCR deflection system;
FIG. 2 is a schematic diagram, partially in block form, of an SCR deflection system of the type shown in FIG. 1 including a gating circuit embodying the invention;
FIG. 3 is a schematic diagram, partially in block form, of one type of a regulator system which employs an SCR as a control device and which is suitable for use with the SCR deflection system of FIG.2;
FIG. 4 is a schematic diagram, partially in block form, of another type of a regulator system suitable for use with the deflection circuit of FIG. 2; and
FIG. 5 is a schematic diagram, partially in block form, of still another type of a regulator system suitable for use with the SCR deflection system of FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 is a schematic diagram, partially in block form, of a prior art deflection system of the retrace driven type similar to that disclosed in U.S. Pat. No. 3,452,244. This system includes a commutating switch 12, comprising a silicon controlled rectifier (SCR) 14 and an oppositely poled damper diode 16. The commutating switch 12 is coupled between a winding 18a of an input choke 18 and ground. The other terminal of winding 18a is coupled to a source of direct current voltage (B+) by means of a regulator network 20 which controls the energy stored in the deflection circuit 10 when the commutating switch is off, during an interval T3 to T0' as shown in curve 21 which is a plot of the voltage level at the anode of SCR 14 during the deflection cycle. A damping network comprising a series combination of a resistor 22 and a capacitor 23 is coupled in parallel with commutating switch 12 and serves to reduce any ringing effects produced by the switching of commutating switch 12. Commutating switch 12 is coupled through a commutating coil 24, a commutating capacitor 25 and a trace switch 26 to ground. Trace switch 26 comprises an SCR 28 and an oppositely poled damper diode 30. An auxiliary capacitor 32 is coupled between the junction of coil 24 and capacitor 25 and ground. A series combination of a horizontal deflection winding 34 and an S-shaping capacitor 36 are coupled in parallel with trace switch 26. Also, a series combination of a primary winding 38a of a horizontal output transformer 38 and a DC blocking capacitor 40 are coupled in parallel with trace switch 26.

A secondary of high voltage winding 38b of transformer 38 produces relatively large amplitude flyback pulses during the retrace interval of each deflection cycle. This interval exists between T1 and T2 of curve 41 which is a plot of the current through windings 34 and 38a during the deflection cycle. These flyback pulses are applied to a high voltage multiplier (not shown) or other suitable means for producing direct current high voltage for use as the ultor voltage of a kinescope (not shown).
An auxiliary winding 38c of transformer 38 is coupled to a high voltage sensing and control circuit 42 which transforms the level of flyback pulses into a pulse width modulated signal. The control circuit 42 is coupled to the regulator network 20.

A horizontal oscillator 44 is coupled to the gate electrode of commutating SCR 14 and produces a pulse during each deflection cycle slightly before the end of the trace interval at T0 of curve 21 to turn on SCR 14 to initiate the commutating interval. The commutating interval occurs between T0 and T3 of curve 21. A resonant waveshaping network 46 comprising a series combination of a capacitor 48 and an inductor 50 coupled between a winding 18b of input choke 18 and the gate electrode of trace SCR 28 and a damping resistor 52 coupled between the junction of capacitor 48 and inductor 50 and ground shapes the signal developed at winding 18b (i.e. voltage waveform 53) to form a gating signal voltage waveform 55 to enable SCR 28 for conduction during the second half of the trace interval occurring between T2 and T1' of curve 41.
The regulator network 20, when of a type to be described in conjunction with FIG. 3, operates in such a manner that current through winding 18a of input choke 18 during an interval between T4 and T5 (region A) of curves 21, 53 and 55 is interrupted for a period of time the duration of which is determined by the signal produced by the high voltage sensing and control circuit 42. During the interruption of current through winding 18a a zero voltage level is developed by winding 18b as shown in interval T4 to T5 of curve 53. The resonant waveshaping circuit 46 produces the shaped waveform 55 which undesirably retains a slump in region A corresponding to the notch A of waveform 53. The slump in waveform 55 applied to SCR 28 occurs in a region where the anode of SCR 28 becomes positive and where SCR 28 must be switched on to maintain a uniform production of the current waveshape in the horizontal deflection winding 34 as shown in curve 41. The less positive amplitude current occurring at region A of waveform 55 may result in insufficient gating current for SCR 28 and may cause erratic performance resulting in an unsatisfactory raster.
FIG. 2 is a schematic diagram, partially in block form, of a deflection system 60 embodying the invention. Those elements which perform the same function in FIG. 2 as in FIG. 1 are labeled with the same reference numerals. FIG. 2 differs from FIG. 1 essentially in that the signal to enable SCR 28 derived from sampling a portion of the voltage across commutating switch 12 rather than a voltage developed by winding 18b which is a function of the voltage across winding 18a of input choke 18 as in FIG. 1. This change eliminates the slump in the enabling signal during the interval T4 to T5 as shown in curve 64 since the voltage across the commutating switch 12 is not adversely effected by the regulator network 20 operation.
A series combination of resistor 22, capacitor 23 and a capacitor 62 is coupled in parallel with commutating switch 12, one terminal of capacitor 62 being coupled to ground. The junction of capacitors 23 and 62 is coupled to the gate electrode of SCR 28 by means of the inductor 50. The resistor 52 is coupled in parallel with capacitor 62.
Capacitors 23 and 62 form a capacitance voltage divider which provides a suitable portion of the voltage across commutating switch 12 for gating SCR 28 via inductor 50. The magnitude of the voltage at the junction of capacitors 23 and 62 is typically 25 to 35 volts. It can, therefore, be seen that the ratio of values of capacitors 23 and 62 will vary depending on the B+ voltage utilized to energize the deflection system. Capacitors 23 and 62 and inductor 50 form a resonant circuit tuned in a manner which provides for peaking of the curve 64 between T4 and T5. This peaking effect further enhances gating of SCR 28 between T4 and T5.
Since the waveshape of the voltage across commutating switch 12 (curve 21) is relatively independent of the type of regulator system employed in conjunction with the deflection system, the curve 64 also is independent of the type of regulator system.
When commutating switch 12 switches off during the interval T3 to T0' curve 21, the voltage across capacitor 62 increases and the voltage at the gate electrode of SCR 28 increases as shown in curve 64. As will be noted, no slump of curve 64 occurs between T3 and T5 because there is no interruption of the voltage across commutating switch 12.



















FIG. 3 is a schematic diagram, partially in block form, of one type of a regulator system which may be used in conjunction with the invention. B+ is supplied through a regulator network 20 which comprises an SCR 66 and an oppositely poled diode 68. The diode is poled to provide for conduction of current from B+ to the horizontal deflection circuit 60 via winding 18a of input choke 18. Current flows through the diode during the period T3 to T4 of curve 21 FIG. 1 after which current tries to flow through the SCR 66 from the horizontal deflection circuit to B+ since the commutating capacitor 25 is charged to a voltage higher than B+.
The horizontal deflection circuit 60 produces a flyback pulse in winding 38a of the flyback transformer 38 which is coupled to winding 38c. The magnitude of the pulse on winding 38c determines how long the signal required to switch SCR 66 on is delayed after T4 curve 21 FIG. 1. If the flyback pulse is greater than desirable, the SCR 66 turns on sooner than if the flyback pulse is less than desirable and provides a discharge path for current in commutating capacitor 25 back to the B+ supply. In this manner a relatively constant amplitude flyback pulse is maintained.
FIG. 4 is a schematic diagram, partially in block form, of another well-known type of a regulator system which may be used in conjunction with the invention shown in FIG. 2. B+ is coupled through winding 18a of input choke 18 and through a series combination of windings 70a and 70b of a saturable reactor 70 and a parallel combination of a diode 72 and a resistor 74 to the horizontal deflection circuit 60. Diode 72 is poled to conduct current from the horizontal deflection circuit 60 to B+.
Flyback pulse variations are obtained from winding 38c of the horizontal output transformer 38 and applied to a voltage divider comprising resistors 76, 78 and 80 of the high voltage sensing and control circuit 42. A portion of the pulse produced by winding 38c is selected by the position of the wiper terminal on potentiometer 78 and coupled to the base electrode of a transistor 82 by means of a zener diode 84. The emitter electrode of transistor 82 is grounded and a DC stabilization resistor 85 is coupled in parallel with the base-emitter junction of transistor 82. When the pulse magnitude on winding 38c exceeds a level which results in forward biasing the base-emitter junction of transistor 82, current flows from B+ through a resistor 86, a winding 70c of saturable reactor 70 and transistor 82 to ground. Due to the exponential increase of current in winding 70c during the period of conduction of transistor 82, the duration of conduction of transistor 82 determines the magnitude of current flowing in winding 70c and thus the total inductance of windings 70a and 70b. The current in winding 70c is sustained during the remaining deflection period by means of a diode 88 coupled in parallel with winding 70c and poled not to conduct current from B+ to the collector electrode of transistor 82. A capacitor 90 coupled to the cathode of diode 88 provides a bypass for B+. Windings 70a and 70b are in parallel with input reactor 18a and thereby affect the total input inductance of the deflection circuit and thereby controls the transfer of energy to the deflection circuit. The dotted waveforms shown in conjunction with a curve 21' indicate variations from a nominal waveform provided at the input of horizontal deflection circuit 60 by the windings 70a and 70b.













FIG. 5 is a schematic diagram of yet another type of a regulator system which may be used in conjunction with the invention. B+ is coupled through a winding 92a and a winding 92b of a saturable reactor to the horizontal deflection circuit 60. Windings 92a and 92b are used to replace the input choke 18 shown in FIGS. 1 and 2 while also providing for a regulating function corresponding to that provided by regulating network 20.
Flyback pulse variations are obtained from winding 38c and applied to the high voltage sensing and control circuit 42 as in FIG. 4. Current flows from B+ through resistor 86, a winding 92c and transistor 82 to ground. As in FIG. 4 the duration of the conduction of transistor 82 determines the energy stored in winding 92c and thus the total inductance of windings 92a and 92b which control the amount of energy transferred to the deflection circuit during each horizontal deflection cycle. The variations in waveforms of curve 21', shown in conjunction with FIG. 4, are also provided at the input of horizontal deflection circuit 60 by windings 92a and 92b.
For various reasons including cost or performance, a manufacturer may wish to utilize a particular one of the regulators illustrated in FIGS. 3, 4 and 5. Regardless of the choice, the gating circuit according to the invention may be utilized therewith advantageously by providing improved performance and the possibility of cost savings by eliminating taps or extra windings on the wound components which heretofore normally provided a source of SCR gating waveforms.

INDESIT TYPE TC26SI CHASSIS VV708 Electronic tuning circuit arrangement for direct and indirect station selection using a memory circuit :Indesit Industria Elettrodomestici Italiana, S.p.A. (Rivalta, IT)

A circuit arrangement for selecting the tuning of a radioelectric signal in a signal receiving set, in particular a television set, comprises a memory circuit having a plurality of cells for storing in digital form information relating to a plurality of tunable signals with means in the circuit arrangement for sequentially scanning the cells of the memory circuit and for obtaining the stored information for the desired selection of a receiving signal.

1. An electronic tuning circuit arrangement comprising:
(a) a control panel (101) having a plurality of push-buttons or sensors;
(b) first means (104) actuable by at least one of said push-buttons or sensors to produce digitally coded information identifying respective ones of a plurality of tunable signals;
(c) second means (128) which receive said digitally coded information and correspondingly supply a respective number (N) in digital form for tuning each signal;
(d) a counter divider (126) connected to receive the digital output of said second means (128) as a divider, and a clock signal (f) derived from a voltage-controlled oscillator (130) as a dividend, for producing a quotient signal (f/N) representing the clock signal frequency divided by said respective number;
(e) means (133) for comparing said quotient signal (f/N) with a frequency reference oscillation (f_r) and producing a resultant signal which is supplied in controlling relation to said voltage-controlled oscillator (130) for causing said oscillator to produce a tuning signal (f_o) directly proportional to said respective number;

(f) a memory circuit (108) having a plurality of cells; said first means (104) supplying to said memory circuit (108), and storing in each of said cells, under the action of push-buttons or sensors of said control panel (101) the digitally coded information relating to each of a plurality of preferred signals preselected by the user from among said plurality of tunable signals; said first means (104) under the action of push-buttons or sensors of said control panel (101) selectively supplying to said counter divider (126) from said second means (128) only one desired respective number in digital form for the tuning of each signal, either through digitally coded information directly supplied to said second means (128) from said first means (104) or through digitally coded information supplied from said memory circuit (108) to said second means (128); and
(g) third means (113) supplying said counter divider (126) from said second means (128) with said respective number in digital form, by sequentially scanning one after another said cells of said memory circuit (108) and then supplying said second means (128) with the stored digitally coded information obtained from each cell scanned.
2. The circuit arrangement of claim 1, wherein said third means (113) comprises an electronic counter whose outputs are connected through gate means (109) to address inputs of said memory circuit (108), and control logic circuits included in said first means (104) which control said gate means (109) and said memory circuit (108) in such a manner that, when the third means (113) are activated, the digitally coded information received by said second means (128) will only be that stored in the cell scanned of said memory circuit (108). 3. The circuit arrangement of claim 2, wherein said counter (113) is a binary counter operable both up and down. 4. The circuit arrangement of claim 3, wherein said counter (113) supplies a four bit output. 5. The circuit arrangement of claim 3, wherein further logic circuits (115, 117, 120, 121) are provided which are activated by manually actuating a push-button or sensor of said control panel (101) for causing the output of said counter (113) to advance or to recede by one step at a time. 6. The circuit arrangement of claim 3, wherein a clock signal of predetermined frequency is fed to the input of said counter (113) upon manually actuating a push-button or sensor of said control panel (101), the output of said counter progressively increasing (or progressively decreasing) by one step at a time as long as said push-button or sensor is actuated. 7. The circuit arrangement of claim 2, wherein second control logic circuits included in said first means (104) are provided which control, through second gate means (122) connected at the outputs of said electronic counter (113), the utilization of said counter (113) for at least a second function. 8. The circuit arrangement of claim 7, wherein, in being utilized for said second function, said electronic counter (113) supplies digit correction signals to said second means (128) and to said counter divider (126), said digit correction signals being also supplied to said memory circuit (108) for storage in a cell corresponding to stored digitally coded information relating to a tunable signal, whereby the stored digitally coded information relating to a tunable signal and the stored digit correction signals from each cell are supplied to said second means (128) and to said counter divider (126) either by said first means (104) or by said third means (113). 9. The circuit arrangement of claim 8, wherein fourth means (112, 124) are provided for stopping said counter in the stage in which it supplies said digit correction signals, when the count reached by said counter, in counting up and down, corresponds to predetermined numbers, said fourth means (112, 124) being inactive during the stage in which said third means (113) operates for sequentially scanning the cells of said memory circuit (108). 10. The circuit arrangement of claim 8, wherein said counter divider (126) receives twelve bits at its input.

11. The circuit arrangement of claim 8, wherein said plurality of push-buttons or sensors includes at least ten push-buttons or sensors numbered from 0 to 9 which are connected to said first means (104) for producing said digitally coded information, at least one push-button or sensor connected to a control circuit for said counter (113) in order to make it advance or recede on command, a push-button or sensor connected to said first means (104) for supplying to said memory circuit (108) and for storing in each cell the digitally coded information preselected by the user from among the information relating to said plurality of preferred signals, and at least a switching-over push-button or sensor connected to said first means (104) for passing from a direct selection condition, in which said first means directly supplies the digitally coded information for a desired one of the tunable signals to said second means (128) whereby the tuning of a signal is selectable by forming a code number of two digits by means of said numbered buttons and in which said counter (113) may supply the digit correction signals, to an indirect selection condition, in which said first means (104) supplies to said second means (128) the digitally coded information for a desired one of the tunable signals stored in a cell of said memory circuit (108), as well as the stored digit correction signals, in response to actuation of one of said numbered buttons, or in which said third means (113) sequentially scan the cells of said memory circuit for supplying the stored digitally coded information and the digit correction signals. 12. The circuit arrangement of claim 1, wherein said memory circuit (108) is a random access memory with memory cells of twelve bits. 13. The circuit arrangement of claim 1, comprising a double binary-seven segments converter (107) for a double seven-segments display (106), the digitally coded information for said second means (128) being supplied from said first means (104) or from said memory circuit (108) in driving relationship to said converter (107).

Description:

BACKGROUND OF THE INVENTION
This invention relates to a circuit arrangement for the selection of one among a plurality of radioelectric signals receivable in a signal receiving set, particularly television signals, comprising a memory circuit in which information relating to a plurality of tunable signals can be stored in digital form. A circuit arrangement of this type is described in copending U.S. patent application Ser. No. 729,757 filed on Oct. 5, 1976 in the name of Mario Malerba and of common assignment herewith.

Such circuit arrangement, applied, for example, to a television set, comprises a voltage controlled oscillator (VCO) whose output signal has a frequency determined by a control loop as a function of a number N different for each one of the frequencies of the selectable signals and obtained from a memory circuit. To select a frequency of a television channel, the number of the channel is set, for example, by means of a push button panel having ten push buttons numbered from 0 to 9, as that of a pocket calculator, and is sent as an address to the memory circuit which substantially produces the number N corresponding to the frequency to be selected. In this way, it is possible to select directly any one of 100 tunable channels, by forming a number of two figures from 00 to 99 on the push button panel. Moreover, it is possible to apply to the tuning thus obtained, which is the theoretical tuning, a manual correction by means of two further push buttons, which determines a variation of the less significant digits of the number N. Thus, it is possible to store in one of the cells of a second memory circuit the information for forming the number N, which is relative to the tuned channel, and to correlate it to a chosen one of the ten push buttons of the panel, so that it will then be possible to read out the ten stored channels with the tunings already corrected.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved electronic tuning circuit arrangement which, by adding a further possibility of selection of stored channels, ameliorates the convenience of tuning for the user.
It is also an object of the invention to provide for the above object to be attained in a very economical way by utilizing devices already existing in the circuit of the receiving set.
A further object of the present invention is to provide an electronic tuning circuit arrangement for a signal receiving set, in particular a television set, comprising a memory circuit having a plurality of cells for storing in digital form information relating to a plurality of tunable signals; and means for sequentially scanning the cells of the memory circuit and for obtaining the stored information for the desired selection of a tunable signal.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the invention, it will now be described in detail with reference to the accompanying drawings given by way of example and in which:
FIG. 1 shows a diagram of a circuit arrangement for a digital control tuner in a television signal receiving set, embodying the principles of the present invention; and
FIGS. 2 and 3 respectively show in detail the control unit and processing unit depicted as blocks in FIG. 1.
DETAILED DESCRIPTION OF THE INVENTION
In FIG. 1, there is diagramatically shown a control board 101 having ten push buttons or touch sensors numbered from 0 to 9, and having, moreover, four additional push buttons or sensors distinguished by the indications D, M, +, -.
Each of the ten push buttons numbered from 0 to 9 is connected to the input of a decimal-binary converter logic circuit 102 having four output conductors on which the information corresponding to the number of the actuated push button appears in binary code.
These four conductors, together with two conductors connected to the push buttons D and M and with a further output conductor from an AND gate 103, arrive at respective inputs 500, 501, 502, 503, 519, 520 and 521 of a control unit 104 comprising a plurality of logic circuits which operate on the input signals in a manner to be described later. Unit 104 may be of the type described in the aforementioned copending U.S. patent application Ser. No. 729,757 and it possesses fifteen outputs 504-518, the first eight (504-511) of which are connected to the inputs of:
a circuit converter 105, converting the data in BCD code into data in binary code, which converts into a single binary number (of seven bits) two binary numbers (of four bits each) which it receives, giving to them the respective weight;
a double seven-segments display 106, through a double binary-seven segments converter 107; and to eight of the twelve inputs-outputs of a RAM (Random Access Memory) 108 having ten memory cells of twelve bits and preferably of the non-volatile type.
The subsequent four outputs 512-515 of the control unit 104 are connected to four address inputs of RAM 108 to which are also connected four outputs of a separator (or buffer) circuit 109 which has an enabling input CE (Chip Enable) connected to the output of gate 103. Separator circuit 109 may conveniently be represented by four AND gates.
The remaining three outputs 516-518 of control unit 104 are connected:
the first: to an input of AND gate 103, to the read-write (R/W) input of RAM memory 108, to the input of an inverting gate 111 and finally to an input of an OR gate 112 having four inputs;
the second: to the enabling input CE of RAM memory 108;
the third: to the reset input R of a four bit counter 113 capable of counting up and down, from zero to nine.
The push button + of control board 101 is connected, through a conductor 114, to an input of an AND gate 115; the push button - is connected, through a conductor 116, to an input of an AND gate 117. The outputs of the gates 115 and 117 are connected to two inputs SET 118 and RESET 119 of a bistable multivibrator 120 and also to the two inputs of an OR gate 121. One output of multivibrator 120 is connected to a count inversion input U/D (UP-DOWN) of counter 113; the output of gate 121 is connected to the second input of gate 103 and to the clock input of counter 113. The four outputs of counter 113 are connected both to the inputs of separator circuit 109 and to the inputs of another identical separator circuit 122. Circuit 122 has an enabling input CE which is connected to the output of inverting gate 111, which output is connected also to an input of a four input NAND gate 124.

Separator circuit (or buffer) 122 has three outputs (of which one, which corresponds to the most significant input, is free) which are connected to the remaining inputs both of gate 112 and of gate 124. The output of NAND gate 124 is connected to the second input of AND gate 115; the output of OR gate 112 is connected to the second input of AND gate 117.
The three outputs of buffer 122 are connected also to three of the remaining inputs-outputs of RAM 108. The two less significant outputs of buffer 122 are connected also to two (the less significant) of twelve inputs of a twelve bit binary counter-divider 126; the third output of buffer 122 is also connected to an input 127 of a processing unit 128 which comprises a plurality of logic circuits and an adder circuit and whose operation will be described later. Processing unit 128 may conveniently be of the type described in my copending U.S. patent application Ser. No. 735,564 filed on Oct. 26, 1976 and of common assignment herewith. The seven outputs of converter circuit 105 are connected to as many inputs 530-536 of processing unit 128 which has ten outputs 540-549 connected to the remaining ten most significant inputs of counter 126. A voltage controlled oscillator (VCO) 130 supplies to the tuner (not shown) a local frequency oscillation f_o for frequency conversion and supplies this local oscillation also to a frequency divider (or prescaler) 131 which divides in the ratio 1:256.
At the output of divider 131, there is present a frequency oscillation f which arrives as a clock signal at counter 126 which produces a frequency signal f/N, where N is the number in binary code which is present at the twelve inputs of counter 126. The output of counter 126 is connected to a first input 132 of a phase comparator 133 which has a second input 134 which receives from a circuit 135 of well-known type a frequency reference oscillation f_r. Circuit 135 may comprise, for example, a line frequency oscillator, tuned by line synchronism pulses, followed by a frequency divider circuit which divides, for example, in the ratio 1:16.
The output of comparator 133 is connected to the input of oscillator 130, and it controls the frequency f_o so that: f/N=f_r
and consequently, with the hypotheses assumed: f_o =256 N f_r (1)
The processing unit 128 has another two outputs 140 and 141 which supply to the tuner the informations relative to band change.
Control unit 104 of FIG. 1 is shown in detail in FIG. 2, and it represents a part of the circuit disclosed in the aforementioned copending U.S. patent application Ser. No. 729,757. In the diagrammatic representation of FIG. 2, the groups of conductors which follow the same path of connection are shown by a single line, by the side of which a numeral indicates how many conductors the group contains; where no numeral is present, it means that the line is formed by a single conductor.
The inputs 500, 501, 502, 503 of control unit 104 are connected through four conductors to inputs of three identical latches, indicated in FIG. 2 by reference numerals 611, 612 and 613, each of which is provided with four inputs and with an enabling input IE (Input Enable). The outputs of latches 611 and 612 are connected, through two lines of four conductors each, and through a separator circuit (or buffer 649) to the two groups of four outputs of circuit 104, respectively 504, 505, 506, 507 and 508, 509, 510, 511.

The inputs 500, 501, 502 and 503 are also connected to inputs of an OR gate 605. The input 520 is connected to a further input of the gate 605 and to an input of a bistable multivibrator (flip-flop) 608 provided with a reset input R. The input 519 is connected to an input of a bistable multivibrator (flip-flop) 609 and to an input of an OR gate 610 having two inputs.
The output of gate 605 is connected to the input of a bistable multivibrator (flip-flop) 615 provided with a reset input R, this latter being connected to the output of the gate 610. Multivibrator 615, as well as multivibrators 608 and 609, have two outputs, one of which is at the opposite logic level of the other. For simplicity of representation, only one output is shown in FIG. 2; however, it can be seen that said output arrives sometimes to negative inputs of gates or to inverter circuits, such as that indicated by reference numeral 617. It is clear that, actually, the corresponding circuits are connected to the negative output of the respective multivibrator.
Thus, the negative output of multivibrator 615 is connected through a delay circuit 618 to:
one input of an AND gate 619 having two inputs;
one input of an AND gate 620 having two inputs;
and, through an additional delay circuit 622, to a differentiator circuit 623.
The positive output of multivibrator 615 is, in turn, connected to an input of an AND gate 624 having two inputs, also through a delay circuit 618 (the delay circuit 618, instead of being disposed at the outputs, may be disposed at the input of multivibrator 615).
The positive output of multivibrator 608 is connected to:
a light source 602, for illuminating the push button M
and, through a delay circuit 625, to the other input of the AND gate 620.
The delay circuits 618, 625 and 622, which produce a time delay equal to τ₁, τ₂ and τ₃ respectively, are such that τ₁ <τ₂ <τ₃.
The negative output of multivibrator 608 is connected:
to the other input of AND gate 619, and to
the other input of AND gate 624.
The outputs of gates 619 and 624 are connected to enabling inputs IE of latches 611 and 612, respectively.
The output of AND gate 620 arrives at an input of an OR gate 626 having two inputs.
The positive output of multivibrator 609 is connected to:
a light source 603, for illuminating the push button D; and
to the enabling input CE of the buffer 649.
The negative output of multivibrator 609 is connected to:
the other input of gate 626; and
through the inverter 617, to the output 516.
The output of gate 626 is connected to the output 517 and, through an inverter 651, to an input of an OR gate 650; the output of latch 613 is connected, through a four conductor line, to the outputs 512, 513, 514 and 515.
A terminal S which receives the external supply voltage is connected, through a switch 641 of the receiving set, to a differentiator circuit 642 whose output is connected:
to the reset input R of multivibrator 609;
to the other input of gate 610; and
to an input of an OR gate 643 having two inputs.
The other input of gate 643 is connected to the output of differentiator circuit 623; the output of gate 643 is connected to the reset input R of multivibrator 608 and to the output 518. The input 521 is connected to the other input of gate 650. The output of gate 650 is connected to an output disable terminal OD of latch 613.
The processing unit 128 is shown, in detail, in FIG. 3, and it represents a part of the circuit disclosed in the aforementioned copending U.S. patent application 735,564. The seven inputs 530, 531, 532, 533, 534, 535 and 536 are connected to seven wires indicated by I, II, III, IV, V, VI and VII.
Wires I and II are connected to the inputs of an OR gate 701 whose output, together with a connection from wire III, is connected to the inputs of an OR gate 702. The output of OR gate 702 is connected to an input of an OR gate 703, to an input of an AND gate 704 and to an input of an OR gate 705. Wires VI and VII are connected to the two inputs of an OR gate 706 whose output, together with a connection from wire V, is connected to the two inputs of an AND gate 707. The output of this AND gate 707, together with a connection from wire IV, is connected to the two inputs of a NOR gate 708 whose output is connected to the other input of OR gate 703. The output of OR gate 703 is connected both to an input of an AND gate 709, and to an inverter 710. The output of AND gate 707 is connected also to an input of an OR gate 711, the other input of which having connected thereto the output of OR gate 701. The output of OR gate 711 is connected to an input of an OR gate 712, the other input of which has connected thereto the output of an exclusive NOR gate 713 whose two inputs are connected to the wires III and IV. The output of OR gate 712 is connected to the other input of AND gate 709. The output of AND gate 709 is connected to the other input of AND gate 704, to the input of an inverter 714, to an input of an AND gate 715, to an input of a NOR gate 729 and to an input 17 of an adder 716 which effects the addition of a first addend of nine binary digits, which it receives at inputs numbered from 11 to 19, with a second addend of ten binary digits which it receives at inputs numbered from 21 to 30. The output of AND gate 704 is connected to an input of an OR gate 717, to an input of NOR gates 718, 719 and 720 respectively, and to the input 19 of adder 716. The output of inverter 714 is connected to an input of an OR gate 721, to an input of an AND gate 722 and to the input 18 of adder 716. The other input of gates 721 and 722 is connected to a wire to which is applied a signal at logic level "0". The output of the AND gate 722 is connected to the other input of the OR gate 717 and to an input of an AND gate 723.
The wire α is connected also to an input of exclusive OR gates 725, 726, 727 and 728 respectively. Gate 725, whose other input is connected to the wire IV, has its output connected to the other input of NOR gate 729. Gate 726, whose other input is connected to the wire V, has its output connected to the other input of gate 720. Gate 727, whose other input is connected to the wire VI, has its output connected to the other input of gates 719 and 723. Gate 728, whose other input is connected to the wire VII, has its output connected to the other input of gate 718. The wire V is connected to an input of two AND gates 730 and 731 respectively. Gate 730, whose other input is connected to the output of gate 723, has its output connected to an input of an OR gate 732, whose output is connected to the other input of gate 731 and to the input of an inverter 733. Connected to the other input of gate 715 is the wire α, and the output of gate 715 is connected to the other input of OR gates 705 and 732. The output of gate 718 is connected to the input 11 of adder 716. The outputs of gates 719 and 731 are connected to the two inputs of an OR gate 735, whose output is connected to the input 12 of adder 716. The output of gate 720 is connected to the input 13 of adder 716. To the inputs 14, 15 and 16 of adder 716 are connected, respectively, the outputs of NOR gate 729, of OR gate 705 and of inverter 710. To the inputs 21, 22 and 23 of adder 716 there are connected the outputs of inverter 733, of OR gate 721 and of OR gate 717, respectively. The inputs from 24 to 30 of adder 716 are connected, respectively, to the wires VII, VI, V, IV, III, II and I.
Adder 716 has ten outputs, indicated progressively by reference numerals 41 to 50, which are respectively connected to the ten outputs (540, 541, 542, 543, 544, 545, 546, 547, 548, 549) of processing unit 128.
The input 127 is connected to an additional input 62 of adder 716.
The outputs of inverter 714 and of gate 704 are respectively connected to outputs 140 and 141.
The operation of the circuit arrangement of FIG. 1 will now be explained.
Control unit 104 comprises a plurality of logic circuits which operate on the various input signals so as to supply, in the various stages of operation which will be listed, the following levels of the output signals:
(I)--At the switching on of the receiving set:
"zero" on all the first twelve outputs 504-515;
"one" on the thirteenth output 516 (the RAM memory 108 therefore disposes itself to be "read", and the buffer circuit 122 is disabled);
"one" on the fourteenth output 517 (the RAM memory 108 is enabled);
a pulse on the fifteenth output 518, which pulse causes the output of the counter 113 to assume the value which has been set and which is equal to four.

In fact, at the moment of switching on the receiving set, by means of the switch 641, the three multivibrators 608, 609 and 615 are reset by means of differentiator circuit 642 and gates 610 and 643, and the outputs of said three multivibrators become "zero" level (reference is made here, as well as hereinafter, unless otherwise stated, to the normal, not negative, outputs), so that the circuit arrangement is prepared for indirect selection as will be better explained later. For accomplishing indirect access by switching on the receiving set, however, it is assumed that memory 108 has been pre-loaded by the user with the desired channels. It will, however, be useful to initiate the explanation by referring to the operation on direct station selection.
(II)--By actuating the push button D and then a couple of numbered push buttons of the control board 101 (for example the one with the digit 1 and then the one with the digit 2), whereby the signals corresponding to said two digits arrive at the control unit 104 successively, through the converter 102;
the digit (in binary code) which corresponds to the first numbered push button which has been actuated (i.e. 1) appears on the first four outputs 504-507;
the digit (in binary code) which corresponds to the second numbered push button which has been actuated (i.e. 2) appears on the second four outputs 508-511; moreover, there is:
"zero" on the third group of four outputs 512-515;
"zero" on the thirteenth output 516 and fourteenth output 517 (the memory RAM 108 is disabled and the buffer circuit 122 is enabled);
a reset pulse on the fifteenth output 518, which pulse causes the output of the counter 113 to assume the value of +4.
In fact, by pressing push button D of panel 101, a "one" signal is produced at input 519. Accordingly, multivibrator 609, which has been reset at the moment of switching on the receiving set, changes state and its output becomes high, thereby producing the switching on of light source 603, the signal "zero" at output 516, and the signal "zero" at output 517. Actually, gate 620 has an input at low level (the one connected to the output of multivibrator 608 through delay circuit 625) and, accordingly, gate 626 has both inputs at low levels. Then, when the number of the channel to be selected is formed (in this case, the number 12), the user presses first the push button having the numeral 1 and then the push button having the numeral 2 (should he want to select a channel having a number less than 10, it is necessary to form 01, 02, etc.). The corresponding signals in binary code arrive at inputs 500 . . . 503 of control unit 104, and the output of multivibrator 615, which is reset by pressing push button D, becomes high level when the push button bearing the numeral 1 is pressed, and returns to low level when the push button bearing the numeral 2 is pressed.

After having pressed push button D, the latch 611, after the time τ₁ has elapsed, becomes enabled and therefore receives in binary code the number 1 from inputs 500 . . . 503 of control unit 104, but after elapsing of the time τ₁ from the moment at which the push button having numeral 1 has been pressed, latch 611 is disabled and latch 612 is enabled and thus receives the number 2.
Therefore, the numbers 1 and 2 appear, in binary codes, at the outputs 504 . . . 507, and 508 . . . 511 respectively, the buffer 649 being enabled.
After the time (τ₁ +τ₃) has elapsed, a pulse appears at output 518 (through differentiator circuit 623 and gate 643). The signal "zero" at the output of gate 626, through gate 650, produces a "one" signal at input OD of latch 613 which disables the outputs of latch 613 which remain at level "zero".

At this point, oscillator 130 is caused by the loop formed by circuits 131, 126, 133 and 130 to supply an oscillation frequency f_o given by the relation (1), i.e. at the theoretical frequency required for receiving channel 12. In fact, processing unit 128 receives the number 12 in binary code from converter 105, and moreover, counter 113 supplies the number four. Processing unit 128, through buffer circuit 122 which is enabled, receives therefore an additional "1" at the input 127; and processing unit 128, which supplies a number suitable for each channel, supplies at its outputs 540-549 for channel 12 the number 263 (see the following Tables I and II) which arrives in binary code at the ten most significant inputs of counter 126.

TABLE I

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EUROPEAN CHANNELS BAND (K) fo (MHz)

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I 02 87 03 94 04 101 III 05 214 06 221 07 228 08 235 09 242 10 249 11 256 12 263 ... ... 20 319 UHF 21 510 22 518 23 526 24 534 ... ... ... ... 67 878 68 886 69 894

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TABLE II

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Channel lst Addend 2nd Addend input Outputs (k) Code inputs 11... inputs 21... 62 41...(fo)

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3 03 0001000100 0000011001 1 94 10 10 0010100101 0001010011 1 249 12 12 0010100011 0001100011 1 263 18 18 0010011101 0010010011 1 305 21 21 0101010000 0010101101 1 510 69 69 0101010000 1000101101 1 894

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Counter 126 results therefore in being set (since it receives also two "zeroes" from buffer circuit 122) to divide by N=263×4=1052. For the relation (1) it results thus, if f_r =15625/16=976.5625 Hz; f_o =256×976.5625×1052=263×10⁶ Hz
which, assuming the intermediate frequency of the receiving set to be calibrated for a value of 38.75 MHz, is just the theoretical frequency of oscillator 130 which is necessary to receive channel 12 whose video carrier has the frequency of 224.25 MHz.
Let us see now how one gets the value of adder 716 to be equal to frequency f_o.
At wires I . . . VII of processing unit 128 are applied, from inputs 530 . . . 536, signals representing in binary code (0-1) the number 12, the signal on wire VII being of the less significant digit, while that on wire I is of the most significant digit.
Referring to FIG. 3, it can be seen that the circuit formed by logic OR gates 701 and 702 supplies a signal at level 1 for all those circuits whose number is greater than 15; the further circuit formed by OR gate 706, AND gate 707, NOR gate 708, OR gate 703, and by inverter 710 supplies, in combination with the preceding circuits, a signal at level 1 for channels whose number is between 5 and 15; the circuit formed by gates NOR exclusive 713, or 711, OR 712 and AND 709 and by inverter 714 supplies, in combination with the preceding circuits, a signal at level 1 for the channels having a number between 5 and 20; finally, AND gate 704 supplies, in combination with the preceding circuits, a signal at level 1 for all those channels whose number is greater than 20. All this will be clearly apparent from the following Table III.

TABLE III

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Output gate signal Input of at high level (1) produced by input adder 716 signals on wires I, II, III, IV, V, VI connected Output VII determined by the selection of to gates: channels: output gate

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701 32 to 99 702 16 to 99 703 0 to 4; 16 to 99 704 21 to 99 19 705 16 to 99 15 706 1 to 3; 5 to 7; 9 to 11; 13 to 15; 17 to 19; 21 to 23; and so on. 707 5 to 7; 13 to 15; 21 to 23; 29 to 31; 37 to 39; and so on. 708 0 to 4; 16 to 20, 32 to 36; 48 to 52; and so on. 709 0 to 4; 21 to 99 17 710 5 to 15 16 711 5 to 7; 13 to 15; 21 to 23; 29 to 99 712 0 to 7; 13 to 15, 21 to 99 713 0 to 7; 24 to 31; 48 to 55; 72 to 79; 96 to 99 714 5 to 20 18 715 -- 717 21 to 99 23 718 even channels from 0 to 20 11 719 0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20 720 0 to 3; 8 to 11; 16 to 19 13 721 5 to 20 22 722 -- 723 -- 725 8 to 15; 24 to 31; 40 to 47; and so on. 726 4 to 7; 12 to 15; 20 to 23; 28 to 31; 36 to 39; and so on. 727 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, and so on. 728 odd channels 729 5 to 7; 16 to 20 14 730 -- 731 -- 732 -- 733 0 to 99 21 735 0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20 12

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It has to be noted that, with the hypotheses which have been made and with reference to Table I, which is an internationally established table setting forth for each channel number a predetermined value of frequency assigned for the video carrier, the frequency f_o is bound to the number K of the television channel by the following relations, for the various ranges:
BI (channels 2 to 4): f_o =73+7K=[64+(7-K)]+[8K+1]+1
BIII (channels 5 to 15): f_o =179+7K=[160+(15-K)]+[8K+3]+1
BIII (channels 16 to 20): f_o =179+7K=[144+(31-K)]+[8K+3]+1
UHF (channels 21 to 99): f_o =342+8K=[336]+[8K+5]+1
Said relations, for the various ranges of tunable signals, are seen to be of the type f_o =M+RK, where R is a number indicative of the channel's step frequency in a predetermined range and M is indicative of a basic value of frequency which has to be fixed in said range. These relations, which give the value of f_o, are not calculated directly in the circuit, but are obtained by calculating the second expressions comprising the terms shown above in square brackets. It should be noted also that for multiplying a binary number by eight it is sufficient to add three zeroes to it, and that the expressions (7-K); (15-K); (31-K) are obtained from the last three or four inverted digits of the number K expressed in binary code, as shown by the following examples (the last three digits in band I, the last four digits in band III)

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K = 3 = 011 7-K = 4 = 100 K = 10 = 1010 15-K = 5 = 0101 K = 18 = 10010 31-K = 13 = 1101

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If the first expression between square brackets of the relations written hereinabove is sent to the inputs 11 to 19 of adder 716 and the second expression between square brackets is sent to the inputs 21 to 30 of adder 716, there remains to be added only the digit outside the square brackets, which is always 1, and it is added on the additional input 62. The first expression between square brackets, which is of the type (P-K) for the European VHF channels and P for the channels in UHF, is formed and sent to the inputs 11 to 19 in the following manner.
The number P is obtained from a series of logic gates, as will be explained hereinafter; the term -K or zero is obtained by connecting wires IV, V, VI and VII (which correspond to the four less significant digits of the number K) to the four less significant inputs of the left-hand side of adder 716, i.e. 11, 12, 13 and 14 through the four OR exclusive gates 725, 726, 727 and 728 and through the four NOR gates 729, 720, 719 and 718. Said NOR gates act as inverters (to obtain the minus sign for the European channels in the VHF range). As can be seen from FIG. 3, OR gate 729 is blocked in the UHF range and in Band I (in which three digits only have to be inverted). The other three gates 718, 719 and 720 are blocked in the UHF range, so that in the UHF range at the inputs 11, 12, 13 and 14 of adder 716 there arrive four zeroes.
The second expression between square brackets, which is of the type [8K+S], is obtained in a simple way by connecting the seven most significant inputs of the right hand side of adder 716, i.e. from 24 to 30, to the seven wires I-VII corresponding to the seven digits of the number K of the channel, and by connecting the remaining three inputs 21, 22 and 23 to logic gates for obtaining the number S (which is always less than 8).
The annexed Table II summarizes the functions of adder 716 on six European channels taken as an example.

Observing Table II, it can be seen that the first digit (starting from the right) of the second addend is always 1, said first digit is obtained by means of AND gates 730, 723 and 715, OR gate 732 and inverter 733. The second digit of the second addend is 1 in Band III, this being obtained by means of OR gate 721. The third digit is 1 in UHF; this is obtained by means of AND gate 722 and OR gate 717. In the first addend, the fifth digit is 1 in the channels over 15, which is obtained by means of OR gate 705; the sixth digit is 1 in the channels between 5 and 15, which information is already available from inverter 710; the seventh digit is always 1, except in Band III, while the eighth digit, instead, is 1 in Band III (such information being available upstream and downstream of inverter 714); the ninth digit is 1 in the UHF range and is obtained by means of AND gate 704.
Moreover, inverter 714 supplies a signal at level "1" when the selected channel is in Band III of the VHF range, and said signal is available at output 140; while the output of AND gate 704 supplies a signal at level "1" when the selected channel is in the UHF range, and said signal is available at output 141. The signals at outputs 140 and 141 are supplied to the tuner of the receiving set for controlling its band switch-over members. Processing unit 128 is also suitable for use with a tuner designed to recieve the signals of American television channels instead of European ones, as American channels are spaced by a 6 MHz step both in VHF and in UHF. Thus, the expressions of f_o are all of the type f_o =T+6K, where T is a fixed number, which expressions are obtainable easily by breaking the factor 6 into (4+2), i.e. f_o =T+4K+2K, and where it is clear that to multiply by two in binary code it is sufficient to add a zero, and to multiply by 4 it is sufficient to add two zeroes; or, it is possible to obtain the factor 6 as (8-2), and so on.
Therefore, it is sufficient to send the signals representing said number K to a first counter whose least significant input receives a zero and to a second counter having two least significant inputs each of which receives a zero and then add to the binary signals representing said number T the binary outputs of the first and second counters.
At this point the set is therefore tuned to the theoretical frequency corresponding to channel 12.
If it is desired to effect a correction of the tuning, it is sufficient to press the push button + or the push button - of control panel 101. By pressing the push button +, a signal arrives at AND gate 115, which is enabled by the output at level "1" of NAND gate 124, so that counter 113 increases the count by one unit, i.e. the output passes from four to five. By pressing the push button -, a signal arrives at AND gate 117, which also is enabled by the output at level "1" of OR gate 112, and counter 113 shifts down the output by one unit, i.e. passes to three. Therefore, through buffer 122, the output of the counter, varied by one unit, arrives at processing unit 128 and at counter 126, whereby the number N correspondingly increases or decreases by one unit. As a result, the frequency f_o increases or decreases by 0.25 MHz.
Gates 115, 117, 112 and 124 prevent counter 113 from rising above 7 and from dropping below zero, to avoid sudden jumps of tuning. In fact, with the output of counter 113 at the value 7, the output of NAND gate 124 passes to the value "0", so that gate 115 is blocked, thereby inhibiting the action of further pulses on connection 114 to increase the count.
When, instead, the output of counter 113 is at the value zero, the output of OR gate 112 passes to "0" and gate 117 is blocked, thereby inhibiting the action of further pulses on connection 116 to reduce the count.
(III)--If now one actuates push button M and then a numbered push button (for instance, the push button 3), control unit 104, which receives the signals, supplies in output:
on the first group 504-507 and second group 508-511 of four outputs, always the same digit as before, i.e. 1 and 2 respectively;
on the third group 512-515 of four outputs, the digit corresponding to the last push button actuated, i.e. 3;
"zero" on the thirteenth output 516 (buffer circuit 122 is enabled) and also on the fifteenth output 518 (the output of counter 113 is not varied);
"one" on the fourteenth output 517 (memory 108 is enabled to be "written").
More particularly, on pressing push button M, there is produced a signal at input 520, the light source 602 is switched on, the enabling inputs of latches 611 and 612 are disabled and, after the time τ₂, the output of gate 620 becomes at level 1 together with output 517, as soon as the output of multivibrator 615 becomes at its low level again. Moreover, the output of multivibrator 615 becomes at its high level as soon as the push button M has been pressed and after having pressed the push button which bears the numeral 3, the number 3 is stored in latch 613 (always enabled) and after the time τ₁ has elapsed (to ensure that latch 613 is charged), output 517 becomes at level 1, there being "zero" at input OD of latch 613 so that the number 3 appears at outputs 512 . . . 515.
The number 12, which arrives at the first eight inputs of memory 108, is therefore stored at the address three, the number 3 arriving from control unit 104 at the address inputs of memory 108, and moreover, by means of the last three inputs of memory 108, there is stored the number which corresponds to the tuning correction (for example, the number five, if the push button + has been pressed once before starting the storage stage).
When, after a suitable period of time, memory 108 has stored said information, the last seven outputs 512-518 of control unit 104 automatically return to zero, so that memory 108 is disabled, and moreover there is a pulse on the fifteenth output 518 for restoring the output of counter 113 on the present value of four.

More particularly, after a time (τ₁ +τ₃), there is a pulse at output 518, and multivibrator 608 is reset (through differentiator circuit 623 and through gate 643), light source 602 is extinguished to indicate that the storage has been accomplished and, after a further time τ₂, the output of gate 626 returns to "zero" as does output 517 and the signal at input OD of latch 613, which brings to zero the outputs 512-515.
At this point, if a different pair of numbered push buttons of control panel 101 is pressed, the receiving set is thereby tuned to the corresponding frequency (i.e. the case in paragraph II recurs). Thus, it is possible to correct tuning by means of the push buttons + or - and, if desired, the new channel, with the tuning corrections, can be stored at another address of memory 108, i.e. the operation in case (III) recurs.
It is thus possible to select up to 100 different channels (00 to 99) and to store up to ten of them (in the addresses from 0 to 9 memory 108).
(IV)--By again actuating the push button D, the circuit arrangement returns to the situation previously described herein in paragraph (I) so that it is prepared for indirect station selection.
By then pressing one of the numbered push buttons of control panel 101 (for instance, the push button having the number 3), indirect station selection becomes operative and control unit 104 supplies the following outputs:
the first eight outputs 504-511 are insulated;
the digit corresponding to the actuated push button (for example 3) appears on the third group of four outputs 512-515;
on the thirteenth (516), fourteenth (517) and fifteenth (518) outputs there are present the same signals of the case in paragraph (I), i.e. "1", "1", and a short pulse.
More particularly, by pressing push button D, there is produced a signal at input 519, thus the output of multivibrator 609 returns to zero, light source 603 is extinguished, outputs 516 and 517 become "1" and the outputs of latch 613 are enabled, while buffer 649 is disabled and the outputs 504-507 and 508-511 are insulated. In this condition, by pressing push button 3 of control panel 101, the corresponding number is stored in latch 613 from inputs 500-503 and appears at outputs 512-515.
Under these conditions, the two buffer circuits 109 and 122 are both disabled and all the information to processing unit 128 and to counter 126 is supplied by memory 108 which is enabled to be read, this information being that which was previously stored in the case of paragraph (III) at the selected address, which in this case is the third address. Therefore, the receiving set becomes tuned to channel 12 (whose number is indicated also by display 106), with the tuning correction effected some time before. At this point, a different numbered push button of control panel 101 may be actuated, whereby memory 108 will supply new information to processing unit 128 and to counter 126 in order to obtain the tuning of the channel which has been stored therein.
(V)--The selection of the channels stored in memory 108 may, however, be effected also in the following different way. By pressing the push button + (or the push button -) of control panel 101, counter 113 increases by one unit (or reduces by one unit) the value of the output and, by means of gate 103, buffer 109 is enabled. Moreover, by means of the connection from the output of gate 103 to input 521 of control unit 104, a signal "one" arrives at input OD of latch 613 and the third group of outputs 512-515 of control unit 104 is insulated. Accordingly, memory 108 receives at the address inputs the number formed by counter 113 (for example, the number 5) and supplies to processing unit 128 and to counter 126, in the same manner as in case (IV), the information of the channel stored at the address five.
By successive actuations of the push button + (or -) it is possible to automatically scan sequentially up (or down) the ten addresses of memory 108, i.e. to tune in successively the ten stored channels.
The output of counter 113 no longer stops at seven or at zero, because when the thirteenth output of control unit 104 is at level "1" (i.e. memory 108 is conditioned to be read) gates 112 and 124 supply always signals at level "1", so that gates 115 and 117 are never locked. The number supplied by counter 113 remains at the address input of memory 108 even after the push button + or - has been released (and consequently buffer 109 is disabled again), inasmuch as it is maintained by a special latch conveniently contained in control unit 104.
Said special latch, designated in FIG. 2 by the numeral 560, has its input and output connected at control unit outputs 512, 513, 514 and 515, its IE terminal (Input Enable) connected at control unit input 521, and its OD terminal (Output Disable) connected at the output of gate 650. In this manner, when the push button + (or -) is actuated and there is a signal at level 1 at input 521, special latch 560 holds the number present at outputs 512, 513, 514 and 515 from counter 113, without transferring it to its output. When the push button + or - has been released, and the signal at input 521 becomes zero, the input of special latch 560 is insulated and the signal zero at its OD terminal transfers to the output and then to outputs 512, 513, 514 and 515, and therefore to the addresses of memory 108, the number previously stored from counter 113.
For a clearer explanation, the following Table IV is presented to show a recapitulatory scheme relating to the various cases described hereinabove.

TABLE IV

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Outputs of control Enablings of the unit 104 Memory 108 set circuits case 516 517 to be: enabling 103 109 122

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II 0 0 written no no no yes III 0 1 written yes no no yes I-IV-V 1 1 read yes yes x no

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(x) is enabled by pressing one of the push buttons + or -.
Hence, the circuit arrangement according to the present invention affords a considerable convenience for the user, since in order to scan the various channels stored in memory 108 it is sufficient to actuate the push buttons + or -.
From the foregoing description, the advantages of the circuit arrangement according to the present invention are clearly apparent; of course, variations in what has been described by way of example will be possible to those skilled in the art, without departing from the scope of the invention.
Thus, for instance, it is possible to send to counter 113 a signal at clock frequency (derived, for example, from a division of the frequency produced by circuit 135) and to cause it to reach the input of counter 113 only when the output of gate 121 is at high level. In this way, as long as the push button + is pressed, the output of counter 113 increases, and as long as the push button - is pressed said output decreases. This occurs up to the value 7 (or down to zero) if a direct selection is carried out (as in case II, correction of tuning); and if an indirect selection is effected (as in case V, automatic rescan), the output of counter 113 will, instead, continue to cyclically vary from 0 to 9 in one or the other direction as long as one maintains the push button + or - pressed.
Therefore, with the circuit arrangement according to the present invention, it is possible to have: a direct station selection by selecting a channel with two digits of control panel 101 and with eventual correction of tuning, as per case (II); a storing of a selected channel, as per case (III); and an indirect station selection, either by selecting a desired cell of memory 108, as per case (IV), or by sequentially scanning the cells of memory 108, as per case (V).

INDESIT TYPE TC26SI  CHASSIS VV708 490-141-M  Control circuit:
 A circuit device for a television receiver having a tuner device with a tuner memory operable to control the tuning of the receiver to stations selected by a user, in which there are further provided means for automatically adjusting the controls of the receiver whenever the station to which the receiver is tuned is changed, this means comprising one or a plurality of random access memories addressed by signals from the tuner memory which are characteristic of each individual station, the output signal from the RAM, (or the enabled RAM if there are a plurality of them) representing the contents thereof at the location addressed, is fed to a digital-to-analogue converter which produces an output voltage signal for adjusting the associated receiver control; changes to the content of the RAM can be made by means of an associated counter controlled to count up or down by a push button panel.

 1. In a circuit device for carrying out and memorising adjustments to the tuning of a television receiver for a plurality of transmitter stations, of the type incorporating tuner memory means for memorising the value of control signals determining the tuning of the receiver,
the improvement wherein:
said tuner memory means are also operable to produce an output signal characteristic of the station to which the receiver is tuned,

there are provided further memory means and
there are further provided means for feeding said output signal from said tuner memory means which is characteristic of the station to which the receiver is tuned as an address signal to said further memory means,
said further memory means storing signals determining the adjustment to at least one of the controls of said receiver other than the tuning control for every station to which the receiver can be tuned,
means for effecting adjustment of this control of said receiver automatically in dependence on said stored signals in said further memory means when the tuning of said receiver is changed to select a different station, and
means for selectively changing the signals stored at any one address in said further memory means whereby to change the adjustment to said one control of said television receiver in respect of any one station.


2. The circuit device of claim 1, wherein said further memory means has a plurality of sets of address locations containing information on the adjustment of a plurality of the controls of said television receiver, and there are provided means for adjusting each of these controls automatically in dependence on the value of the signals stored in the said further memory means upon each change of tuning of said receiver from one station to another.


3. The circuit device of claim 1, wherein said further memory means and said tuner memory means are formed as parts of a common memory device.

4. The circuit device of claim 1, wherein said means for adjusting the associated control of the receiver in dependence on the contents of said further memory means includes a digital-to-analogue coverter to the output of said further memory means, said digital-to-analogue converter generating a voltage signal for adjustment of said associated control of said receiver.

5. The circuit device of claim 1, wherein said further memory means comprise at least one RAM memory in non volatile NMOS technology.

6. The circuit device of claim 1, wherein said further memory means comprise at least one MOS random access memory.

7. The circuit device of claim 6, wherein said at least one RAM memory has a voltage supply from a cell battery independent from the main voltage supply to said receiver.

8. The circuit device of claim 1, wherein said means for selectively changing the signals stored at any one address in said further memory means comprise: processor means, and
selector means operable to produce output signals which are fed to said processor means, the output signals from said processor means comprising digital control signals for feeding to said further memory means at an address determined at any one time by said characteristic output signal from said tuner memory means.


9. The circuit device of claim 8, wherein said further memory means comprises an individual memory device for each control of said receiver to be adjusted by said device, and there is provided a respective counter at the input of each said memory device, and a respective analogue-to-digital converter at the output of each said memory device.

10. The circuit device of claim 8, wherein said processing means comprise a single counter to the output of which are connected switching means operable to connect this output to any one of a plurality of said further memory devices in dependence on which of said buttons of said control panel are depressed.

11. The circuit device of claim 8, wherein said selector means comprise a push-button control panel having a pair of push-buttons for each said receiver control to be adjusted by said device.

12. The circuit device of claim 11, wherein said processor means comprise at least one pre-settable up/down counter which counts up or down in dependence on which button of said panel is depressed.

13. The circuit device of claim 12, wherein the counting of said at least one counter is controlled by an oscillator circuit.

14. The circuit device of claim 12, wherein the output of said at least one counter is connected to the input of said further memory means and there are provided means for setting said further memory means into a "write" mode upon depression of one of the push buttons of the said push-button control panel.

15. The circuit device of claim 12, wherein the output of said further memory means is connected to the pre-set input of said at least one associated counter.

Description:

BACKGROUND OF THE INVENTION
The present invention relates to a circuit device for effecting and memorising adjustments to the setting of the controls of a television signal receiver, especially of a colour television receiver; such controls as the volume, brightness, contrast, colour saturation etc. must often be adjusted when changing stations in order to obtain optimum setting of the controls for each station to which the receiver can be tuned in order to account for differences in the signals from each station. Conventionally, television controls are mechanical control systems using potentiometers inserted into the path of the electric signal to be controlled (direct control) or else supplying a D.C. voltage by means of which electronic voltage control is effected (indirect control).
Such mechanical systems have considerable disadvantages, not only from the point of view of durability, since the potentiometers, being mechanical, are subject to wear, but also from that of performance due to non-linearity and discontinuity in the response. Moreover, such mechanical systems are not easily adaptable to the use of remote controls.
For this reason wholly electronic control systems, which operate indirectly, have been recently introduced. These usually comprise a series of counters which are able to count both up and down, each followed by a suitable digital-to-analogue converter. By energising a counter, selected by operation of one of a number of pairs of push buttons, it is possible to increase or reduce the content of this counter and thereby to cause the corresponding control voltage to vary: such variation is discontinuous, but has sufficient resolution for most purposes.
This latter system eliminates many of the disadvantages of the conventional mechanical controls but it is still not wholly satisfactory because, since each station to which a receiver can be tuned usually has modulation characteristics which are different from those of the others, with every change of station it is necessary to readjust, systematically, the controls of the receiver, that is the volume, brightness, contrast (and colour controls in the case of colour transmission).
In fact at present it is possible in many places to receive a large number of transmitter stations (in some cases more than twenty), and hence television receivers have to allow changeover from one station to another with the greatest simplicity. The technical problem which this invention seeks to solve is the provision of a circuit device which is able to effect adjustment of the controls of a receiver upon changes in the tuning thereof to receive signals from different transmitters, which does not suffer from the disadvantages of known systems.

SUMMARY OF THE INVENTION
According to the present invention there is provided a circuit device for carrying out and memorising adjustments to the tuning of a television receiver for a plurality of transmitter stations, of the type having memory means for memorising the value of control signals determining the tuning of the receiver, in which the said memory means are also operable to produce an output signal characteristic of the station to which the receiver is tuned, and there are means for feeding this signal as an address signal to further memory means in which are stored signals determining the adjustment to at least one of the controls of the receiver, other than the tuning control, means for effecting adjustment of this control automatically in dependence on the said stored signals when the tuning of the receiver is changed to select a different station, and means for selectively changing the signal stored at any one address in the said further memory means whereby to change the adjustment to the said one control of the television receiver.

BRIEF DESCRIPTION OF THE DRAWINGS
Two embodiments of the invention will now be more particularly described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 is a schematic electrical diagram of an adjustment and memorisation circuit for the controls of a television receiver, constructed and arranged as a first embodiment of the present invention;
FIG. 2 is a schematic electrical diagram of a second embodiment of the present invention, which is somewhat simpler than the circuit shown in FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION
Referring now to FIG. 1 of the drawings there is shown a control panel 1 which is provided with six adjustment buttons or keys 2, 3, 4, 5, 6, 7. The buttons or keys 2, 4, 6, are connected each to a first input of respective OR gates 8, 9, 10, to respective inputs of a six input OR gate 11, and each to an UP/DOWN input (which controls the counting direction) of a respective one of three counters 16, 17 and 18. The buttons 3, 5, 7 are connected, respectively, to the second inputs of the OR gates 8, 9, 10 and to the remaining three inputs of the OR gate 11.
The output of the OR gate 11 is connected to a first input of an AND gate 12 and, through a differentiator circuit comprising a capacitor 13 which is earthed via a resistance 14, to the reset inputs (R) of the three counters 16, 17, 18; the second input of the AND gate 12 is fed with a signal from a clock generator 15, and the output of the AND gate 12 is connected to the clock inputs (CP) of the three counters 16, 17, 18. The outputs of the three counters 16, 17, 18 are connected, selectively by means of respective switch circuits 19, 20, 21, to the input/output terminals of three random access memories 22, 23, 24 and at the same time to the inputs of three digital-to-analogue converters 25, 26, 27 and, also at the same time to the preset inputs (PS) of the said three counters 16, 17, 18. The outputs of the three OR gates 8, 9, 10, are connected via respective delay circuits 28, 29, 30, to the "enable" inputs (CE) of respective switch circuits 19, 20, 21 and at the same time to the read-write (R/W) inputs of the random access memories 22, 23, 24. Address signals are fed to the three RAMs 22, 23, 24 from a terminal N fed from the output of a tuning control memory 49 having also an input/output line fed from a processor circuit 48 which receives control signals from a tuning control panel 47 having a plurality of push buttons or keys 47a selectively operable to choose the station to which the receiver is to be tuned. The terminal N line of the memory 49 also feeds a tuning control circuit 50 incorporating a digital-to-analogue converter and operating in a known way to control tuning of the receiver in dependence on the station selected. This system operates in a known way and does not form part of the inventive concept of the present invention, and therefore will not be further described.
The outputs of the digital-to-analogue converters 25, 26, 27, indicated by V, L and S, supply the adjustment voltages for the volume, brightness and colour controls.
The circuit described above operates as follows:
When any receivable transmitter station is selected by operation of the station selector panel 47 of the television receiver, there is applied to the input N, by the memory 49 associated therewith, a binary signal representing the selected transmitter station: this binary signal addresses the three random access memories 22, 23, 24 so that at the output thereof there is reproduced the information at present stored in those cells of the memories associated with that transmitter station, which represents the levels of the adjustment signals which were selected on a previous occasion when the receiver was tuned to that transmitter station.
The pairs of buttons 2, 3; 4, 5; and 6, 7 may be used to adjust any three of the controls of the receiver: in this example the controls to be adjusted thereby are the volume, brightness and colour saturation respectively, although they may be connected to control contrast or fine tuning of the receiver instead. The buttons 2, 4 and 6 select adjustment of the associated control in one direction, for example increasing volume, increasing brightness and increasing colour saturation, and the buttons 3, 5 and 7 select adjustment in the opposite direction, decreasing the volume, brightness or colour saturation respectively.
Upon depression, for example, of the key 2 a rest impulse is applied, through the gate 11 and the differentiator circuit comprising the capacitor 13 and resistor 14, to each of the three counters 16, 17, 18 which are then predisposed to count, starting from respective numbers which are preset, at the PS inputs thereof, from the outputs of the respective memories 22, 23, 24. The output signal from the gate 11 also enables the gate 12 to pass the clock pulses, generated by the generator 15, to the clock inputs of the three counters.
Depression of the key 2 also feeds a signal to the OR gate 8 which thus provides an output signal which, after a time delay T introduced by the delay circuit 28, sets the memory 22 to the write mode and opens the switch circuit 19 to pass on signals received from the counter 16 to the memory 22, which records them. The counters 16, 17 and 18 are predisposed to count DOWN and depression of the key 2 passes a signal to the U/D input of the counter 16 to set this in the count UP mode. When the counter 16 receives the preset signal from the RAM 22 it then starts to count up, and this is recorded simultaneously, in that cell of the memory 22 at the address, corresponding to the selected station, determined by the address signal on the input N, and the D/A converter 25 therefore supplies an increasing voltage which causes the volume to increase until the key 2 is released. During this operation, since none of the keys 4, 5, 6 or 7 have been depressed, the gates 9 and 10 have given no signal, and the content of the memories 23 and 24 has not changed.
Upon depressing the key 3, operation of the circuit is identical to that described above, except that no signal is fed to the U/D input of the counter 16 and hence the counter stays set to count down; there is thus produced a reduction in the content of the RAM 22 at the selected address with a corresponding reduction of the output voltage V, and hence a reduction in the volume of the receiver until the key 3 is released.
The pairs of keys 4, 5 and 6, 7 operate in exactly the same way to control, respectively, the counters 17 and 18 and thus the content of the memories 23 and 24. In the absence of any adjusting control effected by depression of the keys of the control panel 1 the digital-to-analogue converters 25, 26, 27 are fed with signals representing the content of the random access memories at the addresses determined by the signal at the input N and the receiver controls remain set at values determined by these.
In the embodiment of FIG. 2, components fulfilling the same function as corresponding components in the embodiment of FIG. 1 are indicated with the same reference numerals.
The UP keys 2, 4 and 6 of the control panel 1 are connected to respective inputs of an OR gate 42, the output of which is connected to a first input of another OR gate 43 and to the counting direction control input (U/D) of a counter 37; the DOWN keys 3, 5 and 7 are connected to respective inputs of an OR gate 41, the output of which is fed to a second input of the OR gate 43 the output of which is connected to an input of the gate 12 and to the capacitor 13 of the differentiator circuit including the earthed resistor 14.
The output of the OR gates 8, 9, 10 are connected to the enabling inputs (C.E.) of respective switching circuits 19, 20, 21, and via respective delay circuits 44, 45, 46, to the read-write inputs (R/W) of respective random access memories 22, 23, 24 and to respective inputs of an OR gate 47 the output of which is fed to the enable input (CE) of a switching circuit 38.
The clock input of the counter 37 is connected to the output of the gate 12, the reset input is connected to the capacitor 13, the preset input is connected to the three switching circuits 19, 21, 21, and the output is connected to the input of the switching circuit 38 the output of which is fed back to the preset input of the counter 37 and is connected to the three switching circuits 19, 20, 21.
The circuit described with reference to FIG. 2 operates as follows:
By depressing one of the keys 2, 4 or 6 the counter 37 is preset, via the gate 42, to count upwards, and via the gate 43 the passage of clock signals through the gate 12 is enabled. At the same time the associated one of the gates 8, 9 or 10 produces an output signal which enables the associated one of the switching circuits 19, 20 or 21 to pass signals fed to it. The output signal from the said one of the gates 8, 9 or 10, after a delay T introduced by the associated delay circuit 44, 45 or 46 is fed to the read/write input of the associated one of the random access memories which is thereby set to write; at the same, delayed, time the switching circuit 38 is enabled.
Meanwhile the signal from the gate 43 has supplied a reset impulse to the counter 37 which then starts to count, from the preset content of the memory 22, 23 or 24, when this arrives.
As in the embodiment of FIG. 1, the content of the memory 22, 23 or 24, at the address determined by the signal at the input N is altered, and hence the corresponding output voltage increases, and continues to increase until the key is released.
By pressing the keys 3, 5 or 7 the same operation is produced, but without energisation of the U/D input of the counter which thus counts down from the number preset by the content of the associated RAM at the selected address, whereby to reduce the controlled parameter.
The counters 16, 17, 18 of FIG. 1, and the counter 37 of FIG. 2 are all identical with each other and are of the six bit output type. Likewise the memories 22, 23 and 24 and the converters 25, 26, 27 are also of the six bit type. Moreover the above mentioned counters are so constructed and arranged that counting ceases as soon as a maximum value of 63 or a minimum value of 0 is reached.
From the above description the advantages of the device of the present invention will be clearly appreciated. By operation of this circuit it is possible to associated, with every transmitter station which can be received by a receiver, the selected best setting of the receiver controls, so that it is not necessary to readjust the controls upon each change of station in order to obtain optimum reception. Moreover it is very simple, if necessary, to alter the previous adjustments for any given station should reception conditions change, and the new values will automatically be memorised and used each time the receiver is tuned to that station unless and until the adjusted values are again changed.
Naturally, in order to retain the information when the receiver is switched off the memories 22, 23, 24 have to be of the non-volatile type, or else of the low consumption type (MOS) in order thay they may be supplied by a separate voltage source, such as a dry cell, when the main voltage source is disconnected.
Many variations are possible without nevertheless going beyond the scope of the present invention. For example, the control board need not be directly connected to the rest of the circuit as shown in the above examples, but may be connected by a remote control system, for example using infra red rays; moreover the circuit may be modified so that the counters are caused to move gradually at each pressure from a control key or button so that greater precision of adjustment is obtained. Likewise, although the RAM memories 22, 23, 24 and the tuning memory 47 are shown as independent memories, they may be formed as parts of a single common memory device.