This version of the PHILIPS K12 is introducing the TRD TUNING SYSTEM (TUNING REMOTE DIGITAL) WHICH allows direct selection of channel frequency on front keyboard or even via remote through a help of a Ucontroller which sends command to the TRD Units system.
Furthermore it has a programmable realtime digital clock which allows to start the tellye at a prefixed time on a prefixed program.
This chassis is even showing the use of the TEXAS INSTRUMENTS TMS1000 used here as a Remote control decoder /receiver plus realtime programmable clock timer feature.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Texas Instruments TMS1000
General
General Information
Texas Instruments was locked in a race with Intel to create the first microprocessor. By most accounts Intel won with the 4004, but there are a few die hard TI fans who say the TMS1000 was first, because it was the first “computer on a chip” and that the 4004 was just a calculator chip.
Texas Instruments followed the Intel 8080 with the 4-bit TMS1000. So, while Intel was leading the industry in microprocessors, TI led with this industry unique design "a computer on a chip", specifically designed for control and automation purposes. The 1000 was the first MCU (MicroComputer Unit) , which is an MPU (MicroProcessor Unit) with other support chips (such as RAM, ROM, counters, timers, I/O interfaces) integrated on to the same silicon chip.
The original 1000 family consists of 6 chips the TMS1000 and TMS1200 are basic chips, the TMS1070 and TMS1270 are high voltage versions to interface to displays, the TMS1100 and TMS1300 provide twice the on-board ROM and RAM. The TMS1000, TMS1070, and TMS1100 are 28-lead packages, the TMS1200, TMS1270, and TMS1300 are 40-lead versions of the same chips (just 200 to the 28-lead chip numbers).
In the 80's TI added to the 1000 family. The 28-lead TMS1170 started with a TMS1100 base and added fluorescent display drive capability and expanded memory (2KB ROM). The TMS1370 was the same as the TMS1170 and added 27 I/O lines. An expanded memory group based on the original TMS1000 chips was also created. They were the TMS1400, TMS1470, and TMS1700 (64 Bytes RAM, 4KB ROM). There were 40-lead versions of the TMS1400 and TMS1470, which because the TMS1600 and TMS1670. CMOS versions were also added, denoted with a "C" suffix, such as TMS1200C.
The TMS1000 also had system evaluator chips. The original evaluator chips were the TMS1098 and TMS1099. These 64-lead evaluator chips were ROM-less versions of their corresponding standard chips. The TMS1099 supported the TMS1000/TMS1200 and the TMS1070/1270. The TMS1098 supported the TMS1100/1300. Later evaluators were introduced to support the entire TMS1000 family, they were the SE1000P (supports TMS1000,1070,1200,1700), SE2200P (supports TMS1100,1170,1300,1370), and the SE1400P (supports 1400, 1470, 1600, 1670).
The success of the the TMS1000 is demonstrated by its long lifecycle (over 20 years) and its expanded product line. The TMS1000 is found in many appliances, control systems, and games. Most of these chips were sourced by companies for direct use in their products and will have custom or house numbers on the chips (not the standard numbers listed above). Even TI used custom numbers in its products.
The PHILIPS CHASSIS K12 WAS the first PHILIPS monocarrier type. Previous K11 was a dual panel development type.
The PHILIPS chassis K12 doesn't share technology from previous CHASSIS K11 except for the 20AX SYSTEM CRT TUBE.
The chassis is a pretty unique type because it was introducing improvements and technology philosophy kindly singular and unique in it's fashion.
From signal processing to Video Matrixing to power supply technology and many further aspects this chassis was a reference to understand PHILIPS development flexibility.
This chassis has known many further versioning and enhancements even in more sophisticated and complex types with different CRT TUBE like the PHILIPS 30AX FAMILY.
Modularity is the main concept of construction but some Units like the E/W and FRAME UNIT gave problems in the insertion slot which often was burning the contacts producing several faults.
The solution was simple: A complete hardening with soldering and reworking of the enpoints of the Units contacts was a definitive solution for long time. But when the damage was more extended the only solution was to direct wire all contacts from Unit to chassis !
Line Deflection + EHT, Line synchronized Supply, EW Correction + Supply, Frame Deflection, Signal Section Parts.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Channel selector having a plurality of tuning systems:A channel selector characterized in that a plurality of receivers capable of simultaneously performing a receiving operation have a main part of a phase-locked loop frequency synthesizer connected in common thereto, the frequency synthesizer having a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. The frequency synthesizer is controlled so that a local oscillation frequency corresponding to a determined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes the broadcast signal from the local oscillation frequency.
1. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said plurality of receivers has its own low pass filter included in its equivalent phase-locked loop frequency synthesizer, and an output of a phase comparator is switched to an input terminal of one low pass filter from among said plurality of low pass filters by a 3-state switching circuit.
2. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
3. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
4. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
5. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said equivalent phase-locked loop frequency synthesizers is controlled so that a local oscillation frequency corresponding to a predetermined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes said broadcast signal from said local oscillation frequency whereby said broadcast signal of said desired receiving channel is tuned.
6. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said phase-locked loop frequency synthesizers selects a desired receiving channel, and wherein a tuning voltage of said desired receiving channel is stored in a voltage memory means, and wherein said channel selector further comprises a tuning means provided for each of said plurality of receivers so that while receiving, said tuning means tunes in accordance with the output of said voltage memory means.
7. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
8. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
9. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
This invention relates to a channel selector for use in television receivers, FM (frequency modulation) radio receivers, AM (amplitude modulation) radio receivers and so on.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:
Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
A stabilized supply voltage circuit for a picture display device comprising a chopper wherein the switching signal has the line frequency and is duration-modulated. The coil of the chopper constitutes the primary winding of a transformer a secondary winding of which drives the line output transistor so that the switching transistor of the chopper also functions as a driver for the line output stage. The oscillator generating the switching signal may be the line oscillator. In a special embodiment the driver and line output transistor conduct simultaneously and in order to limit the base current of the line output transistor a coil shunted by a diode is incorporated in the drive line of the line output transistor. Other secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode of the chopper so as to generate further stabilized supply voltages.
1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4. A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.
Description:
The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.
Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the
literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply
voltage device.
In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.
It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.
The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.
The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V 0 . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.
In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.
In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.
This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.
The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V i - V o = 0.5 V i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.
In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.
The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.
Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.
Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.
As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
PHILIPS CHASSIS K12 HIGH-VOLTAGE GENERATING DEVICE / TRANSFORMER:
A high-voltage generating device which comprises a transformer having a secondary coil subdivided into sections which are series-connected via diodes. The beginning of the first section is connected to a point of fixed potential via a further diode. The beginning and the end of the first section are also connected to this fixed potential point via first and second capacitors, respectively. As a result, a tapping lead connected, for example, to the beginning of the second section provides a voltage of from one to two times the voltage difference across a section, as desired.
Inventors: Tol, Franciscus (Eindhoven, NL) Baggermans, Albertus B. A. (Eindhoven, NL) U.S. Philips Corporation (New York, NY)
1. A high-voltage generating device comprising, a transformer having a primary coil and a secondary coil which is divided into a plurality of sections, a plurality of diodes, means connecting the end of each section, except for the end of the last section, to the anode of a diode, the cathode of which is connected to the beginning of the next section, means connecting the end of the last section to the anode of a diode whose cathode is connected to a high-voltage lead, means connecting the cathode of at least one of the other diodes to a tapping lead, means connecting the beginning of the first section to the cathode of a diode whose anode is connected to a point of fixed potential, and means connecting the beginning and the end of the first section to the point of fixed potential via first and second capacitors, respectively.
2. A high-voltage generating device comprising, a transformer having a primary winding and a secondary winding with the secondary winding divided into a plurality of winding sections, a plurality of diodes, a high-voltage output terminal, means connecting said plurality of sections in series with said plurality of diodes between said output terminal and a point of fixed potential with each section coupled to the next section by a diode and with a first diode connecting the beginning of the first section to said point of fixed potential and a second diode connecting the end of the last section to said output terminal, first and second capacitors, means coupling the beginning and end of the first section to said point of fixed potential via said first and second capacitors respectively, and means for coupling the beginning of at least one other section to a further output terminal to supply a voltage of an amplitude determined in part by said capacitors.
3. A device as claimed in claim 2 wherein said first and second capacitors have equal capacitance values.
4. A device as claimed in claim 2 wherein said first and second capacitors have unequal capacitance values.
5. A device as claimed in claim 2 wherein said further output terminal is coupled to the beginning of the second section and wherein the voltage supplied by said further output terminal can be adjusted to a value between one and two times the voltage across a section by the choice of the relative capacitance values of said first and second capacitors.
6. A device as claimed in claims 2, 3 or 4 wherein the end of at least one winding section is directly connected to the beginning of the next winding section via said diode.
7. A device as claimed in claims 2 or 5 wherein said transformer comprises the horizontal deflection transformer of a television receiver, said output terminal supplying the high-voltage for the television receiver cathode ray tube and said further output terminal supplying the focus voltage for the cathode ray tube.
Description:
The invention relates to a high-voltage generating device, notably for a television picture tube, comprising a transformer with a secondary coil which is divided into a number of sections. The end of each section, except for the end of the last section, is connected to the anode of a diode, the cathode of each diode is connected to the beginning of the next section, but the end of the last section is connected to the anode of a diode whose cathode is connected to a high-voltage lead, the cathode of at least one of the other diodes also is connected to a tapping lead.
A device of this kind is known from the magazine "Funkschau" 1976, Heft 24, pages 1051-1054.
For example, the focus voltage for a picture tube is derived from the
tapping lead. The voltage at the area of this tapping depends on the
number of sections and on the value of the high voltage. When a higher
voltage is required, the tapping lead must be connected behind the next
section on the secondary winding. In many cases, however, the voltage
which is tapped off behind, for example, the first section is just too
low, whereas that tapped off behind the second section is much too high.
An object of the invention is to enable a direct voltage to be tapped off behind the first section which amounts to from one to two times the voltage difference between the beginning and the end of this section.
To this end, the device in accordance with the invention is characterized in that the beginning of the first section is connected to the cathode of a diode whose anode is connected to a point carrying a fixed potential, the beginning and the end of the first section also being connected, via capacitors, to the point carrying the fixed potential.
By a suitable choice of the capacitance of the two capacitors, any voltage between one and two times the voltage across a section can be tapped off at the beginning of the second section.
It is to be noted that a transformer whose secondary winding is formed by a number of sections which are connected in series via diodes, the beginning of the first section also being connected to the cathode of a diode, is known per se from U.S. Pat. No. 4,091,349. However, in this transformer none of the intermediate diodes is connected to a tapping lead and the ends of the first section are not connected to capacitors either.
The invention will be described in detail hereinafter with reference to the accompanying diagrammatic drawing in which:
FIG. 1 shows a diagram of a known high-voltage generating device,
FIG. 2 is a diagram of the voltage present at a number of locations in the device shown in FIG. 1 at a given instant,
FIG. 3 shows a diagram of an embodiment of the device in accordance with the invention,
FIG. 4 is a diagram of the voltage present at a number of locations in the device shown in FIG. 3 at a given instant,
FIG. 5 is a diagram which represents the variation with time of the voltage in a number of locations in the device shown in FIG. 3, and
FIG. 6 shows a diagram to illustrate the voltage variation wih time at a location in various versions of the device shown in FIG. 3.
FIG.1 shows a known high-voltage generating device, comprising a transformer 1 with a primary coil 3 to which a pulse-shaped voltage is applied, for example, a line output transformer in a colour television receiver. The secondary coil is subdivided into four sections 5, 7, 9 and 11, the end of each of the first three sections 5, 7, 9 being connected to the anode of a diode 13,15, 17, respectively, the cathode thereof being connected to the beginning of the next section. The end of the last section 11 is connected to the anode of a diode 19, the cathode of which is connected to a high voltage lead 21 which is connected, for example, to the high voltage connection of a picture tube (not shown). The cathode of the first diode 13 is also connected to a tapping lead 23 wherefrom, for example, the focus voltage for said picture tube can be derived. The beginning of the first section 5 is connected, via a connection lead 25, to a point which carries a fixed potential.
FIG. 2 illustrates the voltage variation in each section, the number of turns n being plotted horizontally and the voltage V being plotted vertically. Each section consists of N turns in which voltage pulses 27 are induced. At the beginning of the first section 5, which is connected to a point carrying a fixed potential, the magnitude of the voltage pulses is zero and at the end of the turn N it is maximum and equal to U volts. The envelope 29 of the voltage pulses 27 is a straight line. Due to the strong capacitive coupling between the sections, no alternating voltages occur between corresponding turns of successive sections, so that the voltage pulses in the second section 7 vary across the section in the same manner as the pulses in the first section 5. The beginning of this second section thus carries a direct voltage U (due to the rectification of the voltage across the first section) and a pulse voltage zero, while the end of this section carries a pulse voltage of the magnitude U which is superposed on the direct voltage U. The same is applicable to the subsequent sections so that the voltage at the end of the fourth section 11 amounts to 4 U. It will be clear that the tapping lead 23 carries a voltage U.
FIG. 3 diagrammatically shows an embodiment of a device of the described kind which has been improved in accordance with the invention. Corresponding parts of the device are denoted by the same reference numerals as in FIG. 1. The difference with respect to FIG. 1 consists in that the beginning of the first section 5 is connected, by means of the connection lead 25, to the cathode of a diode 31 whose anode is connected to a point carrying a fixed potential, and in that at the beginning of the first section there is connected a first capacitor 43, a second capacitor 45 being connected to the end thereof, said capacitors also being connected to the point carrying a fixed potential.
If the capacitances of these capacitors are equal, their combined effect corresponds to that of a capacitor 33 which connects the centre of the section to a point carrying a fixed potential (denoted by a broken line).
The result of these steps is shown in FIG. 4 which shows, like FIG. 2, the voltage variation in the various sections. Thanks to the diode 31 and the effective capacitance 33, no longer the beginning but the centre of the first section 5 is maintained at a fixed potential for alternating voltages. As a result, the voltage pulses 35 induced in this section equal zero at the area of the central turn N/2 and are oppositely directed at the two ends of the section: thus
-U/2 at the beginning and +U/2 at the end. The capacitance 33 is charged so far that the diode 31 just becomes a conductive for each pulse, that is to say to a voltage +U/2 with respect to the point of fixed potential to which the anode of this diode is connected. The first section thus carries a mean voltage +U/2 on which there are superposed voltage pulses of the magnitude -U/2 at the beginning and +U/2 at the end of the section. This is shown in FIG. 5 in which the curve 37 represents the voltage variation as a function of the time at the beginning of the section. The curve 39 represents the voltage variation at the end of the section.
Due to the capacitive coupling between the first section 5 and the second section 7, corresponding turns of these two sections do not carry an alternating voltage with respect to each other, so that the voltage variation at the beginning of the second section corresponds to that of the first section, the mean voltage level, of course, being higher by the amount of te rectified voltage across the first section, so U volts. This is represented by the curve 41 in FIG. 5. It follows that the mean voltage on the tapping lead 23 equals 3 U/2 volts. This voltage is a direct voltage on which voltage pulses of -U/2 volts are superposed. If desired, these superposed voltage pulses can be eliminated by an RC network (not shown) connected to the tapping lead. Thus, a voltage is obtained on the tapping lead which is one and a half times that of the device shown in FIG. 1.
As has already been stated, it has been assumed that the capacitances of the capacitors 43, 45 are equal, so that the overall effect thereof can be represented by a capacitor 33 connected to the central turn. However, the voltage carried by the tapping lead 23 can be influenced by choosing these capacitances to be different.
When the values of the capacitors 43 and 45 are not the same, their combined effect corresponds to that of a capacitor 33 which is connected to a turn other than the central turn. The point in the section where the induced voltage pulses have the value zero is shifted accordingly across the section. When the capacitance of the first capacitor 43 is larger than that of the second capacitor 45, this point is situated nearer to the beginning of the section and vice versa. In extreme cases, this point may be situated at the beginning or at the end of the section. This means that the mean voltage level of the first section can vary from 0 to U volts. The direct voltage level of the curve 41 in FIG. 5 can vary accordingly from U to 2 U volts, the peaks of the negative pulses, of course, always reaching the level of the rectified voltage across the first section (U volts).
This is shown in FIG. 6 for a number of cases. The curve 41 in this Figure is identical to the curve 41 in FIG. 5
and relates to the symmetrical condition in which the capacitances of the capacitors 43 and 45 are equal. The curve 47 is obtained when the capacitance of the capacitor 43 (referred to hereinafter as C43) exceeds that of the capacitor 45 (referred to hereinafter as C45), so C43>C45. Curve 49 is obtained when C43<C45. Curve 51 represents an extreme situation where C43 is so large that the diode 31 is actually short-circuited for alternating voltages. This corresponds to the situation shown in FIG. 1. Finally, curve 53 represents the other extreme situation where C45 is so large that C43 can be neglected.
The foregoing demonstrates that the voltage at the tapping lead 23 can be adjusted between U and 2 U Volts by the choice of C43 and C45. The capacitors 43, 45 may consist of discrete components, but they may alternatively be formed during the winding of the section by using an adapted winding technique.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I
PHILIPS TRD (Tuning Remote Digital) Search type tuning system Chassis K12i:Dics-Digital Tuning System For TV Receivers" by N.V. Philips' Gloeilampenfabrieken, Netherlands, 2/1977
Walker, "For TV Tuners a Digital Look", Electronics, Jun. 26, 1975, pp. 65-66.
Evans et al., "Direct Address Television Tuning and Display System Using Digital MOS Large Scale Integration", IEEE Transactions on Consumer Electronics, vol. CE-22, No. 4, pp. 267-288, Nov. 1976.
Electronics, vol. 48, No. 24, Nov. 27, 1975, "Philips TV Set Indicates Station Tuning and Color Settings on Screen", pp. 6E and 8E.
Werner, "Linear Color Bar Display for CTV Sets", Radio Mentor Electronic, vol. 41, No. 9, pp. 350-351, Sep. 1975.
A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past thosechannels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning systemfor a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control)detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.
Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuningsystems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.
Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptablereception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.
The present invention relates to a television set which includes a picture display device, an alpha numerical character generating circuit connected to the said device, a control device and means for checking analogue data relating to the operation of the set, such as volume, brightness and color. The system commonly used on television receivers for tuning into the required channels is the so-called FREQUENCY SYNTHESIZER system. This system, made possible by the advent of integrated circuits, offers a number of advantages over other known systems, such as the conventional potentiometer type MECHANICAL MEMORY systems and the more recent so-called VOLTAGE SYNTHESIZER systems. The frequency synthesizer system is fully electronic enabling any channel to be called up directly by the user who formulates the channel number on a keyboard or other control device. The system usually consists of a quartz-controlled reference oscillator, a phase lock loop, a programmable divider and a computer which supplies the number to be sent to the programmable divider in response to the number of the channel set by the user. Thanks to the phase lock loop, for each channel number set by the user, the frequency of the local oscillator on the set is kept so stable and accurate that the set is tuned with great precision to the corresponding channel signal. For further details concerning frequency synthesizer tuning systems, refer to the article entitled "A Frequency Synthesizer for Television Receivers" by E. G. Breeze, published in the November, 1974 issue of the "Transactions BTR" Magazine, or "Digital Television Tuner Uses MOS LSI and Non Volatile Memory" by L. Penner, published in the April 1, 1976 issue of "Electronics".
Channel selection is controlled by a frequency synthesizer a sweep of available channels is made by a channel selecting arrangement and this sweep is arranged to be stopped when a signal is received. When the sweeping is stopped a fine tuning arrangement takes control to respond to the frequency of the received signal and to compensate for any drift of that signal.
According to this invention there is provided a receiver comprising frequency synthesizer controlled channel selection means which includes a fine tuning arrangement; means for initiating a sweep of available channels by the channel selection means; means for stopping the sweep on reception of a signal and means, operable on cessation of sweeping and responsive to the frequency of the signal, and arranged to control the fine tuning arrangement to compensate for frequency drift of the signal.
The receiver may be in the form of a television receiver.
The means operable a cessation of sweeping may comprise level detector means arranged to receive a signal whose level is representative of the frequency of the received signal and to provide an output signal when a predetermined frequency drift is detected.
In a preferred form two level comparators are provided each arranged to receive the frequency representative signal and a respective reference level and to provide an output respectively representative of an upward and downward frequency drift exceeding predetermined limits.
The signal whose level is representative of the frequency of the received signal may be provided by automatic frequency control (A.F.C.) means conveniently in the form of an A.F.C. discriminator.
The means operable or cessation of sweeping may be arranged to control the fine tuning arrangement via a signal path which includes means for blocking said signal path until the said signal is received.
The means for blocking may be in the form of gate means connected to the said signal path and arranged to receive a second input a signal indicative of the receipt of the said signal.
The means for initiating a sweep may comprise an operator control coupled to control input means of the channel selection means, and the means for stopping sweeping is operative to isolate the operator control from the said control input means.
The operator may be coupled to the channel selection means via gating means operative to open an operation of the operator control and the means for stopping sweeping may provide a signal operative to block the gating means or receipt of the said signal.
The means for stopping sweeping may include means for detecting the reception of the said signal which in a preferred form of television receiver comprises a sync comparator operative to compare video signals with line flyback signals and to provide an output signal whose level is indicitive of the reception of the said signal.
The frequency synthesizer system lends itself well to a number of different modes of television channel tuning;
direct selection by formulating the required channel number as described above television channels are numbered: for example, in the European C.C.I.R. standard, V.H.F. band channels are numbered from 2 to 12 and U.H.F. band channels from 21 to 69; in the American Standard, VHF channels are numbered from 2 to 13 and UHF from 14 to 83).
memory selection: each of a certain set of keys corresponds to a preselected and memorised channel;
automatic scanning of all the channels of a given standard, or of all the channels contained in the memory or continuous scanning of all the frequency bands involved.
The first application enables immediate, direct selection of any one of the channels in the relative standard (60 in Europe, 82 in America).
the second enables faster detection of one of a limited number of preferred channels.
The third is a fast, simple way of finding out which standard channels can be received, which channels have been memorised and whether other broadcasting stations exist on non-standard frequencies such as the private broadcasting stations in Italy (there are currently over a hundred operating).
A)- A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A first programmable frequency divider controlled by a reversible counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator, after passing through another programmable frequency divider, also is applied. The phase comparator output is a tuning voltage used to control the tuning of the local oscillator. A logic circuit is coupled to sense predetermined relationships of signals from a picture carrier detector, a sound carrier detector, an AFT discriminator circuit, and the presence of vertical synchronization signal components for changing the count in the reversible binary counter to adjust the first programmable frequency divider to compensate for channel frequency offsets which may occur in excess of the pull-in range of the AFT discriminator circuit. To permit operation of the
receiver as a signal seek receiver, a pair of signal seek pushbuttons for the "up" and for the "down" direction, respectively, are provided. Operation of either of these pushbuttons functions in conjunction with further logic circuitry and in conjunction with timing circuitry to automatically step tune the receiver channel-by-channel in the selected direction until a channel with a signal present is sensed by the first logic circuit, whereupon the signal seek circuit operation is disabled until one or the other of the signal seek pushbuttons is reactivated.
1. A frequency synthesizer signal seek tuning system for a tuner of a television receiver capable of receiving a composite television signal, said system including in combination:
reference oscillator means providing a reference signal at a predetermined frequency;
local oscillator means in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider having an input coupled to said reference oscillator means for producing an output signal having a frequency which is a programmable fraction of the frequency of the signal applied to the input thereto from saidreference oscillator means;
means coupled to the output of said programmable frequency divider and the output of said local oscillator means for developing a control signal and applying such control signal to said local oscillator means for controlling the frequency ofoperation thereof;
channel selection means coupled to said programmable frequency divider for establishing a predetermined initial programmable fraction therein each time a new channel is selected by said channel selection means;
control means coupled to the output of the tuner of the television receiver and further coupled to said programmable frequency divider for controlling said frequency divider to change the programmable fraction thereof in response to predeterminedconditions of the signals from the tuner; and
signal seek tuning means coupled to said channel selection means and said control means for causing said channel selection means to select a new channel in response to said predetermined conditions of the tuner signals persisting for a predetermined time period.
2. The combination according to claim 1, wherein the composite television signal has at least carrier signal components and synchronizing signal components and further including carrier sensing means coupled to receive at least the carriersignal components of the composite signal from the tuner and providing an output voltage indicative of the tuning of said receiver to a carrier component of said composite signal; and synchronizing signal component sensing means coupled to receive atleast said synchronizing signal components of the composite signal for providing a first predetermined output with synchronizing signal components sensed thereby; wherein said control means is coupled to the outputs of said carrier sensing means andsaid synchronizing signal components sensing means and further coupled to said programmable frequency divider means for changing the programmable fraction thereof in response to first predetermined conditions of signals at the outputs of said carriersensing means and said synchronizing signal components sensing means and the operation of said signal seek tuning means being terminated in response to second predetermined conditions of signals at the outputs of said carrier sensing means and saidsynchronizing signal components sensing means.
3. The combination according to claim 1, further including first and second switches in said signal seek tuning means for initiating a signal seek operation in the "up" and "down" directions, respectively, operation of one of said first andsecond switches causing said channel selection means to select the next channel in the selected direction and establishing said predetermined initial programmable fraction in said programmable frequency divider in response thereto.
4. The combination according to claim 3, wherein said control means terminates operation of said signal seek means in response to detection of second predetermined conditions of the signals from the tuner.
5. The combination according to claim 1, wherein said predetermined conditions of the tuner signals comprise first and second predetermined conditions, respectively; said programmable frequency divider has its input coupled to the output ofsaid reference oscillator means; and wherein said control means includes reversible digital counter means coupled to said programmable frequency divider, and logic circuit means coupled to the output of the tuner for causing said counter means to countin one direction when said first predetermined conditions exist and to count in the opposite direction when said second predetermined conditions exist.
6. The combination according to claim 5, further including additional means coupled to said counter means and coupled to said logic circuit means for inhibiting operation of said signal seek tuning means and for preventing a change in the countof said counter means when third predetermined signal conditions exist in the tuner output.
7. The combination according to claim 6, further including a second programmable frequency divider coupled to the output of said local oscillator means and producing an output signal having a frequency which is a programmable fraction of thefrequency of the signal applied to the input thereto from said local oscillator means; and wherein said channel selection means is further coupled to said second programmable frequency divider for controlling said second programmable frequency dividerto establish the programmable fraction thereof each time a new channel is selected by said channel selection means.
B)- A tuning system for a television receiver includes a local oscillator which is controlled first by a phase lock loop arrangement and then by an AFT discriminator arrangement for tuning the receiver to non-standard as well as standard frequency carriers. The phase lock loop arrangement includes a programmable divider for dividing the local oscillator frequency by a programmable factor corresponding to the presently selected channel. When the local oscillator is being controlled by the AFT discriminator arrangement, the count accumulated by the programmable divider during a reference interval determines how far the local oscillator frequency has drifted from its nominal value. If a predetermined frequency offset has been exceeded, control is returned to phase lock loop control and the programmable factor is incrementally changed.
1. In a system for tuning a television receiver to the various channels a viewer may select, apparatus comprising:
local oscillator means for generating a local oscillator signal;
counter means for generating a frequency divided signal by counting a predetermined number of periods of said local oscillator signal, said predetermined number being proportional to the frequency of said local oscillator signal;
means for generating a reference frequency signal;
phase control means for generating a control signal representing the phase and frequency deviation between said frequency divided signal and said reference frequency signal;
mode switching means for selectively coupling said control signal to said local oscillator means; said mode switching means initially coupling said control signal to said local oscillator means;
said local oscillator means changing the frequency of said local oscillator signal in response to said control signal until said frequency divided signal and said reference frequency signal to be in a predetermined phase and frequency relation;
said counter means accumulating a nominal number of counts during a predetermined portion of said frequency divided signal when said frequency divided signal and said reference signal are in said predetermined phase and frequency relationship;
means for generating a lock signal when said frequency divided signal and said reference frequency signal are in said predetermined phase and frequency relationship;
said mode switching means decoupling said control signal from said local oscillator means in response to said lock signal;
means for generating a count signal when said control signal is decoupled from said local oscillator means, said count signal having a duration with a predetermined time relationship to said reference frequency signal;
means responsive to said count signal for disabling said counter means from counting when said control signal is decoupled from said local oscillator means except during the duration of said count signal; and
means for generating an offset signal representing the deviation between the count accumulated by said counter means during a time interval corresponding to said predetermined portion of said frequency divided signal when said control signal isdecoupled from said local oscillator means and said nominal number of counts, said offset signal being coupled to said mode switching means to control the coupling of said control signal to said local oscillator means.
2. The apparatus recited in claim 1 wherein said means for generating said offset signal includes:
memory means for generating an output signal having a first amplitude when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;
means for resetting said memory means prior to the occurrence of said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillator means;
means for setting said memory means if the count accumulated by said counter during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillatormeans is less than said nominal number of counts by a first predetermined deviation; and
means for resetting said memory means if the count accumulated by said counter means during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said localoscillator means is greater than said nominal number of counts by a second predetermined deviation.
3. The apparatus recited in claim 1 wherein said counter means derives said frequency divided signal by counting a first number of periods during a first portion of said frequency divided signal and by counting a second number of periods duringa second portion of said frequency divided signal.
4. The apparatus recited in claim 3 wherein the various channels a viewer may select are partitioned into frequency bands, said first number is related to the channel selected by a viewer and said second number is related to the frequency bandin which the selected channel resides.
5. The apparatus recited in claim 4 wherein said predetermined portion is at least a part of said second portion.
6. The apparatus recited in claim 5 wherein said counter includes:
variable modulus frequency divider means for selectively dividing the frequency of said local oscillator signal by a first factor or a second factor, said first factor being related to the frequency spacing between channels in at least one ofsaid bands;
decade counter means for counting periods of the output signal of said variable modulus frequency divider;
channel number comparator means for generating a channel match signal when the number of periods counted by said decade counter means equals said first number, said decade counter means being reset in response to said channel match signal;
first factor stop comparator means for generating a first factor stop signal when the number of periods counted by said decade counter means equals a third number, said third number being also related to the band in which the selected channelresides but less than said second number, said variable modulus divider means being caused to divide by said second factor in response to said first factor stop signal; and
added count comparator means for generating an added count match signal when the number of periods counted by said decade counter means equals said second number, said decade counter means being reset in response to said added count match signal,said variable modulus divider means being caused to divide by said first factor in response to said added count match signal.
7. The apparatus recited in claim 6 wherein said nominal number of counts equals said second number.
8. The apparatus recited in claim 7 wherein said means for generating said offset signal includes means for resetting at least said decade counter means and for causing said variable modulus divider to divide by said first factor in response tothe initiation of said count signal.
9. The apparatus recited in claim 7 wherein said means for generating said offset signal includes:
memory means for generating an output signal when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;
means for resetting said memory means prior to the occurrence of said first factor stop signal during the duration of said count signal when said control signal is decoupled from said local oscillator;
means for inhibiting the generation of said added count signal when said control signal is decoupled from said local oscillator;
means for setting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is less than said second number by a first predetermineddeviation; and
means for resetting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is greater than said second number by a secondpredetermined deviation.
10. The apparatus recited in claim 9 wherein said means for generating said offset signal includes means for repetitively generating said offset signal.
11. The apparatus recited in claim 1 wherein said means for disabling said counter means includes input switching means for selectively decoupling said local oscillator signal from said counter means when said control signal is decoupled fromsaid local oscillator means except in response to said count signal; and
said counter means includes means for generating an illegal signal when an illegal channel has been selected;
said input switching means also decoupling said local oscillator signal from said counter means in response to said illegal signal.
12. The apparatus recited in claim 11 wherein:
said means for generating said illegal signal includes band selection means for generating a band traversed signal whenever the count accumulated by said counter corresponds to the boundary of a band and means for generating a band signalrepresenting the band in which the selected channel resides in accordance with which of said band traversed signals have been generated during said first portion of said frequency divided signal, said means for generating a band signal generating saidillegal signal when a band signal is not generated.
13. The apparatus recited in claim 11 wherein said means for generating said reference frequency also includes means for deriving a signal having a predetermined frequency; and said input means includes means for coupling said signal having apredetermined frequency to said counter means in response to said illegal signal.
Description: The present invention pertains to television tuning systems including a phase locked loop frequency synthesizerand particularly pertains to frequency counters which may be utilized in such systems.
In concurrently filed U.S. patent application Ser. No. 70,849, and now U.S. Pat. No. 4,031,549 by Henderson et al., assigned to the same assignee as the present invention, there is described a tuning device system for a television receiverwhich includes a phase locked loop for tuning a local oscilator to the nominal local oscillator frequencies required to tune the receiver to RF carriers at standard broadcast frequencies allocated to the various channels a viewer may select. The tuningsystem also includes an automatic fine tuning (AFT) frequency discriminator for tuning the local oscillator to minimize any deviation between the frequency of an actual picture carrier and the nominal picture carrier frequency. If the receiver iscoupled to a television distribution system which provides RF carriers having nonstandard frequencies arbitrarily near respective ones of the standard broadcast frequencies, when the phase locked loop has achieved lock at a nominal frequency, a modecontrol unit selectively couples the discriminator and a frequency drift control circuit to the local oscillator. If the frequency of the local oscillator drifts more than a predetermined offset from the frequency synthesized under phase locked loopcontrol because no carrier has been detected by the discriminator, discriminator and drift control are terminated so that the receiver will not be tuned to an undesired carrier such as, for example, the lower adjacent channel sound carrier, and phaselocked loop control is reinitiated to synthesize a local oscillator signal having a frequency incremented from the frequency of the originally synthesized local oscillator signal by a predetermined amount. After the phase locked loop is locked at anincremented frequency, discriminator control is again initiated. If, during this cycle of discriminator control, the local oscillator again drifts more than the predetermined offset from the incremented local oscillator frequency because no carrier isdetected by the discriminator, phase locked loop control is again reinitiated to synthesize a local oscillator signal having a frequency decremented from the frequency of the originally synthesized local oscillator signal by a predetermined amount. Ifduring any discriminator control cycle the local oscillator has not drifted further than the predetermined offset because the discriminator has tuned the local oscillator to a carrier within the predetermined offset, phase locked loop control is notreinitiated and the tuning sequence is complete.
In order to reduce the complexity, and therefore the cost, of an implementation of such a tuning system, it is desirable that individual potions of the system be capable of performing more than one function. For example, in copending UnitedStates Patent Application Ser. No. 663,097 filed for R. M. Rast on Feb. 27, 1976, and now U.S. Pat. No. 4,009,439 and assigned to the same assignee as the present invention, which is hereby incorporated by reference, there is described a frequencydivider for a television tuning phase locked loop tuning system. For each channel a viewer selects, the divider divides the frequency of the local oscillator signal by a number proportional to the nominal local oscillator frequency by forming a signalincluding first and second portions having durations respectively equal to first and second numbers of periods of the local oscillator signal. The first number is related to the selected channel number. The second number is related to the frequencyband in which the selected channel resides. To generate signals including in which band the selected channel resides for use in the phase locked loop itself and in the local oscillator to control its frequency range, a band selection unit is included asan integral part of the divider.
In accordance with the present invention, a programmable counter which may be used, for example, in a phase locked loop portion of a tuning system of the type decribed in the concurrently filed Henderson et al. application referenced above todivide the frequency of the local oscillator by a number proportional to the nominal local oscillator frequency for a selected channel is arranged so that it may also serve to generate a signal indicating whether or not the frequency of the localoscillator has drifted beyond a predetermined frequency offset after phase locked loop control of the local oscillator has been terminated. When the local oscillator is under phase locked loop control, the programmable counter accumulates a nominalnumber of counts during a predetermined portion of its output signal. Means are provided for generating a count signal after phase locked loop control of the local oscillator has been terminated. The count signal has a duration with a predeterminedtime relationship to a reference signal to which the local oscillator signal is locked when the local oscillator is under phase locked loop control. The counter is disabled from counting when the local oscillator is not under phase locked loop controlexcept during the duration of the count signal. Offset detection means, in response to the count signal, generates an offset signal representing the deviation between the count accumulated during a time interval corresponding to the predeterminedportion after phase locked loop control of the local oscillator has been terminated to determine how far the frequency of the local oscillator has drifted from the frequency synthesized under phase locked loop control.
C)- A tuning system for a television receiver includes a phase locked loop (PLL) configuration and an automatic fine tuning (AFT) configuration which are selectively enabled to operate to tune the receiver to nonstandard as well as standard frequency RF carriers which may be provided by cable and master antenna systems. After the selection of a new channel, the operations of the PLL and AFT configurations are sequentially enabled by a mode control apparatus. During the operation of the AFT configuration, an offset detector determines when the frequency of the local oscillator signal is caused to be more than a predetermined offset from its value established during the previous operation of the PLL configuration. In response, the mode control unit reestablishes the operation of the PLL configuration. Channel selection apparatus causes a new channel to be selected after a predetermined number of alternate operating cycles of the two configurations.
1. Apparatus for selectively tuning a receiver to any one of a plurality of RF carriers associated with respective channels, comprising:
local oscillator means for generating a local oscillator signal;
mixer means for combining a selected one of said RF carriers with said local oscillator signal to derive an IF signal having at least one carrier with a nominal frequency value;
phase locked loop (PLL) means for selectively controlling said local oscillator means when enabled to operate to cause said local oscillator signal to have a programmed frequency substantially equal to the product of a programmable factor and the frequency of a frequency reference signal;
programmable factor control means for determining programmable factor in accordance with the channel selected and for generating a CHANGE signal when a new channel is selected;
lock means for generating a LOCK signal when said local oscillator signal has a frequency substantially equal to said programmed frequency;
automatic fine tuning (AFT) means for selectively controlling said local oscillator means when enabled to operate to reduce a deviation between the actual frequency of said IF carrier and said nominal frequency value;
offset detector means for generating an OFFSET signal when the frequency of said local oscillator signal is caused to be offset from said programmed frequency by a predetermined amount during the operation of said AFT means;
mode control means for enabling the operation of said PLL means in response to said CHANGE signal, for enabling the operation of said AFT means in response to said LOCK signal and for again enabling the operation of said PLL means in response to said OFFSET signal; and
channel selection means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated a predetermined number of times.
2. The appara
tus recited in claim 1 wherein:
said predetermined number of times is equal to one.
3. The apparatus recited in claim 1 wherein:
said programmable factor control means is coupled to counter means for counting the number of times said OFFSET signal is generated to change said programmable factor by an increment less than the difference between programmable factors associated with respective adjacent channels when said OFFSET signal is generated a second predetermined number of times less than said first mentioned predetermined number of times; and
said channel selection means is also coupled to said counter means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated said first mentioned predetermined number of times.
4. The apparatus recited in claim 3 wherein:
said programmable factor control means increases said programmable factor by said increment in response to a first generation of said OFFSET signal and decreases said programmable factor by said increment in response to a second generation of said OFFSET signal and changes said programmable factor to the value associated with the next channel in response to a third generation of said OFFSET signal.
5. The apparatus recited in claim 4 wherein:
said programmable factor control means includes inhibiting means for inhibiting said programmable factor control means from changing said programmable factor to the value in response to said OFFSET signal after a predetermined time longer than the time required to tune said receiver to a selected channel.
The present invention relates to search type tuning systems.
A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past those channels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning system for a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control) detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.
Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuning systems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.
Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptable reception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.
SUMMARY OF THE PRESENT INVENTION
The present invention is an improvement to the type of electronic tuning system which includes first tuning means for tuning a tuner to standard frequencies associated with respective channels, second tuning means for tuning the tuner to reduce deviations between the frequency of an IF carrier generated by the tuner and its desired or nominal value that may arise due to, e.g., offsets in the frequencies of received RF carriers, and mode switching means for selectively applying the first and second tuning control signals to the tuner. In this type of electronic tuning system, the operation of the first tuning means is enabled after a new channel is selected and the operation of the second tuning means is enabled after the first tuning means has completed its operation. During the operation of the second tuning means, an offset detector determines when the frequency of a local oscillator signal generated by the tuner becomes offset from value established during the operation of the first tuning means and causes the operation of the first tuning means to again be enabled.
In accordance with the present invention, search means are provided in the above described type of electronic tuning system for causing a new channel to be selected if no RF carrier is tuned by the end of a predetermined number of operating cycles of the second tuning means.
SUPPLY 4822 212 20302 (TDA2581)
MATRIX 3122 133 31460 (TDA2771)
CHROMA 4822 212 20306 (TDA2523/4) + (TDA2560/3)
SOUND 4822 212 20599 (TDA2790)
MULTISTABILIZER 4822 212 20304 (TCA750Q)
IF AMPLIFIER 4822 212 20309 (TDA2750)
3122 133 31490
E/W + 29 /32/225V SUPPLY 4822 212 20305
SYNCRONIZATION 3122 133 31470 (TDA2572A)
IF DETECTOR 3131 118 58690 4822 212 20438 (TDA2760)
FRAME DEFLECTION 20AX 4822 212 20303 (TDA2780AQ)
TRD UNIT 8212 860 06032 ( SAB2015 SAB2024 )
OSD TUNING TRD UNIT 8212 860 06083
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I TDA2581 CONTROL CIRCUIT FOR SMPS/PHILIPS POWER PACK:
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I E/W CORRECTION Circuit arrangement in an image display apparatus for (horizontal) line deflection:
Line deflection circuit in which the deflection coil is east-west modulated. In order to cancel an east-west dependent horizontal linearity defect the inductance value of the linearity correction coil is made independent of the field frequency, for example by means of a compensating current. In an embodiment this current is supplied by the shunt coil of the east-west modulator.
1. Circuit arrangement for use with a line deflection coil, said circuit comprising a generator means adapted to be coupled to said coil for producing a sawtooth line-deflection current through said line deflection coil, said deflection current having a field-frequency component current, a horizontal linearity correction coil adapted to be coupled in series with said deflection coil and including an inductor having a bias-magnetized core, and means for making the inductance value of the linearity correction coil substantially independent of the field frequency component current. 2. Circuit arrangement as claimed in claim 1, wherein said making means includes a current supply source means for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the compensating current having a field-frequency variation. 3. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is opposite to the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have the same direction. 4. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is the same as the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have opposite directions. 5. Circuit arrangement as claimed in claim 2, wherein said correction coil further comprises an additional winding disposed on the core, said additional winding being coupled to said supply source means to receive the compensating current. 6. Circuit arrangement as claimed in claim 5, further comprising modulator means for modulating the line deflection current with said field frequency component, said modulator including a compensation coil coupled in series with said additional winding. 7. Horizontal linearity correction coil comprising a core made of a magnetic material and bias-magnetized by at least one permanent magnet, and an additional winding disposed on the core. 8. Image display apparatus including a circuit arrangement as claimed in claim 1.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Line oscillator synchronizing circuit:A television receiver having a line synchronizing circuit wherein gate pulses for keying the synchronizing signal are derived from the oscillator signal, the gate pulses being positioned, by means of an auxiliary phase control loop, substantially symmetrical relative to
an edge of a reference signal also derived from the oscillator signal. The auxiliary control loop also eliminates the influence of phase variations occurring in the line deflection circuit.
1. A television receiver having a line deflection circuit and a line synchronizing circuit, said line synchronizing circuit comprising a controllable oscillator, a signal derived therefrom being applicable to said line deflection circuit; a pulse generator coupled to said oscillator for deriving pulse-shaped gate signals; a coincidence detector; means for applying said pulse-shaped gate signals and pulse-shaped line synchronizing signals to said coincidence detector; a first phase discriminator coupled to said coincidence detector for determining the phase difference between said line synchronizing signal and a reference signal derived from said oscillator signal; a first low-pass filter for smoothing the output voltage from said first phase discriminator, said controllable oscillator being coupled to said first low-pass filter whereby the output therefrom controls the frequency and/or phase of said controllable oscillator; a second phase discriminator for determining the interval between the center instant of a pulse of said pulse-shaped gate signal and the center instant of an edge occurring in said reference signal; a second low-pass filter for smoothing the output voltage from said second phase discriminator; and means for controlling the center instant of the edge in said reference signal using the output from said second low-pass filter; wherein said line synchronizing circuit further comprises gate means having a first input terminal for receiving the output from said pulse generator and a second input terminal for receiving an output signal from said line deflection circuit, said gate means also having an output terminal for generating the gate pulses for said coincidence detector and said second phase dis
criminator. 2. A television receiver as claimed in claim 1, wherein said controlling means comprises a differential amplifier for amplifying the difference between the second smoothed voltage and a reference voltage, the time position of an edge of the oscillator signal being controllable by the output signal of the differential amplifier. 3. A television receiver as claimed in claim 1, wherein the time constant of the second low-pass filter is at least ten times smaller than the time constant of the first low-pass filter. 4. A television receiver as claimed in claim 1, wherein the gate means comprises an AND-gate, a first input terminal of which is the second input terminal of the gate means and a second input terminal of said AND-gate is supplied with a signal originating from the controllable oscillator, and an OR-gate, a first input terminal of which is the first input terminal of the gate means and a second terminal of said OR-gate is connected to the output terminal of the AND-gate, the output terminal of the OR-gate being the output terminal of the gate means. 5. A television receiver as claimed in claim 1, wherein said line sychronizing circuit further comprises an amplifier for amplfying the first smoothed voltage, the output voltage of which is supplied to the pulse generator. 6. A television receiver as claimed in any of the preceeding claims, wherein said line synchronizing circuit, with the exception of capacitors forming a part of said low-pass filters, is integrated in a semiconductor body.
PHILIPS 26C970/00R REMBRANDT CHAS
SIS K12I RGB HYBRID AMPLIFIER 4822 212 20307 3122 128 58455 CUT-OFF BEAM CONTROL CIRCUIT.
The RGB Amplifier in the chassis PHILIPS K12 is operating on the G1 instead on katode AS in conventional schemes.
These are realized with HYBRID IC'S technology and they're in ceramic substrate.
PHILIPS CHASSIS K12 (20AX) CRT TUBE RGB AMPLIFIER DETAIL RGB HYBRID AMPLIFIER 4822 212 20307 3122 128 58455
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Hybrid RGB Amplifiers on CRT Socket.
Driving directly: G1 blue G1 red G1 green.Hybrid IC Technology on Ceramic substrate.
On a ceramic substrate, spiral-type inductors of a single layer wiring of a metal thin film are provided and respectively connected to a wiring pattern formed on another face of the substrate via through holes. A semiconductor chip is flip-chip mounted on the substrate in a face-down manner. On the face of the semiconductor chip, capacitors composed of a highly dielectric material, resistors formed by an ion implantation method or a thin-film forming method, and FETs are provided, respectively. Interconnection between the substrate and an external circuit board is achieved employing terminals formed at end faces of the substrate. The terminals have a concave shape with respect to the end face of the substrate. Thus, there is no need to use a package, and miniaturization and reduction in cost of a high-performance hybrid IC is achieved.
1. A hybrid IC comprising:
a substrate including a front face, a back face opposite the front face, and side faces interposed between the front face and the back face which define an outer perimeter of the substrate;
at least one inductor formed on at least one of the front face and the back face of the substrate;
a semiconductor chip mounted on the front face of the substrate by flip-chip bonding;
at least one terminal formed in a predetermined portion of the side faces of the substrate,
wherein the semiconductor chip comprises a plurality of circuit elements provided therein, at least one of the plurality of circuit elements being an MIM capacitor having a metal-insulation film-metal (MIM) structure, the insulation film being composed of a highly dielectric material.
2. A hybrid IC according to claim 1 further comprising at least one matching circuit for matching an input signal to the circuit elements provided inside the semiconductor chip, the matching circuit comprising at least one inductor.
3. A hybrid IC according to claim 2, wherein a wiring pattern is formed of a single metal layer on both the front and back faces of the substrate, the wiring patterns on the respective front and back faces of the substrate being interconnected with each other via through holes, and the at least one inductor comprised in the matching circuit is formed in the wiring pattern on one of the respective front and back faces of the substrate.
4. A hybrid IC according to claim 2, wherein the matching circuit is constituted only by inductors and comprises at least one serial inductor and at least one parallel inductor.
5. A hybrid IC according to claim 4, wherein the parallel inductor comprised in the matching circuit is a spiral-type inductor, outermost wiring of the spiral-type inductor being grounded.
6. A hybrid IC according to claim 2, wherein the inductors comprised in the matching circuit are a spiral-type inductor or a meander-type inductor.
7. A hybrid IC according to claim 2, wherein the matching circuit comprises an inductor and a capacitor, the capacitor being formed inside the semiconductor chip.
8. A hybrid IC according to claim 7, wherein the inductor comprised in the matching circuit is a spiral-type inductor or a meander-type inductor.
9. A hybrid IC according to claim 1, wherein the at least one terminal includes at least an RF terminal functioning as an input terminal for an RF signal, an LO terminal functioning as an input terminal for an LO signal, an IF terminal functioning as an output terminal for an IF signal, a ground terminal, and a supply terminal.
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HERE BELOW A DETAILED DESCRIPTION OF THE PHILIPS CHASSIS K12 CRT DRIVING TECHNOLOGY:
PHILIPS CHASSIS K12 Automatic gray scale control circuit for a color television receiver
The present invention relates to a novel automatic gray scale control circuit for a color television receiver. The circuit senses the cut-off voltage of each gun during the blanking interval, and uses a voltage equal to the cut-off voltage to energize the driver and bias the gun during the video field. The effect is to standardize the emission of each of the three guns against variation in gun cut-off voltage and to produce improved gray scale accuracy at the lowest emission levels. Since the gray scale adjustment is optimized at the lowest emission levels, where the eye is most intolerant to error in hue, one may avoid the need for manual adjustment of the cut-off point, and in cases where the gain does not vary widely from gun to gun, avoid the need for separate gain adjustment. Thus, the circuit may be used either to simplify or eliminate the color set up process at the factory when the receiver is manufactured. It may also reduce or avoid the need for readjustment after periods of use.
PHILIPS CHASSIS K12 CRT Beam current control apparatus:TDA2770 TDA2771
Introducing beam current control:
In a television picture display device wherein a cathode of a picture display tube is driven by an emitter-follower and a control signal for a beam current reference level control circuit is obtained from the collector circuit of this emitter-follower, measures are taken to compensate for leakage currents from and to the cathode. To this end a blacker-than-black current compensation circuit is provided while furthermore it is ensured that the blacker-than-black curent can be processed by the beam current reference level control circuit.
1. A television picture display device for displaying pictures derived from video signals, said display device comprising a picture display tube having a cathode; an emitter-follower device coupled to said cathode for producing a beam current for driving said picture display tube; a beam current reference level control circuit coupled to said emitter-follower device for controlling the black level of the beam current; a blacker-than-black current compensation circuit incorporated in said beam current reference level control circuit for compensating for a leakage current in said cathode caused by a blacker-than-black level in the video signal; and a blacker-than-black current conduction circuit coupled to said cathode to enable compensation of said leakage current when said beam current is blanked.
2. A television picture display device as claimed in claim 1, wherein the blacker-than-black current conduction circuit comprises a direct current source coupled to the cathode of the picture display tube for keeping said emitter-follower device conductive at the occurrence of a blacker-than-black current in the cathode circuit of the picture display tube thereby allowing for the compensation of said blacker-than-black signal.
3. A television picture display device as claimed in claim 2, wherein the direct current source comprises a first and second resistor serially connected to a supply voltage said first resistor being a.c. coupled to the base of the emitter-follower device.
4. A television picture display device as claimed in claim 1, which further comprises a second emitter-follower device, of an opposite conduction type as said first-mentioned emitter-follower device, also coupled to said picture display tube cathode, and wherein said blacker-than-black current conduction circuit comprises a difference-forming circuit, coupled to the collector of the second emitter-follower device and coupled to an input of said beam current reference level control circuit.
5. A television picture display device as claimed in claim 4, wherein said difference-forming circuit comprises a current mirror circuit having an input and an output, the input of which is coupled to the collector of the second emitter-follower device and the output to the collector of the first-mentioned emitter-follower device.
6. A television picture display device as claimed in claims 2, 3, 4, 5 or 1, which further comprises a heater, a wehnelt electrode connection of the picture display tube and a leakage current conducting circuit, said heater and said wehnelt electrode connection being coupled to the collector of the first-mentioned emitter-follower device through a said leakage current conducting circuit.
The invention relates to a television picture display device having a picture display tube, a cathode of which is driveable by an emitter-follower, the collector of this emitter-follower being coupled to an input of a beam current reference level control circuit.
Dutch Patent Application No. 7604463 discloses a television picture display device of the above-defined type. In this device a control of the black level, serving as the reference level, of the beam current, to a constant value takes inter alia place by means of a voltage produced across the collector resistor of the emitter-follower. Although in principle this control should furnish a very constant black level this appears not to be the case.
SUMMARY OF THE INVENTION
It is an object of the invention to improve the constancy of the controlled reference level of the beam current.
A television picture display device of the above-defined type according to the invention is therefore characterized in that the beam current reference level control circuit comprises a blacker-than-black current compensation circuit by which the influence of the blacker-than-black current on the beam current reference level control circuit is compensated for while a blacker-than-black current conductive circuit is coupled to the cathode of the picture display tube so that the beam current reference level control circuit can also process a blacker-than-black current of the picture display tube occurring in case of a blanked beam current.
It should be noted that the use of a blacker-than-black current compensation circuit in a beam current reference level control circuit is known per se from the Dutch Patent Application No. 6903362. In that case, however, the picture display tube is controlled via the wehnelt electrode. When picture display devices to which the invention relates are controlled via the cathode, a blacker-than-black current compensation appears to be impossible without further measures. Applicants found, namely, that the cathode current of the picture display tube, in the case of a blanked beam current, may have a direction which may cut off the emitter-follower so that no measuring data about the collector resistance of the emitter-follower become available, and a blacker-than-black current compensation is not possible. By coupling a blacker-than-black current conduction circuit to the cathode of the picture display tube in such a manner that also the blacker-than-black current, occurring with a blanked beam current, can be processed by the beam current reference level control circuit, a blacker-than-black current compensation is possible. The blacker-than-black current conduction circuit may be a circuit supplying a constant direct current to the cathode of the picture display tube which ensures that the emitter-follower cannot be cut off if the picture display tube, in the case of a suppressed beam current, carries a cathode current which might cut off the emitter-follower, or a circuit which can take over the blacker-than-black current from the emitter-follower and pass it on to the beam current reference level control circuit.
DESCRIPTION OF THE DRAWINGS
The invention will now be further explained with reference to the drawing.
In the drawing
FIG. 1 shows a circuit of a picture display device according to the invention in which the emitter-follower can be kept conductive by means of a direct current and
FIG. 2 shows a further circuit of a picture display device according to the invention in which the emitter-follower current can be taken over by another circuit and passed to a control circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In FIG. 1 a video signal is applied to an input of an adder circuit 3. A control signal originating from an output 7 of a beam current reference level control circuit 9 appears at a further input 5 of the adder circuit 3. This control signal is added to the video signal and the sum signal is applied to the base of an emitter-follower 13 via an amplifier 11.
The emitter of the emitter-follower 13 drives a cathode of a picture display tube 14. The collector circuit of the emitter-follower 13 comprises a resistor 15, an end of which is connected to an input 17 of the beam current reference level control circuit 9. The beam current supplied by the emitter-follower 13 flows through this resistor 15.
The input 17 is, at the same time, the input of an amplifier 19, an output 21 of which is connected to an input 25 of an amplifier 27 via a switch 23. A capacitor 29 is also connected to the input 25. The switch 23 closes periodically under the influence of a signal derived from an output 31 of a switching signal generator 33 during the occurrence of the reference level, for example the black level, in the video signal.
Consequently a voltage, which is a measure of the cathode current of the picture display tube 14 during the occurrence of the reference level, is produced across the capacitor 29. This cathode current is composed of a beam current and a leakage current. To compensate for the influence of this leakage current, a switch 35, which is also connected to the output 21 of the amplifier 19, is periodically closed during the occurrence of a blacker-than-black level in the video signal, under the influence of a signal originating from an output 37 of the switching signal generator 33.
The switching signal generator 33 is synchronized with the video signal by a synchronisation signal, applied to an input 39 thereof, obtained from the video signal.
A capacitor 41, connected to the output of the switch 35, now has a voltage there across which is a measure of the leakage current of the cathode of the picture display tube 14. This voltage is supplied to an input 43 of the amplifier 27. The amplifier 27 amplifies the difference of the voltages across the capacitors 29 and 41 so that a control signal is produced at the output 7 thereof which is a measure of the beam current of the picture display tube during the occurrence of the reference level in the video signal. This control signal counteracts changes in the beam current reference level which corresponds to the video signal reference level.
The leakage current of the picture display tube 14 may sometimes be directed towards the cathode of that tube. In that case the emitter-follower 13 would be cut off and the leakage current could not be measured in the above described manner. Therefore a direct current is supplied to the emitter-follower 13 via two resistors 45, 47, which are connected to a positive supply voltage which may be in the order of approximately 40 μA. This direct current keeps the emitter-follower 13 in the conducting state thereof.
To enable also a compensation of this direct current in the the blacker-than-black compensation circuit, constituted by the switch 35, the capacitor 41 and the difference formation in the amplifier 27, the value of this direct current must not be dependent on the video signal. Therefore this video signal is applied, via a capacitor 49, to the junction of the resistors 45, 47 so that the voltage across the resistor 45 becomes independent of the video signal.
A second emitter-follower 51, which is also driven by a video signal, is also connected to the cathode of the picture display tube 14. The function of this second emitter-follower 51 is to enable a sufficiently rapid change of the charge of the cathode capacitance in the case of positive-going voltage transients in the video signal. This second emitter-follower plays no part in the measurements of the beam current reference value because the measurements are performed in periods in which the level in the video signal is constant for some time.
The variation in the leakage current in the cathode circuit of the picture display tube 14 can be many times larger than that in the beam current, which condition occurs if the reference level in the video signal is present. The variation in the voltage difference across the capacitors 28 and 41 would then be many times smaller than the variation in the voltage across one of the capacitors 28, 41. This might adversely affect the accuracy of the control system. To prevent this, two resistors 53 and 55 are provided which pass the leakage current from the wehnelt circuit and the heater circuit to the resistor 15 and, consequently, compensate the cathode leakage current to a large extent.
It will be obvious that the direct current supplied to the cathode of the picture display tube may be obtained, if so desired, by means of a transistor connected as a current source. This transistor should then be suitable for a rather high voltage because the voltage at the cathode of the picture display tube may change very much.
In FIG. 2 elements corresponding to elements of the circuit of FIG. 1 have been given the same reference numerals as in FIG. 1.
The blacker-than-black current compensation circuit of FIG. 2 is arranged somewhat differently then in FIG. 1. The capacitor 41 is now arranged in series with the output 21 of the amplifier 19 and the two switches 23 and 35, and the input 43 of the amplifier 27 is connected to ground. The switch 35 now operates as a clamping switch which ensures that the blacker-than-black level is connected to ground and the voltage across the capacitor 29 becomes a measure of the beam current occurring at the reference level in the video signal.
A further difference relative to the circuit of FIG. 1 is that the collector circuit of the second emitter-follower 51 includes a circuit which acts as blacker-than-black current conduction circuit and supplies any current flowing to the cathode to the input 17 of the beam current reference level control circuit 9 so that also these currents can be measured. The direct current supply circuit (45, 47) at the cathode of the picture display tube can then be dispensed with.
The collector current of the second emitter-follower 51 is supplied to the resistor 15 via two current mirror circuits. A first current mirror circuit is constituted by a series arrangement of a resistor 57 and a diode 59 in parallel with the series arrangement of the base-emitter path of a transistor 61 and a resistor 63 to a positive supply voltage. The collector current of the transistor 61 is supplied to a second current mirror circuit having a transistor 65 and a diode 67, which is in parallel with the base-emitter path of the transistor 65. The collector of the transistor 61 is connected to the resistor 15 through which the difference in the collector currents of the two emitter-followers 13, 51 now flows. Independent of the direction of the cathode currents of the picture display tube 14, a voltage, which is a measure of that cathode current, is now produced across the resistor 15.
Instead of determining the difference current by means of current mirror circuits in the described manner, it is alternatively possible, if so desired, to use other difference-determining circuits.
If so desired also the measuring data for a beam current limiting control of the resistor 15 can be obtained in the described circuits.
The amplifier 19 may comprise a circuit which limits the amplitude of the video signal outside the instants in which measuring takes place. This may be a circuit operated by an auxiliary signal or a self-switching circuit, for example a diode limiter circuit.
If the picture
display tube is a color display tube having several electron guns, the emitter-followers for each of the guns may have the resistor 15 in common and a sequential measurement may take place at a reference level sequentially occurring in the different video signals, so that only a portion of the control circuits is not common.
It will be obvious that the choice of the measuring instants and the associated occurrence of the reference levels and blacker-than-black levels are not important for the essence of the invention and may be chosen in a suitable manner.
The blacker-than-black current compensation circuits 9 of the above-described embodiments are interchangeable.
The amplifier 27 may comprise a level reference circuit so that the value of the beam current is determined which is associated with the corresponding reference level in the video signal.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I System for stabilizing cathode ray tube operation:
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The invention pertains to a video display apparatus which includes a cathode ray tube having at least one electron gun and means for deriving a source of excitatory voltage signal representative of picture information. In accordance with the invention there is provided a system for stabilizing the display intensity attributable to the electron gun comprising means coupling the source of voltage signal to the gun for generating a stabilized current in the gun, the level of current in the gun being substantially independent of variations in the operating characteristics of the gun. In the preferred embodiment of the invention a test signal is periodically applied at a predetermined level to the gun. A sampler samples the beam current of the gun during the test signal and generates a correction signal in accordance with the sample value. The correction signal is applied to the electron gun so as to stabilize its reference current level.
1. In a television display apparatus which includes a cathode ray tube having at least one electron gun and means for applying a television video signal to said electron gun; a system for stabilizing the display intensity attributable to said electron gun, comprising:
means for generating first and second test signals during the vertical blanking intervals of said television video signal;
means for applying said first and second test signals to said electron gun during first and second portions, respectively, of said vertical blanking intervals;
means for sampling the beam current of said electron gun during said first and second portions and for generating first and second correction signals, respectively, in accordance with the sampled values; and
means for applying said first and second correction signals to said electron gun so as to stabilize the reference current level of said electron gun.
2. The system as defined by claim 1 wherein said first and second correction signals are applied to grids of said electron gun.
3. The system as defined by claim 2 wherein means are provided for maintaining the correction signals during the intervals between successive test signals.
4. The system as defined by claim 1 wherein means are provided for maintaining the correction signals during the intervals between the successive test signals.
5. The system as defined by claim 1 wherein said first and second test signals are at white and black level viedo, respectively.
6. The system as defined by claim 5 wherein said first correction signal is applied as a multiplying factor to said television video signal.
7. The system as defined by claim 6 wherein the corrected television video signal is applied to the control grid of said electron gun.
8. The system as defined by claim 6 wherein the corrected television video signal is applied to the cathode of said electron gun.
9. The system as defined by claim 6 wherein said second correction signal is applied as a DC reference level to the corrected television video signal.
10. The system as defined by claim 1 wherein said means for sampling the beam current comprises a resistor in series with the cathode of said gun.
11. In a video display apparatus which includes a cathode ray tube having a plurality of electron guns and means for applying a plurality of television video signals representative of color picture information to said electron guns; a system for balancing the color screen temperature of said cathode ray tube, comprising:
means for generating first and second test signals during the vertical blanking intervals of said television video signal;
means for applying said first and second test signals to said electron guns during first and second portions, respectively, of said vertical blanking intervals;
means for sampling the beam current of each electron gun during said first and second portions and for generating first and second correction signals, respectively, for each electron gun in accordance with the sampled values; and
means for applying said first and second correction signals to their respective electron guns so as to balance the screen color temperature of said cathode ray tube.
12. The system as defined by claim 11 wherein said first and second correction signals are applied to grids of said electron guns.
13. The system as defined by claim 12 wherein means are provided for maintaining the correction signals during the intervals between successive test signals.
14. The system as defined by claim 11 wherein means are provided for maintaining the correction signals during the intervals between successive test signals.
15. The system as defined by claim 11 wherein said first and second test signals are at white and black level video, respectively.
16. The system as defined by claim 15 wherein said first correction signal is applied as a multiplying factor to each of said plurality of television video signals.
17. The system as defined by claim 16 wherein the corrected plurality of television video signals are applied to the control grids of their respective electron guns.
18. The system as defined by claim 16 wherein the corrected plurality of television video signals are applied to the cathodes of their respective electron guns.
19. The system as defined by claim 16 wherein said second correction signals are applied as DC reference levels to the corrected television video signals.
20. The system as defined by claim 11 wherein said means for sampling the beam current comprises a plurality of resistors in series with the cathode of said electron guns.
PHILIPS CHASSIS K12 Color television CRT beam current correction circuit:
Multi-gun color television display apparatus having for each gun an identical beam current reference level control system wherein the relative position of a reference level in the video signal and a setting voltage of the electron guns are periodically shifted for obtaining, for the control system outside the measuring periods, a coincidence of the reference level in the video signal and the cut-off point of each of the electron guns for a proper color rendition at a low brightness.
Inventors:Janssen, Peter J. H. (Eindhoven, NL) U.S. Philips Corporation (New York, NY)
1. A colour television display apparatus including a beam current reference level control
circuit comprising a measuring circuit included in the cathode circuits
of the electron guns of a multi-gun colour display tube for measuring
during a measuring period the beam current reference level to be
corrected, a level insertion circuit for providing during this measuring
period a reference level in a video signal to be applied to each gun of
the display tube, and a beam current level correction circuit coupled
to the measuring circuit and to a control electrode of each gun of the
display tube for obtaining substantially the same beam current reference
level in each of the electron guns, wherein said control circuit
further comprises a level shift circuit coupled to the electron guns of
the display tube for shifting, at each electron gun over substantially
the same amount, the mutual position of the reference level in the video
signal and a setting voltage of the electron gun occurring outside the
measuring period, relative to that mutual position during the measuring
period.
2. A colour television display apparatus as claimed in claim 1, wherein the electron guns of the display tube include screen grids which are coupled to the level shift circuit.
3. A colour television display apparatus as claimed in claim 2, wherein each of said screen grids includes a potentiometer for varying the screen grid voltage, said potentiometers each having one end thereof coupled one to the other in a common connection, and wherein the level shift circuit is coupled to said common connection.
4. A colour television display apparatus as claimed in claims 1, 2 or 3 wherein the measuring circuit comprises a plurality of beam current level correction circuits and means for sequentially coupling the cathodes to each of said beam current level correction circuits.
Description:
BACKGROUND OF THE INVENTION
The invention relates to a colour television display apparatus having a beam current reference level control circuit comprising a measuring circuit included in the cathode circuits of the electron guns of a multi-gun colour display tube for measuring during a measuring period the beam current reference level to be corrected, a level insertion circuit for providing during said measuring period a reference level in a video signal to be applied to each gun of the display tube, and a beam current level correction circuit coupled to the measuring circuit and to a control electrode of each gun of the display tube for obtaining substantially the same beam current reference level in each of the electron guns.
The Dutch Patent Application No. 7202401 (PHN 6130) discloses a colour television display apparatus of the above-mentioned type wherein by the use of a sequence circuit a great portion of the beam current reference level control circuits is in common for the different electron guns of the picture display tube. Then the beam current reference levels of these guns cannot substantially differ from one another. The colour rendition of this apparatus is very constant and substantially independent of disturbing influences. However, in general, the phosphors of the picture display tubes do not have the same efficiency so that the colour rendition for low luminance values is not quite correct if this rendition is correctly adjusted for high luminance values. It would be possible to obtain a correct rendition for low luminance values by using a beam current reference level which would be much lower than the presently used value of some μA. This has practical disadvantages. In addition it would, for example, be possible to perform a correction by means of a circuit with which the beam current reference levels could be adjusted in a ratio matched to the efficiency of the phosphors. This would not only require an adjustment for high luminances but also an additional adjustment at a low luminance.
SUMMARY OF THE INVENTION
It is an object of the invention to obtain a correct colour rendition at that low luminance without an additional adjustment at a low luminance.
To this end a colour television diaplay apparatus of the type mentioned in the preamble according to the invention is characterized in that the electron guns of the picture display tube are coupled to a level shift circuit for shifting at each electron gun, over substantially a same value, the mutual position of the reference level in the video signal and a setting voltage of the electron gun outside the measuring period relative to that mutual position during the measuring period.
The value of the voltage with which the level shift is obtained is the same for all three guns because the beam current reference levels are the same. No adjustment of a mutual amplitude ratio is then required. In addition, the value of this voltage depends substantially only on the beam current reference level value and a plurality of other known and constant factors, so that it can be obtained by means of a proper rating of the circuit so that no adjustment is required.
DESCRIPTION OF THE DRAWING
The invention will now be further explained with reference to the drawings.
In the drawings
FIG. 1 shows on the basis of a diagram the underlying principle of the invention,
FIG. 2 shows, with reference to a block diagram, a colour television receiver having a display apparatus including a level shift circuit according to the invention,
FIG. 3 shows wave forms occurring in different points in the circuit of FIG. 2,
FIG. 4 shows, with reference to a principle circuit diagram, an embodiment of a measuring circuit and a sequence circuit for a display apparatus according to the invention,
FIG. 5 shows, with reference to a principle circuit diagram, an embodiment of a blanking circuit and a beam current level correction circuit for a display apparatus according to the invention,
FIG. 6 shows, with reference to a principle circuit diagram, an embodiment of a level insertion circuit for a display apparatus according to the invention,
FIG. 7 shows, with reference to a block diagram, a pulse generator circuit for a display apparatus according to the invention,
FIG. 8 shows, with reference to a concise principle circuit diagram, a possible embodiment of a level shift circuit in the Wehnelt circuits of the picture display tube for a display apparatus according to the invention and
FIG. 9 shows, with reference to a concise principle circuit diagram, a possible embodiment of a level shift circuit in the cathode circuits of the picture display tube for a display apparatus according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In FIG. 1 a curve C shows how the beam current IB of an electron gun of a picture display tube varies as a function of the Wehnelt cathode voltage VGK. Furthermore, a video signal V is shown as a function of the time with which the Wehnelt cathode voltage can be varied. During a measuring period T the video signal V has a reference level R. In a picture display apparatus according to the invention the beam current is measured during this measuring period T and controlled by means of a beam current reference level control circuit to a constant beam current reference value IBR of some μA. To this end the control circuit continuously readjusts, for example, the Wehnelt cathode voltage VBR. The video signal V has a black level B which substantially coincides with the reference level R.
In a colour display apparatus according to the invention a beam current reference control circuit is present for each electron gun of the picture display tube. If these control circuits are mutually equal--which, for example, can be accomplished in a simple manner by using a sequentially measuring circuit which may be in common for a great portion of the three electron guns--then the beam current reference value of each gun is adjusted to the same value IBR. At this beam current value the phosphors of the picture screen of the picture display apparatus emit a very small quantity of light which, however, due to the difference in efficiency of the phosphors, are not equal so that a certain colour will be somewhat more predominant. Due to the control circuits, this colour remains very constant. With a low-level drive of the picture display tube, so if the video signals are near the black level, a colour deviation occurs which is the smaller in proportion, as the amplitude of the video signals are greater because, for a white rendition occurring at the maximum amplitude, the amplitude ratio of the video signals is readjusted.
In order to obtain a proper colour rendition also at a low video signal amplitude, the luminance must occur for all three colours in the same ratio as with a high video signal amplitude. As known, this can be accomplished by having the black levels B in the video signals coincide with the cut-off points Vco of the electron guns. Then, however, no beam current occurs and a control of that current is impossible.
It has appeared that the difference Vs, between the cut-off voltage Vco and the voltage VBR applied by the control circuits to the guns, is substantially constant even if the voltage VBR must vary, due to disturbing influences, to keep IBR constant. This applies to each of the three electron guns. By shifting the video signal and consequently the black level B outside the measuring period T for each of the three guns over an amount Vs, a proper colour rendition for low video signal amplitudes can yet be obtained while maintaining the beam current reference level control system. This shift is shown in the figure by means of a dotted video signal curve V' having a black level B' which substantially coincides with the cut-off position Vco. An additional method is to shift the characteristics of the electron guns of the picture display tube outside the measuring period T to the position indicated by a dashed-dotted line. A combination of these methods is also possible. Some circuit possibilities for obtaining said level shifts will be indicated below. The value Vs can be calculated from ##EQU1## where k is a constant which depends on the construction of the electron gun and which can be easily determined.
For a cut-off voltage of 175 V the following table applies for the electron guns which are used most frequently at the moment
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IBR = 2μ A Vs = 11.56 Volts IBR = 3μ A Vs = 13.23 Volts IBR = 4μ A Vs = 14.56 Volts
______________________________________
If the characteristics of the picture display tube are known, this level shift voltage can, if so desired, be converted into a shift
voltage for a screen grid of the picture display tube.
If the amplitude of the level shift voltage deviates somewhat from these values, the displayed colour will indeed not be perfectly identical, during the occurrence of the black level in the video signal, to the colour when the white level occurs but a considerably more accurate colour rendition is yet obtained at low video signal amplitudes than if no level shift were used.
In FIG. 2 an RF, IF and detector section 1 has an input 3 to which a colour television signal to be processed may be applied. This results in a luminance signal Y at an output 5 of section 1, a chrominance signal Chr at an output 7 and a synchronizing signal S at an output 9.
The synchronizing signal S is applied to an input 11 of a time base generator 13. Deflection currents are obtained from two outputs 15 and 17 which are connected to a deflection coil system 19 of a display tube 21, and an EHT, for feeding an anode 25 of the display tube 21, is obtained from an output 23 of the time base generator 13.
An output 27 of the time base generator 13 supplies line flyback pulses to an input 29 of a pulse generator 35 and an output 31 supplies field flyback pulses to an input 33 of the pulse generator 35. In FIG. 3 these pulses are represented by the waveforms 201 and 202, respectively. FIG. 3 furthermore shows a number of waveforms 203, 204 . . . 220 and a number of instants t1, t2 . . . t10 which are of interest for the explanation of the operation of the circuit. The waveforms have not been drawn to scale.
The pulse generator 35 has a number of outputs 37, 39, 41, 43, 45, 47, 49, 51, 53 and 55 at which the waveforms 203, 210, 211, 212, 213, 214, 215, 216, 217 and 218, respectively, are available.
The output 55 of the pulse generator 35 is connected to an input 57 of a level insertion circuit 59 whose input 61 is connected to output 5 of section 1 from which it receives the luminance signal Y. The level insertion circuit 59 has an output 63 at which the modified luminance signal represented by waveform 220 of FIG. 3 is available, which, during three line periods t5 -t6, t7 -t8, t9 -t10 at the beginning of a field, comprises a reference level 221 which has been inserted with the aid of the waveform 218 applied to the input 57.
At a further output 65 of the level insertion circuit 59 the waveform 219 is available which is applied to an input 67 of a chrominance signal amplifier 69 for suppressing the chrominance signal applied to an input 71, which is connected to the output 7 of section 1.
The output 63 of the level insertion circuit 59 is connected to an input 73 of a distributor circuit 75 of which three outputs 79, 81, 83 are connected to inputs 85, 87 and 89, respectively, of three blanking circuits 91, 93 and 95, respectively. Inputs 97, 99 and 101 of these blanking circuits 91, 93, 95 are connected to outputs 51, 49 and 47, respectively, of the pulse generator 35 and inputs 103, 105 and 107 are connected to outputs 109, 111 and 113, respectively, of a demodulation and matrix circuit 115, a chrominance signal coming from an output 119 of the chrominance signal amplifier 69 being applied to an input 117 of said demodulation and matrix circuit 115.
The demodulation and matrix circuit 115 produces (B-Y), (G-Y) and (R-Y) colour difference signals at its outputs 109, 111 and 113, respectively. In the blanking circuits 91, 93 and 95, these colour difference signals are added to a modified luminance signal from the distributor circuit 75 to obtain the colour signals R, G and B; the reference signal 221, derived from the luminance signal, being suppressed in a special sequence due to the signals having the waveforms 214, 215 and 216 at the inputs 97, 99 and 101. In this example, such a sequence is adhered to that, in the R-signal, a reference level is left from t5 till t6 only, in the G-signal from t7 till t8 and in the B-signal from T9 till T10. These signals with the relevant reference level are available at outputs 121, 123 and 125 of the blanking circuits 95, 93 and 91, respectively and are fed to inputs 127, 129 and 131 of beam current level correction circuits 133, 135 and 137, respectively, in which these reference levels are coupled to a certain beam current value of a corresponding electron gun of the display tube 21.
The beam current level correction circuits 133, 135 and 137 have outputs 139, 141 and 143, respectively, which are connected to the Wehnelt electrodes of the "red", the "green" and the "blue" gun, respectively, of the display tube 21. Furthermore, inputs 145, 147 and 149 of said blanking correction circuits are connected to the output 37 of the pulse generator 35 in order to supply a blanking signal which, during the time base flyback periods, prevents a signal from being applied to the display tube 21. Inputs 151, 153 and 155 are furthermore connected to outputs 157, 159 and 161 of storage circuits 163, 165 and 167, respectively, of a sequence circuit.
Inputs 169, 161 and 173 of the storage circuits 163, 165 and 167 are connected to outputs 174, 175 and 176 of switches 177, 178 and 179, respectively, whose control signal inputs 183, 184 and 185 are connected to the outputs 39, 41 and 43, respectively, of the pulse generator 35.
The switch 177 conducts only from t5 till t6, switch 178 from t7 till t8 and switch 179 from t9 till t10. Each of these switches feeds a level applied to one of its inputs 180, 181 and 182, respectively, into the relevant storage circuits 163, 165, 167.
The
inputs 180, 181, 182 are connected to an output 186 of a measuring
circuit 187 having an input terminal 189 connected to the interconnected
cathodes of the display tube 21, an input terminal 190 connected to a
positive voltage of 130 volts, an input 191 connected to the output 45
of the pulse generator 35 and an input 192 connected to the output 53 of
the pulse generator 35.
The interconnected cathodes of the display tube 21 are also connected to the positive voltage of +130 volts via a parallel connection of a resistor 193 and a diode 194. The screen grids of the guns are each connected to an adjustable tap of potentiometers 195, 196, 197 which are arranged in series with two potentiometers 801, 803 between +130 v and a higher voltage ++.
The measuring circuit 187 transfers a beam-current dependent voltage, which is consecutively caused by the reference level of the signal at each of the Wehnelt electrodes, to switches 177, 178, 179 which retain these voltages in the memory circuits 163, 165, 167 during the field period and which transfer these voltages to the inputs 151, 153, 155 of the beam current level correction circuits 133, 135, 137. During this transfer, the other guns draw no beam current. This results in a stabilisation of the beam current of each gun corresponding to the reference level in the luminance signal, using only one measuring circuit 187 which influences each of the control loops thus obtained in exactly the same manner.
A beam current control thus obtained on a reference level ensures a very good setting of the three guns of the display tube 21 which, at a sufficient gain in the control loop, always results in a constant colour of signals of low brightness, so-called background brightness, independent of, for example, supply voltage and temperature variations.
To ensure that this colour is the proper colour a pulse is supplied via a capacitor 805 to the tops of the parallel-arranged potentiometers 195, 196, 197 which pulse is obtained via an inverting circuit 809 from the output 45 of the pulse generator 35 and which, consequently, has a waveform which is opposite to waveform 213. Each of the screen grids of the picture display tube 21 is supplied with a pulse of substantially the same amplitude so that the setting of the electron gun of the picture display tube 21, during the occurrence of the video signal, is shifted relative to that during the occurrence of the reference level at which the beam current is stabilised. By means of a proper choice of the amplitude of this pulse the black level in the video signal at each electron gun is substantially placed in the cut-off point of this gun. The screen grid potentiometers 195, 196, 197 are adjusted so that the Wehnels voltages are mutually equal during occurrence of a black level. Because the gain factors of the screen grid can somewhat deviate from a standard value the adjustment of potentiometers 195, 196, 197 may differ somewhat. The level shift voltage is supplied to the tops of the potentiometers 195, 196, 197 and consequently has a somewhat different amplitude at the screen grids in a manner which is then accurately adapted to the relevant gain factors of the screen grids. A customary adjusting procedure for a white-signal is now sufficient to obtain a proper rendition at any level of the video signals.
The circuit 809, 805, 195, 196, 197 is used as a level shift circuit with which the cut-off point of each of the electron guns, outside the measuring period, substantially coincides with the black level in the video signals.
A possible implementation of another circuit with which the same results can be achieved and which is operative in the cathode circuit of the picture display tube is shown in FIG. 9.
It is alternatively possible to perform a level correction in each of the video signals. This is illustrated in FIG. 8.
In FIG. 4 corresponding sections have the same reference numerals as in FIG. 2. FIG. 4 illustrates one of the three beam current reference level-clamping control circuits and the common measuring amplifier 187 for the three reference level-clamping control loops, the sequence switches 177 and the beam current level correction circuit 133.
A signal occurring at the cathodes of the display tube 21 causes a voltage across the resistor 193 which voltage is limited by the protection diode 194, which is cut off during the measuring intervals. This voltage is applied to the input terminals 189, 190 of the measuring amplifier 187. The input terminals 189, 190 are connected to the base and emitter, respectively, of a pnp-transistor 301 whose collector is connected to ground via a resistor 303, is grounded with respect to high frequencies via a capacitor 305 and has a negative feedback coupling to the base via a resistor 307.
A signal amplified by the transistor 301 is fed to the base of an npn-transistor 313 via a series connection of a resistor 309 and a capacitor 311. Connected to the base of transistor 303 is the collector of an npn-transistor 315 which serves as a clamping switch, the emitter of the transistor 315 being connected to ground via a series connection of a resistor 317 and two diodes 319 and 321 and the base of the transistor 315 being connected to the input 191 of the circuit 187.
Due to the waveform 213 which is applied to the input 191, the transistor 315 is cut off only during the occurrence of the signal caused by the reference signal 221 at the cathodes of the display tube 21. During the preceding line periods the capacitor 311 has assumed a constant charge condition, (has been clamped) via transistor 315 which is then conducting, as a result of the absence of a signal at the cathodes of the display tube 21, because both the chrominance signal and the luminance signal are then suppressed. The diodes 319 and 321 then provide a clamping level at the base of transistor 313. During the interval t4 -t10, signals caused by the reference level 221 during time intervals t5 -t6, t7 -t8 and t9 -t10, respectively occur at the successive cathodes of the display tube 21. These signals occur at the base of the transistor 313 in amplified form and, via the emitter of the transistor 313 and a series resistor 323, they drive the base of the an npn-transistor 325. The emitter of transistor 325 is connected to the collector of an npn-transistor 327 whose emitter is connected to ground and whose base is connected to the input 192, and via a resistor 329, to ground.
The waveform 217 is fed to the base of the transistor 327 so that, only during the time intervals t5 -t6, t7 -t8, t9 -t10, the emitter of transistor 325 is grounded via transistor 327; and transistor 325 functions as an amplifier so that only then a signal is produced at its collector across a resistor 331. This signal is fed to the base of an npn-transistor 333 which is connected in emitter follower arrangement and whose emitter is connected to the output 186 and via a resistor 335, to ground.
At the output 186, a signal is obtained having levels which are produced by each of the cathodes in succession during the previously mentioned time intervals. These levels are a measure of the beam current of the relevant gun and are transferred via switches 177, 178 and 179 consecutively, to the memory circuit 163 during the time interval t5 -t6, to the memory circuit 165 during the time interval t7 -t8, and to the memory circuit 167 during the time interval t9 -t10.
Switch 177 is formed by two npn-transistors 337, 339, connected in opposition, whose respective bases are connected via resistors 341, 343 to the input 183 which, during the time interval t5 -t6, receives a positive pulse represented by the waveform 210 from output 39 of pulse generator 35. As a result, the two transistors 337 and 339 are conducting during this time interval. These transistors are cut off for the rest of the time. During the time interval t5 -t6 input 180 of the switch 177 is then connected to output 174 thereat and via input 169 of the memory circuit 163, to a resistor 345 whose other terminal is connected to a capacitor 347 whose other side is connected to ground.
In time interval t5 -t6 capacitor 347 is charged to the level occurring at the output 186 of the measuring amplifier 187 which, via the output 157, is fed to the input 151 of the beam current level correction circuit 133 and, by means of which, the beam current, caused by the reference signal 221 in the gun of the display tube 21 connected to the output 199, is maintained constant.
In a similar manner the beam currents of the other guns are stabilized in the time intervals t7 -t8 and t9 -t10.
In FIG. 5 corresponding sections have the same reference numerals as in FIG. 2 and FIG. 4. In FIG. 5 one of the blanking circuits 95 and the corresponding beam current level correction circuit 133 are shown, as well as their relationship with the reference level control circuit referred to in FIG. 4.
A modified luminance signal Ym with the waveform 220 is applied to the input 89 of the blanking circuit 95 which, during the time intervals t5 -t6, t7 -t8 and t9 -t10, contains the reference level 221 which is suppressed from t1 till t5. The input 89 is connected to the base of an npn-transistor 401 whose emitter is grounded via a resistor 403 and whose collector is connected to the emitter of an npn-transistor 407 via a resistor 405. The collector of the transistor 407 is connected to a positive voltage, and the base is connected to the input 107 and receives a red colour difference signal -(R-Y) which is suppressed from t1 till t10.
The output 121 of the blanking circuit 95 is connected to the collector of the transistor 401. Connected to the emitter of the transistor 401 is the emitter of an npn-transistor 409 whose collector is connected to a positive voltage and whose base is connected to the input 101.
A voltage of the waveform 214 is fed to the input 101 so that transistor 409 is conducting during the time intervals t7 -t8 and t9 -t10 due to which the transistor 401 cuts off and transistor 407 draws no current either and the signal at the output 121 is suppressed.
When transistor 409 is not conducting, a combination of the -(R-Y) signal, supplied via the emitter follower 407 and the-Ym signal, supplied via the amplifier transistor 401, is fed to the output 121. This combination is a -R signal containing a reference level corresponding to level 221 during the time interval t5 -t6, said reference level being suppressed in the time intervals t1 -t5 and t6 -t10. Via the input 127 of the beam current level correction circuit 133, this signal is applied to the base of an npn-transistor 411 whose collector is connected to a positive voltage and whose emitter is connected via a resistor 413 to the collector of an npn-transistor 415 whose emitter is grounded via a resistor 417 and whose base is connected to a reference voltage via a resistor 418.
The emitter of the transistor 415 is furthermore connected to the emitters of two npn-transistors 419 and 421 whose collectors are connected to a positive supply voltage.
Via an npn-transistor 423 which is connected as an emitter follower, a level correction voltage applied to the input 151 is transferred to the base of the transistor 419, while a blanking signal with the waveform 203 applied to the input 145 is transferred to the base of the transistor 421. The blanking signal suppresses the beam currents during the line field flyback periods in the usual manner. As the transistor 421 only becomes conducting during these flyback periods, the transistor 415 is cut off and no signal is supplied to the collector of the transistor 415 because the emitter circuit of the transistor 411 is then interrupted.
The level correction voltage applied to the input 151 is fed to the emitter of the transistor 415 via the emitters of the transistors 423 and 419 and influences the direct current through the resistor 413 which is supplied by the transistor 415 and thus the d.c. level of the -R-signal transferred to the collector of the transistor 415 via the emitter of the transistor 411.
The collector of the transistor 415 is connected to the base of an npn-transistor 425 whose collector is connected to a positive supply voltage via a resistor 427 and whose emitter is connected to the base of an npn-transistor 431 via a variable resistor 429. The emitter of the transistor 431 is connected to ground and the collector is connected to the emitter of an npn-transistor 433 whose collector is connected to a positive supply voltage of +130 V via a resistor 435. The base of the transistor 431 receives a negative feedback voltage from the collector of the transistor 435 via a potential divider of resistors 437, 439.
A red colour signal R, amplified by transistors 431 and 433, is obtained from the collector of transistor 433, which signal is fed via the output 139 to the Wehnelt electrode of the red gun of the display tube 21. The gain of the beam current level correction circuit 133 is adjustable with resistor 429 in order to enable a white-point correction. Due to the clamping control loop, a white-point correction hardly affects the beam current which is caused by the reference signal 221 so that the adjustment of the resistor 429 will not change the black level and, thus, neither the colour of the dark portions in the image.
In FIG. 6 the same reference numerals have been used as in FIGS. 2, 4 and 5 for the corresponding sections of the circuit. FIG. 6 shows a level insertion circuit 59.
A luminance signal is applied to the input 61 of said circuit which signal is fed to an input 501 of an amplifier 503. The amplifier 503 furthermore has an input 507, to which a direct voltage is applied, which is adjustable with a potentiometer 509, and which serves for brightness control, and an input 511 to which a blanking signal is applied having the waveform 219 of FIG. 2. The picture black level 22 in waveform 220 is adjustable by means of the potentiometer 509 relative to the level occurring during the blanking periods. The waveform 220 is the luminance signal occurring at the output 63 across an emitter resistor 513 of an npn-transistor 515, which is connected as an emitter follower and whose base is connected to the output 505 of the amplifier 503.
A signal with the waveform 218 is fed to the input 57 of the level insertion circuit 59. Via a capacitor 517 and a resistor 519, said signal is applied to a splitter, one side of which is connected to the base of an npn-transistor 523 via a resistor 521 and the other side to the basis of an npn-transistor 529 via a potential divider of resistors 525, 527.
During the most positive parts of the waveform 218 a low voltage develops across the collector resistor 531 of the transistor 523. The level of the signal in time intervals t5 -t10 lies below the cutoff point of the transistor 523 so that this signal is not contained in the collector signal 219 of the transistor 523. However, due to the potential divider 525, 527, which is connected to a positive voltage, the transistor 529 only responds to the most negative portions of the signal 218 and the transistor 529 is cut off during time intervals t5 -t6, t7 -t8 and t9 -t10 so that positive-going square-wave voltages will then occur on the collector of the transistor 529.
Via a resistor 533, the collector of the transistor 529 is connected to a potential divider with a resistor 535 and a series connection of a diode 536 and a resistor 537. The voltage on the tap of this potential divider has a constant value of +2.2 V which also occurs on the collector of the transistor 529 in the abovementioned time intervals. Via a resistor 538, this voltage is transferred to the base of an npn-transistor 539 whose collector is connected to a positive supply voltage and whose emitter is connected to the emitter of the transistor 515. In the time intervals t5 -t6, t7 -t8 and t9 -t10 the emitter voltage of transistor 539 becomes +1.5 V due to its base voltage so that the transistor 515 is cut off and the reference level 221 is produced at the output 63. For the rest of the time the transistor 539 is cut off and a signal is applied to the output 63 via the transistor 515.
As becomes apparent from the waveform 220 the black level 222 of the signal is also adjustable relative to the constant reference level 221 which, due to the previously discussed beam current reference level control circuits, corresponds to a constant beam current value in each of the guns of the display tube 21.
In FIG. 7, in which the corresponding sections have the same reference numerals as in FIGS, 2, 4, 5 and 6, a block diagram is shown of a possible embodiment of the pulse generator 35.
Field flyback pulses, with a waveform 202 whose trailing edge sets a first section of the shift register from its 0-state to the 1-state, are applied to input 33, which is connected to an input 601 of a shift register 603. Due to line flyback pulses with a waveform 201 applied to each of the five sections of the shift register 603, the second section of the shift register is set from the 0 to the 1 state and the first section is reset to the zero state upon the first line flyback pulse occurring after the trailing edge of the field flyback pulse. The 1 state is shifted one section further in the shift register 603 upon each subsequent line flyback pulse.
The sections of the shift register 603 have outputs 605, 607, 609, 611 and 613 at which, consecutively, the pulses represented in FIG. 3 by the waveforms 204, 205, 206, 207 and 208 arise, which are applied to five inputs 615, 617, 619, 621 and 623 of a gate circuit 625, of which a sixth input 627 is connected to the input 33 for the field flyback pulse. The gate circuit 625 applies an extended field flyback pulse with a waveform 209 to an output 629 which pulse covers the total duration of the original field flyback pulse 202 and the subsequent shift-register output pulses 204, 205, 206, 207 and 208.
The outputs 609, 611 and 613 of shift register 603 are connected to three inputs 631, 633 and 635 of a gate and inverter circuit 637. At an output 639 of this circuit connected to the output 45, this results in a pulse represented by the waveform 213 in FIG. 2, which has the duration of the three pulses 206, 207 and 208 together. This pulse 213 is applied to the clamping switch 315 of the measuring amplifier 187 as described previously.
The output 609 of the shift register 603 is furthermore connected to an input 641 of a gate circuit 643, the output 611 is connected to an input 645 of a gate circuit 647 and the output 613 is connected to an input 649 of a gate circuit 651. The other inputs 653, 655 and 657 of these gate circuits are connected to the line flyback pulse input 29. At an output 659 of the gate circuit 643, which is connected to the output 39, the waveform 210 arises which corresponds to a waveform 206 which has been suppressed during the line flyback period. An output 661 of the gate circuit 647 is connected to the output 41 and carries the waveform 211, i.e. a waveform 207 which is suppressed during the line flyback period, and the output 663 of the gate circuit 651 connected to the output 43 receives waveform 212, i.e. a waveform 208 which is suppressed during the line flyback period. As previously stated, the pulses 210, 211 and 212 serve for sequentially connecting the relevant memory circuits 163, 165 and 167 via the switches 177, 178 and 179 to the output 186 of the measuring circuit 187 during the corresponding line periods at the beginning of each field.
The outputs 659, 661 and 663 of the gate circuits 643, 647 and 651 are furthermore connected to inputs 665, 667 and 669 of a gating and superimposition circuit 671, to an input 673, 675 and 677 of a gate circuit 679 and the outputs 659, 661 are connected pairwise to inputs 681, 683 of a gate circuit 685, the outputs 659, 663 are connected to inputs 687, 689 of a gate circuit 691, the outputs 661, 663 are connected to inputs 693, 695 of a gate circuit 697.
A further input 699 of the gating and superimposition circuit 671 is connected to the output 629 of the gate circuit 625 and an input 701 is connected to the line flyback pulse input 29. An output 703 is connected to the output 55 and supplies the waveform 218 which is a combination of line flyback pulses 201 with an extended field flyback pulse 209 on which inverted waveforms 206, 207 and 208 are superimposed. The waveform 218 is fed to the level insertion circuit 59 where it is split up into a suppression signal and a level insertion signal by amplitude selection at two levels in the signal 218. It will be evident that for circuits for which there is no need to minimize the number of connections between the pulse generator 35 and the level insertion circuit 59, the two signals may alternatively be produced separately in the pulse generator 35 and transferred to the relevant circuit.
An output 705 of the gate circuit 679 is connected to the output 53 at which the waveform 217 develops which occurs during the common time interval of the waveforms 210, 211 and 212 and which is used to render the measuring circuit 187 conductive for the transfer of the measured beam current values to its output 186.
The gate circuit 685 has an output 707 which is connected to output 51 and at which the waveform 216 appears, the gate circuit 691 has an output 709 connected to the output 49 and supplying the waveform 215 and the gate circuit 697 has an output 711 which is connected to the output 47 and at which the waveform 214 appears. During the measurement of the beam current of a gun these waveforms, as previously stated, serve to suppress the beam currents of the other guns by means of the appropriate suppression circuits 95, 93 and 91.
The line flyback pulse input 29 and the field flyback pulse input 33 are furthermore connected to inputs 713 and 715, respectively, of a gate circuit 717 whose output 719 is connected to the output 37. As a result, a combination of field and line flyback pulses appears at this output having the waveform 203 and being employed for suppressing the signal passage through the amplifiers for the R, G and B-signals 133, 135 and 137.
In FIG. 8 in which corresponding sections have the same reference numerals as in the other figures, the video output amplifiers are shown in a corresponding manner as those in FIG. 5. The reference numerals of corresponding sections in the amplifier which were not shown in FIG. 5 are provided with a prime or a double prime respectively.
Instead of being connected to a fixed voltage, the resistors 439, 439', 439" are now connected to an output 811 of an amplitude correction circuit 813, an input 815 of which is connected to the output 45 of the pulse generator 35 and by means of which the amplitude and the location of the pulse are adjusted to the correct value. As a consequence thereof, a pulse having the same amplitude is supplied to each of the bases of the transistors 431, 431' and 431". Because the output amplifiers are highly fedback via the mutually equal resistors 437, 437', 437", the pulse present on the transistor bases is transferred to the collectors of the transistors 433, 433', 433" without disturbing the mutual equality in amplitude. A level shift of the video signals as shown in FIG. 1 now occurs at the Wehnelt electrodes of the picture tube 21 outside the measuring periods of the beam current reference level control circuit.
FIG. 9 shows a possible circuit for causing a level shift in the cathode circuit of the picture display tube outside the measuring period. Corresponding sections have been given the same reference numerals as in the previous figures. The input circuit is shown of the measuring circuit 187 of FIG. 5. The base of the transistor 301 is now connected via a resistor 817 of approximately 1000 Ω to the interconnected cathodes of the picture display tube 21. These cathodes are furthermore connected to the collector of a pnp-transistor 819 whose emitter is connected to a positive voltage (130+Vs). The base of the transistor 819 is connected via a resistor 821 to an output 823 of an inverting circuit 825, an input of which is connected to the output 45 of the pulse generator 35. As a consequence the transistor 819 is cut off during the measuring period and the cathode current flows via the resistor 817 to the measuring circuit 187. The cathode voltage is then substantially +130 V. The transistor 819, which operates as a switch, is kept fully conducting outside the measuring period by the output voltage of the inverting circuit 825 and the cathode voltage then becomes +(130+Vs) Volts, that is to say a desired level shift of Vs Volts occurs.
It will be evident that some modifications to the pulse generator 35 will enable the measuring times to be transferred to other periods and furthermore, if desired, it is possible to measure during, for example, more consecutive line periods per gun, the sequence in which the gun currents are measured also being optional. For line-sequential colour television systems employing a delay device to make the colour information of one or more preceding line periods available, it is desirable, in order to avoid disturbing effects, to commence the suppression in the chrominance signal at least a number of line periods corresponding to the delay time of the delay device prior to the measuring cycle.
The cathodes of the display tube which in the described embodiment are directly interconnected may be interconnected via a resistive network, if desired.
The variable resistors 195, 196 and 197 for the screen grids, shown in FIG. 2 serve to enable adjustment of a favourable operating point for the colour signal output amplifiers with the transistors 431 and 433 because the permissible voltages for the transistors used at present are not yet sufficiently high. Should this be the case, said variable resistors might be omitted, if desired.
It will be evident that, if desired, the reference level control voltages obtained from the storage circuits 163, 165, 167 may affect the settings of the other electrodes of the guns of the display tube 21 in order to enable the beam currents to be maintained constant when driving the guns with a reference level. To influence the Wehnelt electrode as is the case in the present embodiment, the reference level control voltages may alternatively be applied to other points in the circuit such as, for example, in the colour difference signal circuits prior to combination with the luminance signal channel.
The measuring circuit 187 may, for example, alternatively have an input bridged by a switching transistor instead of by the diode 194.
It is obvious that the term multi-gun colour display tube also includes an assembly of several individual display tubes co-operating in the specified manner.
In the favourable embodiment described above the display tube is used as an input sequence switch for the measuring circuit. It is evident that, if desired, a cathode resistor may be included in each of the cathode circuits of the display tube, in which case a separate input sequence switch may be provided between the cathodes and the input of the measuring circuit.
If no sequence circuit is used in the measuring circuit the control systems must be and must remain mutually equal and they must control the relevant beam current control circuits to the same reference level to enable an advantageous use of the measure according to the invention.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Television display apparatus including a beam current clamping control circuit:
A beam current clamping control circuit in which in case of a too large deviation of the desired value of the field frequency measured beam current an accelerated correction of this deviation is effected.
1. Television display apparatus including a beam current clamping control circuit having a beam current measuring circuit operable by a pulse generator and coupled to a television display tube for measuring, during at least part of a line scan time of a field blanking time a beam current reference level to be corrected, a level insertion circuit for inserting the reference level during the measuring time into a video signal to be applied to the television display tube and a level correction circuit coupled to an output of the measuring circuit and to a control electrode of the television display tube, the measuring circuit including a threshold circuit and a storage circuit, characterized in that the threshold circuit is a circuit which applies a signal to an output thereof when a too large beam current occurs, said output being coupled to an operation signal input of a circuit means for extending the charge correction time of the storage circuit per field period.
2. Television display apparatus as claimed in claim 1, characterized in that the circuit extending the charge correction time is a circuit means for increasing the measuring frequency, whereby a greater number of measurements per unit time is effected.
3. Television display apparatus as claimed in claim 1, characterized in that the circuit extending the charge correction time is a change-over switch a first input of which is coupled to an input of the measuring circuit, a second input is coupled to a beam current independent charging circuit coupled to a supply source and an output is coupled to the storage circuit.
4. Television display apparatus as claimed in claim 1, characterized in that the pulse generator includes a counting circuit having a feedback which can be switched on by the threshold circuit.
5. A beam current clamping control circuit for a television display tube comprising a beam
current measuring circuit means for measuring during at least part of a line scan time of a field blanking time a beam current reference level to be corrected, a pulse generator coupled to said measuring circuit, a level insertion circuit means coupled to said pulse generator for inserting the reference level during the measuring time into a video signal to be applied to the television display tube, a level correction circuit coupled to an output of the measuring circuit, the measuring circuit including a threshold circuit means for coupling to said tube for applying a signal to an output thereof when a beam current above a selected value occurs, a storage circuit, and a circuit means for extending the charge correction time of the storage circuit per field period having an input coupled to said threshold circuit output and an output coupled to said storage circuit.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I On-screen channel display:An on-screen television display including means internally of the receiver for generating characters to indicate the channel number, time of day or other data. The system includes circuit means responsive to the horizontal and vertical sync signals of a television receiver for positioning and timing of the display. BCD data is coupled to a character generator, and the output of the character generator is then multiplexed with positioning and timing signals. The multiplexed output is coupled to a video interface which supplies the video signal to the cathode ray tube.
1. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
2. A display system in accordance with claim 1 wherein said decoding means comprises a seven segment decoder.
3. A display system in accordance with claim 2 wherein a line counter is provided to count horizontal scans of the cathode ray beam and wherein the output of said counter is coupled to said multiplexer to control the same.
4. A display system in accordance with claim 1 wherein said decoder is a seven segment decoder and wherein means are provided to gate the data output of said decoder which represent the vertical segments of the character to be displayed during given horizontal scans of the beam of the cathode ray tube.
5. A system ,in accordance with claim 1 including timing circuit means, means for multiplexing coded data representing each of said characters in accordance with timing signals from said timing circuit means, a seven segment decoder for decoding said multiplexed data, and means for using said decoded data to apply a video signal to the cathode ray tube of the television receiver.
6. A display system in accordance with claim 5 wherein there is provided an oscillator, means for keying the operation of the oscillator to the horizontal sync of the television receiver, and a counter for counting an output of said oscillator and for producing said timing signals.
7. A channel number display system in accordance with claim 6 wherein said data multiplexer has units digits gates and tens digits gates, said timing signal multiplexing data between said units and tens digits gates into at least four output lines, and means for coupling said multiplexed data to inputs of said seven segment decoder.
8. A channel number display system in accordance with claim 7 wherein means are provided to blank the display system output for a time interval between the switching of said data multiplexer from the units digits gates to the tens digits gates to provide spacing between the units and tens characters on theraster of the cathode ray tube.
9. A channel number display system in accordance with claim 8 wherein select means are provided to select one of a greater number of variable character displays, said means including a BCD signal responsive select circuit.
10. A channel number display system in accordance with claim 9 wherein said select means includes a four-six character select circuit for selecting either four or six character display.
11. A system for displaying a character on the raster of a television receiver comprising: means for developing coded data indicative of the character to be displayed, a seven segment decoder, means for coupling the coded data to the input of the seven segment decoder, means for using the output of the seven segment decoder to illuminate a seven segment display on the raster of a cathode ray tube, and wherein three outputs of the seven segment decoder represent the horizontal segments of the character to be displayed and the remaining four outputs represent the vertical segments thereof, and wherein there is provided a multiplexer, a horizontal scan counter, means for coupling the counter outputs to the multiplexer, means for coupling the three horizontal segment outputs to the multiplexer, a timing counter, means for using the timing counter to gate the four vertical segment outputs during each scan associated with the character display, and means for coupling the four gated vertical segment outputs to the multiplexer.
12. A display system in accordance with claim 11 wherein there is provided an oscillator, means for keying the oscillator to the horizontal scan of the cathode ray beam, said oscillator having a frequency substantially higher than the horizontal line frequency of the cathode ray tube, means for coupling the output of the oscillator to the timing counter to control the same.
13. A display system in accordance with claim 12 wherein means are provided to use the horizontal sync signal of the television receiver to enable said timing counter.
14. Apparatus for use with a television receiver, said receiver comprising a horizontal scanning circuit, a vertical scanning circuit, a video signal circuit, and a display device coupled to said scanning and video signal circuits, and creating a character on said display device in the form of line segments oriented in generally horizontal and vertical directions and superimposed over other information displayed thereon and comprising:
data means for developing coded data indicative of the character to be displayed;
decoding means having a plurality of outputs and producing at each of said outputs a signal representative of the presence of a corresponding line segment in the character to be displayed;
an oscillator coupled to said horizontal scanning circuit and synchronized to the operation of said horizontal scanning circuit and producing a signal at a frequency greater than the horizontal scanning frequency;
counting means coupled to the output of said oscillator and developing signals representative of the position of the horizontal scan;
gating means coupled to said decoding means and said counting means and gating said signals representative of the presence of a corresponding generally vertical line segment in response to the position of the horizontal scan;
matrix means for matrixing said gated signals representative of the presence of corresponding generally vertical line segments and said signals representative of corresponding generally horizontal line segments to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a horizontal scan;
signal selection means for selecting one of said line signals in accord with the position of the vertical scan; and
combining means coupled to said video signal circuit for combining said selected line signal with a signal representative of said other information displayed on said display device.
15. The apparatus of claim 14 wherein said character is displayed in the form of the presence or absence of seven line segments and said decoding means comprises a seven segment decoder having seven outputs and producing at each of said outputs a signal representative of the presence of a corresponding one of said seven line segments in the character to be displayed.
16. The apparatus of claim 14 creating at least two characters on said display device wherein said data means develops coded data indicative of the characters to be displayed and said apparatus further comprises multiplex means coupled to said data means, said decoding means and said counting circuitry for applying to said decoding means coded data indicative of different characters to be displayed in response to the position of the horizontal scan.
17. The apparatus of claim 16 further comprising means for preventing the display of said characters for a time interval including the switching of said multiplex means to provide spacing between said characters.
18. The apparatus of claim 14 further comprising a time delay circuit coupled between said oscillator and said horizontal scanning circuit and preventing the operation of said oscillator until a predetermined time period has elapsed following the commencement of a horizontal scan.
19. Apparatus for use with a television receiver, said receiver comprising a first scanning circuit for scanning in a first direction, a second scanning circuit for scanning in a second direction generally perpendicular to said first direction, a video signal circuit, and a display device coupled to said scanning and video signal circuits, and creating a character on said display device in the form of line segments oriented in generally said first and second directions and superimposed over other information displayed thereon and comprising:
data means for developing coded data indicative of the character to be displayed;
decoding means having a plurality of outputs and producing at each of said outputs a signal representative of the presence of a corresponding line segment in the character to be displayed;
timing and gating means coupled to said decoding means and said first scanning circuit and gating said signals representative of the presence of a corresponding line segment in said second direction in response to the position of the scan in said first direction;
matrix means for matrixing said gated signals representative of the presence of corresponding line segments in said second direction and signals representative of corresponding line segments in said first direction to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a scan in said first direction;
signal selection means for selecting one of said line signals in accord with the position of the scan in said second direction; and
combining means coupled to said video signal circuit for combining said selected line signal with a signal representative of said other information displayed on said display device.
20. A system for displaying at least two characters on the raster of a television receiver comprising: an oscillator, means for keying the operation of the oscillator to the horizontal sync of the television receiver, a counter for counting an output of said oscillator and for producing timing signals, means for developing and multiplexing coded data representing each of said characters to be displayed in accordance with said timing signals, a seven segment decoder having a plurality of inputs and outputs for developing signals on a predetermined combination of said outputs in response to each selected coded input, means for coupling the coded data to given inputs of said decoder, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal, and means for adding the generated video signal in the television receiver video circuit to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
21. A channel number display system in accordance with claim 20 wherein said data developing and multiplexing means has units digits gates and tens digits gates, said timing signal multiplexing data between said units and tens digits gates into at least four output lines, and means for coupling said multiplexing data to inputs of said seven segment decoder.
22. A channel number display system in accordance with claim 21 wherein means are provided to blank the display system output for a time interval between the switching of said data developing and multiplexing means from the units digits gates to the tens digits gates to provide spacing between the units and tens characters on the raster of the cathode ray tube.
23. A channel number display system in accordance with claim 22 wherein select means are provided to select one of a greater number of variable character displays, said means including a BCD signal responsive select circuit.
24. A channel number display system in accordance with claim 23 wherein said select means includes a four-six character select circuit for selecting either four or six character display.
25. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
26. A display system in accordance with claim 25 wherein said circuit means further comprises counting means coupled to the output of said oscillator and developing signals indicative of the horizontal position of the beam of the cathode ray tube of said broadcast television receiver.
27. A display system in accordance with claim 26 further comprising means coupled to the horizontal scan circuitry of said broadcast television receiver and said counting means for resetting said counting means.
28. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver, means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
29. A display system in accordance with claim 28 wherein said decoding means comprises a seven segment decoder.
30. A display system in accordance with claim 28 wherein a line counter is provided to count horizontal scans of the cathode ray beam and wherein the output of said counter is coupled to said multiplexing means to control the same.
31. A display system in accordance with claim 30 further comprising means coupled to the horizontal scan circuitry of said broadcast television receiver and said counting means for resetting said counting means.
32. A system for displaying a character indicative of the channel being received on the picture display device of a broadcast television receiver comprising: means for developing data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling said data to inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each data input, circuit means for processing the signal on said outputs of said decoder into a video signal for generating a line segment character and including an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for adding said video signal to other video signals being processed by said broadcast television receiver to develop a character display on said picture display device.
33. A system for displaying a character indicative of the channel being received on the picture display device of a broadcast television receiver comprising: means for developing data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling said data to inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each data input, circuit means for processing the signal on said outputs of said decoder into a video signal for generating a line segment character and including an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization circuitry of said broadcast television receiver for keying said oscillator, and means for adding said video signal to other video signals being processed by said broadcast television receiver to develop a character display on said picture display device.
The use of on-screen display of a channel number, for instance, has been proposed in an article entitled, "Broadcast and Television Receivers" IEEE, Vol. BTR-15, No. 2, July 1969, however, the character generators which are available commercially are generally "read only memories" designed to display either 16 or 64 alpha-numeric characters. These character generators require 350 memory bits for 10 characters. In such a device, all 35 possible positions in a 5 × 7 font are used for the numerals. The character generator is the most expensive element of such a system.
A Co-pending Patent Application of Ralph Joseph Ludlam entitled, "Electronic Channel Selection & Device", Ser. No. 265,231, now abandoned, describes a system for producing digital information representative of a selected channel. This data may be used by the display system of the present invention.
FIELD OF THE INVENTION
The field of art to which this invention pertains is on-screen display of characters in a television receiver with character generation locally in the receiver.
SUMMARY OF THE INVENTION
It is an important feature of the present invention to provide an improved system for the display of characters on the screen of a television receiver using character generating means locally in the receiver.
It is another feature of the present invention to provide a relatively inexpensive means for generating characters in a system as described above.
It is a principal object of the present invention to provide an on-screen character display system for a television receiver which utilizes a character generator having a segment decoder for transforming digital information into line segment information and having means for gating and multiplexing the line segment information into a usable video output signal.
It is a further feature of the present invention to provide a character generator described above including a seven segment decoder having direct coupling from the output of the decoder to a multiplexing stage for the horizontal segments of each character and having coupling to the multiplexer through a gating circuit for the vertical segments of the character.
It is a further feature of the present invention to provide a circuit as described above which includes a vertical and horizontal delay means as well as vertical and horizontal blanking means to properly position the characters at a predetermined location on the screen of the television receiver.
It is an additional feature of the present invention to provide a circuit as described above which includes means for blanking the character generating portion of the video signal between characters to provide adequate spacing.
It is also an object of this invention to provide circuit means for generating additional characters such as characters to indicate the time of day on the screen of a television receiver.
Walker, "For TV Tuners a Digital Look", Electronics, Jun. 26, 1975, pp. 65-66.
Evans et al., "Direct Address Television Tuning and Display System Using Digital MOS Large Scale Integration", IEEE Transactions on Consumer Electronics, vol. CE-22, No. 4, pp. 267-288, Nov. 1976.
Electronics, vol. 48, No. 24, Nov. 27, 1975, "Philips TV Set Indicates Station Tuning and Color Settings on Screen", pp. 6E and 8E.
Werner, "Linear Color Bar Display for CTV Sets", Radio Mentor Electronic, vol. 41, No. 9, pp. 350-351, Sep. 1975.
Programmable television receiver controllers which may be manually programmed by a user to select or to limit the viewing selections for random times, typically in one-half hour intervals, throughout a predetermined time period such as a one week time period. Program selections may be made by setting suitable controls for the day, AM or PM, the half hour of the day and the channel desired, and entered into a memory by a push-button control. Thereafter a digital control clock automatically selects the pre-entered information at the appropriate times and provides a control signal which may be used to automatically select the identified channels to the exclusion of all others. Alternatively, the signal may be used to exclude the selected channel from selection manually. In one embodiment, the programmable controller is incorporated in the original design of the television receiver and in a second embodiment, an external controller is disclosed which can be attached to the antenna terminals of a conventional television. Additional embodiments include means for controlling other functions such as the ON-OFF function of the receiver.
1. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address for application to said memory means means for generating said write-addresses;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and
control means for controlling the reception of a television receiver according to said data read from said memory means.
2. The controller of claim 1 wherein said memory means is a semiconductor memory. 3. The controller of claim 1 wherein said storing means includes a means for generating said write-addresses which is responsive to the position of at least one first switch and a means for generating said data corresponding to channel selections which is responsive to the position of at least one second switch. 4. The controller of claim 1 wherein said controller means controls the reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 5. A programmable television controller comprising: random-access memory means for storing data;
data means for selectively generating data corresponding to a television channel;
write-address means selectively generating a write-address corresponding to a future time for application to said memory means;
program means for selectively storing said data in said memory means at said write-address;
read-address means for generating said read-addresses responsive to real time;
memory read means for applying said read-addresses to said memory means for reading out said data stored in said memory means; and
control means for controlling the reception of a television receiver according to said data read from said memory means.
6. The controller of claim 5 wherein said memory means is a semiconductor memory. 7. The controller of claim 5 wherein said data means comprises at least one switch. 8. The controller of claim 5 wherein said write-address means comprises at least one switch. 9. The controller of claim 5 wherein said program means comprises:
means for normally coupling said read-address means to said memory;
means for normally placing said memory in a read mode;
switching means for momentarily decoupling the read-address means from said memory means, coupling said write-address means to said memory means, and switching said memory means from said read mode to a write mode.
10. The controller of claim 5 wherein said read-addresses are binary coded signals which increment on one-half hour intervals. 11. The controller of claim 5 wherein said control means controls said reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 12. The controller of claim 5 wherein said control means controls the reception of said television receiver by limiting the reception to a channel other than the channel corresponding to said data received from said memory means if said data is present. 13. The controller of claim 5 wherein said control means includes a pretuner means having at least one input for coupling to a television receiver antenna and a pretuner output for coupling to an input on a television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal. 14. The controller of claim 13 wherein said control means further includes a disable means for disabling said control means thereby preventing reception of any channel when a power source powering said controller is interrupted, said disable means continuing to disable said controller until said disable means is reset. 15. The controller of claim 13 wherein said controller is installed within a controller housing, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller. 16. The controller of claim 13 wherein said pretuner output is for coupling to an antenna input on the television receiver and the frequency of said fixed frequency signal corresponds to a predetermined television signal. 17. The controller of claim 13 wherein said pretuner output is for coupling to an input of an intermediate frequency amplifier stage in the television receiver and the frequency of said fixed frequency signal corresponds to the intermediate frequency amplifier stage frequency of operation. 18. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address means for generating said write-addresses for application to said memory means;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and,
control means for controlling the reception of a television receiver according to said data read from said memory means, said control means including a pretuner means having at least one input for coupling to a television receiver antenna and pretuner output for coupling to an input on the television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal;
a controller housing for housing said controller, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller.
1. Field of the Invention
The present invention relates to the field of automatic controllers, and more particularly, to programmable controllers for use with television receivers and like equipment.
2. Prior Art
Many systems have been proposed for the automatic control of television receivers, that is, automatic channel selection for particular times of the day based upon programming information entered into the controller at some previous time. Most of these systems, however, are in substantial part mechanical systems which are not particularly easy to program, thereby being relatively expensive to manufacture and difficult to use. Accordingly, such systems have not enjoyed significant commercial use on conventional receivers.
Simple programmable television receiver controllers would provide a number of advantages over conventional channel selectors, and even over remote controlled channel selectors for a number of reasons. There may be programs of particular merit or interest which a viewer does not want to miss. However, the viewer's attention may inadvertently be drawn to another channel at the time, thereby failing to change channels to the more desirable program at the appropriate time. Also at the present time, a number of programs and movies being shown on T.V. are directed toward an adult audience, which programs may be undesirable or outright unsuitable for viewing by children, a situation which may only be expected to increase in the future. In addition, more andmore homes have at least one television receiver controllable at least a substantial amount of the time by children, whereby with conventional channel selectors the "viewers discretion" cannot be exercised by a parent. Accordingly, aprogrammable controller could be programmed periodically, such as once a week, so that those programs of highest merit or viewer interest, will be automatically selected and/or predetermined unobjectionable programs will be selected at times when objectionable programming is being televised on other channels. As an alternative, of course, objectionable programming itself could be programmed for the purposes of locking out such programs from the viewer's selections, e.g., eliminating such programming from the channel selections accessible from the manual channel selector.
U.S. Pat. Nos. 3,215,798 and 3,388,308 disclose automatic television programming systems of the mechanical or electromechanical type, whereby a rotary device mechanically tied to a time clock is programmed to provide some physical movement indicative of the channel to be selected at that time. Devices of the same general type involving some form of motor driven switching unit are also disclosed in U.S. Pat. Nos. 2,755,424, 3,496438, and 3,569,839. In all of these patents the mechanical complexity of the system disclosed is believed to preclude the widespread adoption thereof on receivers intended for consumer use. Further, most of these systems are operative on a number of switching signals equal to the number of selections desired, though some coding to somewhat reduce the complexity of such systems is known, such as that in U.S. Pat. No. 3,496,438. Also, obviously timing mechanisms or the electromechanical type for various other applications are also known, that disclosed in U.S. Pat. No. 3,603,961 being but one example of such devices.
BRIEF SUMMARY OF THE INVENTION
Programmable television receiver controllers which may be manually programmed by a user to select or to limit the viewing selections for random times, typically in one-half hour intervals, throughout a predetermined time period such as a one week time period. Program selections may be made by setting suitable controls for the day, A.M. or P.M., the half hour of the day and the channel desired, and entered into a memory by a push-button control. Thereafter a digital control clock automatically selects the pre-entered information at the appropriate times and provides a control signal which may be used to automatically select the identified channels to the exclusion of all others. Alternatively, the signal may be used to exclude the selected channel from selection manually. In one embodiment, the programmable controller is incorporated in the original design of the television receiver and in a second embodiment an external controller is disclosed which may be attached to the antenna terminals of a conventional television. Additional embodiments include means for controlling other functions such as the ON-OFF function of the receiver.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION Gain control arrangement useful in a television signal processing system
In a color television receiver, first and second amplifiers are respectively included in the luminance and chrominance channels to permit control of contrast and saturation. The amplifiers have gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. A first potentiometer is coupled between a source of fixed voltage equal to the extrapolated cut off voltage of the first amplifier and a gain controlling voltage source. The gain controlling voltage may be produced by a circuit including an element responsive to ambient light. The wiper of the first potentiometer is coupled to the first amplifier to couple a voltage developed at a predetermined point of the first potentiometer to the first amplifier to control its gain. A second potentiometer is coupled between a source of voltage equal to the extrapolated cut off voltage of the second amplifier and the gain controlling voltage source to receive a portion of the gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the first and second amplifiers. The wiper of the second potentiometer is coupled to the second amplifier to couple a voltage developed at a predetermined point of the second potentiometer to the second amplifier to control its gain. In this manner, the contrast of the receiver may be varied over a relatively wide range while saturation is maintained substantially constant.
1. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut-off at predetermined voltages which may or may not be the same voltage;
a gain controlling voltage source;
means for coupling said gain controlling voltage to said first amplifier to control its gain;
potentiometer means coupled between a fixed voltage substantially equal to the extrapolated cut-off voltage of said second amplifier and to said gain controlling voltage source to recieve a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut-off voltages of said first and second amplifiers; and
means for coupling a voltage developed at a predetermined point on said potentiometer means to said second amplifier to control its gain.
2. The apparatus recited in claim 1 wherein said means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut-off voltage of said first amplifier and said gain controlling voltage source. 3. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain control voltage characteristics including linear portions extrapolated to cut-off at substantially the same predetermined voltage;
a source of gain controlling voltage; and
means for coupling said gain controlling voltage to said first and second amplifiers.
4. Apparatus comprising:
first variable gain amplifying means for amplifying a first signal in response to a first DC control signal, said first amplifying means having a first gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to VO ;
second variable gain amplifying means for amplifying a second signal in response to a second DC control signal, said second amplifying means having a second gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to AVO, where A is a number greater than 0;
a first source of fixed voltage substantially equal to VO ;
a second source of fixed voltage substantially equal to AVO ;
means for developing a third DC control voltage v;
means for developing a portion Av of said third control voltage v;
first means for deriving said first control voltage including means for providing the difference between said third control voltage v and said fixed voltage VO and means for adding a predetermined portion of the difference between said third control voltage v and said fixed voltage VO to said DC control voltage v; and
second means for deriving said second control voltage including means for providing the difference between a portion Av of said third control voltage v and said fixed voltage AVO and means for adding a predetermined portion of the difference between said portion Av and said fixed voltage AVO to said DC control voltage v.
5. The apparatus recited in claim 4 wherein A is equal to 1. 6. The apparatus recited in claim 4 wherein said first amplifying means is included in a luminance channel of a televeision signal processing system and said second amplifying means is included in a chrominance channel of said television signal processing system. 7. The apparatus recited in claim 6 wherein means for developing said third control voltage includes means responsive to ambient light. 8. The apparatus recited in claim 4 wherein said first means includes first voltage divider means coupled between said fixed voltage VO and said third DC control voltage v; and wherein said second means includes second voltage divider means coupled between said fixed voltage AVO and said portion Av. 9. The apparatus recited in claim 8 wherein said first voltage divider means includes a first potentiometer, said first potentiometer having a wiper coupled to said first amplifying means; and wherein said second voltage divider means includes a second potentiometer, said second potentiometer having a wiper coupled to said amplifying means. 10. The apparatus recited in claim 4 wherein said second gain versus DC control voltage characteristic includes a region between said voltage AVO and a voltage VB where the gain is greater than 0, said voltage VB being substantially equal to the voltage at which said second amplifying means has a gain substantially equal to 0; and wherein said second source of fixed voltage includes means for coupling said voltage VB to said second amplifying means. 11. The apparatus recited in claim 10 wherein said second source of said voltage AVO includes a third source of fixed voltage VB ; potentiometer means coupled between said third source of fixed voltage VB and said means for developing said third DC control voltage; and means coupled to said potentiometer means for developing said voltage AVO at a point along said potentiometer means; said potentiometer means including a wiper coupled to said second amplifier means, said wiper being adjustable to couple a DC voltage VFB and said third control voltage to said second amplifying means.
The present invention pertains to gain controlling apparatus and particularly to apparatus for controlling the gains of amplifiers included in the luminance and chrominance channels of a television signal processing system.
Recently, the maximum brightness available from television receivers has increased sufficiently so that a pleasing image may be reproduced under conditions of high ambient light as well as under conditions of low ambient light. Apparatus is known for automatically controlling the contrast and brightness properties of a television receiver in response to ambient light to provide a pleasing image over a range of ambient light conditions. Such apparatus is described in U.S. Pat. Nos. 3,027,421, entitled "Circuit Arrangements For Automatically Adjusting The Brightness And The Contrast In A Television Receiver," issued to H. Heijligers on Mar. 27, 1962 and 3,025,345, entitled "Circuit Arrangement For Automatic Readjustment Of The Background Brightness And The Contrast In A Television Receiver," issued to R. Suhrmann on Mar. 13, 1962.
Apparatus is also known for automatically controlling the contrast and saturation properties of a color television receiver by controlling the gains of luminance and chrominance channel amplifiers, respectively, in response to ambient light. Such apparatus is described in U.S. Pat. Nos. 3,813,686 entitled "Ambient Light Responsive Control Of Brightness, Contrast And Color Saturation," issued to Eugene Peter Mierzwinski, on May 28, 1974 and 3,814,852 entitled "Ambient Light Responsive Control Of Brightness, Contrast and Color Saturation," issued to Eugene P. Mierzwinski on June 4, 1974.
Also of interest is apparatus for manually controlling the gains of luminance and chrominance channel amplifiers. Such apparatus is described in U.S. Pat. Nos. 3,374,310, entitled "Color Television Receiver with Simultaneous Brightness and Color Saturation Controls," issued to G.L. Beers on Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic Control Circuit," issued to DuMonte O. Voigt on June 7, 1966; and 3,715,463, entitled "Tracking Control Circuits Using a Common Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When the gain of luminance channel is adjusted to control the contrast of an image, either manually or automatically, in response to ambient light, it is desirable to simultaneously control the gain of the chrominance channel in such a manner that the ratio of the gains of the luminance and chrominance channels is substantially constant over a wide range of contrast control to maintain constant saturation. If the proper ratio between the amplitudes of the chrominance and luminance signals is not maintained incorrect color reproduction may result. For instance, if the amplitude of the luminance signals are increased without correspondingly increasing the amplitude of the chrominance signals, colors may become desaturated, i.e., they will appear washed out or pastel in shade. Furthermore, it may be desirable to provide controls for presetting the gains of the luminance and chrominance channels to compensate for tolerance variations in other portions of the television signal processing apparatus.
In accordance with the present invention, apparatus is provided which may be utilized in a color television receiver to control contrast over a relatively wide range while maintaining constant saturation. The apparatus includes first and second amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. Means couple a gain controlling voltage source to the first amplifier to control its gain. Potentiometer means are coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of the second amplifier and the source of gain controlling voltage to receive a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the amplifiers. A voltage developed at a predetermined point along the potentiometer means is coupled to the second amplifier to control its gain.
In accordance with another feature of the present invention, the means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of said first amplifier and said gain controlling voltage source.
In accordance with still another feature of the present invention the gain controlling voltage source includes an element responsive to ambient light .
These and other aspects of the present invention may best be understood by references to the following detailed description and accompanying drawing in which:
FIG. 1 shows the general arrangement, partly in block diagram form and partly in schematic diagram form, of a color television receiver employing an embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG. 2 shows graphical representation of gain versus control voltage characteristics of amplifiers utilized in the embodiment shown in FIG. 1;
FIG. 3 shows graphical representations of gain versus control voltage characteristics of amplifiers which may be utilized in the receiver shown in FIG. 1;
FIG. 4 shows, in schematic form, another embodiment of the present invention which may be utilized to control the amplifiers whose gain versus control voltage characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now
to FIG. 1, the general arrangement of a color television receiver employing the present invention includes a video signal processing unit 112 responsive to radio frequency (RF) television signals for generating, by means of suitable intermediate frequency (IF) circuits (not shown) and detection circuits (not shown), a composite video signal comprising chrominance, luminance, sound and synchronizing signals. The output of signal processing unit 112 is coupled to chrominance channel 114, luminance channel 116, a channel 118 for processing the synchronizing signals and a channel (not shown) for processing sound signals.
Chrominance processing channel 114 includes chrominance processing unit 120 which serves to remove chrominance signals from the composite video signal and otherwise process chrominance signals. Chrominance signal processing unit 120 may include, for example, automatic color control (ACC) circuits for adjusting the amplitude of the chrominance channels in response to amplitude variations of a reference signals, such as a color burst signal, included in the commposite video signal. Chrominance signal processing circuits of the type described in the U.S. Pat. No. 3,740,462, entitled "Automatic Chroma Gain Control System," issued to L.A. Harwood, on June 19, 1973 and assigned to the same assignee as the present invention are suitable for use as chrominance processing unit 120.
The output of the chrominance signal processing unit 120 is coupled to chrominance amplifier 122 which serves to amplify chrominance signals in response to a DC signal vC generated by gain control network 142. As illustrated, chrominance amplifier 122 provides chrominance signals to a chroma demodulator 124. An amplifier suitable for use as chrominance amplifier 122 will subsequently be described with reference to FIG. 6.
Chroma demodulator 124 derives color difference signals representing, for example, R-Y, B-Y and G-Y information from the chrominance signals. Demodulator circuits of the general type illustrated by the chrominance amplifier CA 3067 integrated circuit manufactured by RCA Corporation are suitable for use as chrominance demodulator 124.
The color difference signals are applied to a video driver 126 where they are combined with the output signals -Y of luminance channel 116 to produce color signals of the appropriate polarity, representing for example, red (R), green (G) and blue (B) information. The color signals are coupled to kinescope 128.
Luminance channel 116 includes a first luminance signal processing unit 129 which relatively attenuates undesirable signals, such as chrominance or sound signals or both, present in luminance channel 116 and otherwise processes the luminance signals. The output of first luminance processing unit 129 is coupled to luminance amplifier 130 which serves to amplify the luminance signals in response to a DC control signal vL generated by gain control unit 142 to thereby determine the contrast of a reproduced image. An amplifier suitable for use as luminance amplifier 130 will subsequently be described with reference to FIG. 5. The output of luminance amplifier 130 is coupled to second luminance signal processing unit 132 which serves to further process luminance signals. A brightness control unit 131 is coupled to luminance signal processing unit 132 to control the DC content of the luminance signals. The output -Y of luminance processing unit 132 is coupled to kinescope driver 126.
Channel 118 includes a sync separator 134 which separates horizontal and vertical synchronizing pulses from the composite video signal. The synchronizing pulses are coupled to horizontal deflection circuit 136 and vertical deflection circuit 138. Horizontal deflection circuit 136 and vertical deflection circuit 138 are coupled to kinescope 128 and to a high voltage unit 140 to control the generation and deflection of one or more electron beams generated by kinescope 128 in the conventional manner. Deflection circuits 136 and 138 also generate horizontal and vertical blanking signals which are coupled to luminance signal processing unit 132 to inhibit its operation during the horizontal and vertical retrace intervals.
Gain control unit 142 is coupled to luminance amplifier 130 and to chrominance amplifier 122 to control their gains. Gain control unit 142 includes a PNP transistor 152 arranged as an emitter-follower amplifier. The collector of transistor 152 is coupled to ground while its emitter is coupled through a series connection of a potentiometer 156 and fixed resistor 154 to a source of positive supply voltage VO. The wiper of potentiometer 156 is coupled to luminance amplifier 130. The series connection of a potentiometer 158 and a variable resistor 159 is coupled between the source of positive supply voltage VO and the emitter of transistor 152. The wiper of potentiometer 158 is coupled to chrominance amplifier 122.
The base of transistor 152 is coupled to the wiper of a potentiometer 146. One end of potentiometer 146 is coupled to the source of positive supply voltage VO through a fixed resistor 144. The other end of potentionmeter 146 is coupled to ground through a light dependent resistor (LDR) 148. LDR 148 is a resistance element whose impedance varies in inverse relationship with light which impinges on it. LDR 148 may comprise a simple cadmium sulfide type of light dependent element or other suitable light dependent device. LDR 148 is desirably mounted to receive ambient light in the vicinity of the screen of kinescope 128.
A single pole double-throw switch 150 has a pole coupled to the junction of potentiometer 146 and LDR 148. A resistor 151 is coupled between the wiper of potentiometer 146 and the other pole of switch 150. The arm of switch 150 is coupled to ground.
The general arrangement shown in FIG. 1 is suitable for use in a color television receiver of the type shown, for example, in RCA Color Television Service Data 1973 No. C -8 for a CTC-68 type receiver, published by RCA Corporation, Indianapolis, Indiana.
In operation, gain control circuit 142 maintains the ratio of the gain of chrominance amplifier 122 to the gain of amplifier 130 constant in order to maintain constant saturation while providing for contrast adjustment either manually by means of potentiometer 146 or automatically by means of LDR 148. If the gain of luminance were adjusted to control the contrast of an image without a corresponding change in the gain of chrominance amplifier 122, the amplitudes of luminance signals -Y and color difference signals R-Y, B-Y and G-Y would not, in general, be in the correct ratio when combined by divider 126 to provide the desired color.
When switch 140 is in the MANUAL position, the gains of chrominance amplifier 122 and luminance amplifier 130 are controlled by adjustment of the position of potentiometer 146. When switch 150 is in the AUTO position the gain of the chrominance amplifier 122 and luminance amplifier is automatically controlled by the response of LDR 148 to ambient light conditions. The voltage developed at the wiper of potentiometer 146 (base of transistor 152) when switch 150 is in the AUTO position is inversely related to the ambient light recieved by LDR 148. It is noted that the values of resistors 114, potentiometer 146, LDR 148 and resistor 151 are desirably selected such that the adjustment of the wiper arm of potentiometer 146 when switch 150 is in the MANUAL position does not substantially affect the voltage developed at the base of transister 152 when switch 150 is placed in the AUTO position.
The control voltage v developed at the wiper arm of potentiometer 146 is coupled through emitter-follower transistor 152 to the common junction of potentiometer 156 and variable resistor 159. A control voltage vL comprising v plus a predetermined portion of the difference VO -v developed across the series connection of fixed resistor 154 and potentiometer 156, depending on the setting of potentiometer 156, is coupled to luminance amplifier 130 to control its gain. Similarly, a control voltage vC comprising v plus a predetermined portion of the difference voltage VO -v developed across the series connection of potentiometer resistor 158 and variable resistor 159, depending on the setting of the wiper of potentiometer 158, is coupled to chrominance amplifier 122 to control its gain.
The gain of luminance amplifier 130 may be pre-set to a desired value by the factory adjustment of potentiometer 156. Similarly, variable resistor 159 is provided to allow factory pre-set of the gain of the chrominance amplifier 122. Potentiometer 158 is provided to allow customer control of saturation.
R
eferring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (gC) and luminance amplifier 130 (gL) are shown. The characteristic gC has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of gC intersects the GAIN axis at GC and intersects the CONTROL VOLTAGE axis at VO. Similarly, the characteristics gL has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of gL intersects the GAIN axis at GL and intersects the CONTROL VOLTAGE axis at VO.
From FIG. 2, the expression for linear portion 212 of gL is ##EQU1## The expression for linear portion 214 of gC is ##EQU2## From FIG. 1, the expression for vL is vL = v + (VO -v) K1 [3]
where K1 is determined by the voltage division of fixed resistor 154 and potentiometer 156 at the wiper of potentiometer 156. When the wiper of potentiometer 156 is at the emitter of transistor 152, K1 =0. The expression for vC is vC = v + (VO -v)K2 [4]
where K2 is determined by the voltage division of potentiometer 158 and fixed resistor 159 at the wiper of potentiometer 158. By combining equations [1] and [3], the equation for gL becomes ##EQU3## By combining equations [2] and [4], the equation for gC becomes ##EQU4## The ratio of gL to gC is thus ##EQU5## It is noted that this ratio is independent of DC control voltage v. Thus, although DC control voltage v may be varied either manually or in response to ambient light to control the contrast of an image reproduced by kinescope 128, the saturation remains constant.
With re
ference to FIG. 2, it is noted that although the linear portion 214 of gC has an extrapolated gain equal to 0 at a control voltage equal to VO, the non-linear portion of gC does not attain a gain equal to 0 until a control voltage equal to VB. That is, a control voltage of VO will not cut-off chrominance amplifier 122.
In FIG. 1A there is shown, in schematic form, a modification to the arrangement of gain control network 142 of FIG. 1 with provisions which allow a viewer to cut off chrominance amplifier 122 to produce a more pleasing image under conditions of poor color reception due, for example, to noise or interference. The modifications to gain control unit 142 shown in FIG. 1A include coupling potentiometer resistor 158 between a source of positive supply voltage VB, the value of VB being greater than the value of VO, and coupling a resistor 160 from a tap-off point 162 along potentiometer 158 to ground. The value of potentiometer 158 and resistor 160 and the location of tap 162 are selected so that voltage VO is developed at tap 162.
The arrangement shown in FIG. 1A allows for the adjustment of contrast while constant saturation is maintained and additionally allows a viewer, by adjusting the wiper of potentiometer 158 to voltage VB, to cut off chrominance amplifier 122.
Referring to FIG. 3 there are shown gain versus DC control voltage characteristics of chrominance and luminance amplifiers which do not have the same extrapolated linear cut off control voltage. The gain versus control voltage characteristic gL ' of the luminance amplifier has a reverse S-shape characteristic including a linear portion 312. Extrapolated linear portion 312 of gL ' intersects the GAIN axis at a gain GL ' and intersects the CONTROL VOLTAGE axis at a voltage VO '. The gain versus control voltage characteristic gC ' of the chrominance amplifier has a reverse S-shape characteristic having a linear portion 314. Extrapolated linear portion 314 of gC ' intersects the GAIN axis at a gain GC ' and intersects the CONTROL VOLTAGE axis at a voltage AVO ', where A is a number greater than zero.
From FIG. 3, the expression for linear portion 312 of gL ' is ##EQU6## where vL ' is the DC conrol voltage coupled to the luminance amplifier. The expression for linear portion 314 of gC ' is ##EQU7## where vC ' is the DC control voltage coupled to the chrominance amplifier.
A modified form of the control network 142 of FIG. 1 suitable for controlling the gain of a chrominance and a luminance amplifier having characteristics such as shown in FIG. 3 is shown in FIG. 4. Similar portions of FIGS. 1 and 4 are identified by reference numbers having the same last two significant digits and primed (') designations. The modified portions of FIG. 1 shown in FIG. 4 include the series connection resistors 460 and 462 coupled between the emitter of transistor 452 to ground. The values of resistors 460 and 462 are selected so that a portion Av' of the DC control voltage v' developed at the emitter of transistor 452 is developed at the junction of resistors 460 and 462. Furthermore, the series connection of potentiometer 458 and variable resistor 459 is coupled between the junction of resistor 460 and 462 and a source of positive supply voltage AVO '.
From FIG. 4, the expression for control voltage vL ' developed at the wiper of potentiometer 456 is vL ' = v' + (vO '-v')K1 ' [10]
where K1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage vC ' developed at the wiper of potentiometer 458 is VC ' = Av' + (AVO ' - Av')K 2 ' [11]
where K2 ' is determined by the voltage division at the wiper of potentiometer 458. By combining equations [8] and [10], ##EQU8## By combining equations [9] and [11], ##EQU9## The ratio of gL ' to gC ' is given by the expression ##EQU10## It is noted that this ratio is independent of DC control voltage v'. Therefore, gain control network 442 of FIG. 4 also allows for the adjustment of contrast while maintaining constant saturation.
It is noted that if A were made equal to 1, the arrangement gain control unit 442 would be suitable to control the gains of chrominance and luminance amplifiers having the characteristics shown in FIG. 2.
In FIG. 5, there is shown an amplifier suitable for use as luminance amplifier 130 of FIG. 1. The amplifier includes a differential amplifier comprising NPN transistors 532 and 534. The commonly coupled emitters of transistors 532 and 534 are coupled to the collector of an NPN transistor 528. The emitter of transistor 528 is coupled via a resistor 530 to ground. The collector of transistor 532 and the collector of transistor 534, via load resistor 536, is coupled to a bias voltage provided by bias supply 546, illustrated as a series connection of batteries. The bases of transistors 532 and 534 are respectively coupled to a lower bias voltage through resistors 533 and 535 respectively.
An input signal, such as, for example, the output signal provided by first luminance processing circuit 129 of FIG. 1 is coupled to the base of transistor 532 via terminal 542. The output signal of the amplifier is developed at the collector of transistor 534 and coupled to output terminal 544.
A DC control voltage, such as vL provided by gain control unit 142 of FIG. 1, is coupled to the base of an NPN transistor 514, arranged as an emitter-follower, via terminal 512. The collector of transistor 514 is coupled to bias supply 546. The emitter of transistor 514 is coupled to ground through the series connection of resistor 516, a diode connected transistor 518 and resistor 520.
The anode of diode 520 is coupled to the base of an NPN transistor 538. The collector of transistor 538 is coupled to the collector of transistor 534 while its emitter is coupled to ground through resistor 540. Transistor 538, resistor 540, diode 518 and resistor 520 are arranged in a current mirror configuration.
The emitter of transistor 514 is coupled to the base of a PNP transistor 522. The emitter of transistor 522 is coupled to bias supply 546 while its collector is coupled to the base of transistor 528 and to ground through the series connection of a diode connected transistor 524 and resistor 526. Transistor 528, resistor 530, diode 524 and resistor 526 are arranged in a current mirror configuration
In operation, the DC control voltage coupled to terminal 512 is coupled in inverted fashion to the anode of diode 524 by transistor 522. As a result, current directly related to the voltage developed at the anode of diode 524 flows through diode 524 and resistor 526. Due to the operation of the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530, a similar current flows through the emitter circuit of transistor 528. The gain of the differential amplifier comprising transistors 532 and 534 is directly related to this current flowing in the emitter circuit of transistor 528, and therefore is inversely related to the DC control voltage at terminal 512. The gain versus DC control voltage characteristics of the differential is similar to gL shown in FIG. 2.
Further, a current is developed through the series connection of resistor 516, diode 518 and resistor 520 in direct relationship to the DC control coupled to terminal 512. A similar current is developed through resistor 540 due to the operation of the current mirror comprising diode 518, resistor 520, transistor 538 and resistor 540. This current is of the opposite sense to that provided by the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530 and is coupled to the collector of transistor 534 so that the DC voltage at output terminal 544 does not substantially vary with the DC control voltage.
In FIG. 6, there is shown an amplifier suitable for use as chroma amplifier 120 of FIG. 1. The amplifier shown in FIG. 6 is of the type described in U.S. patent application Ser. No. 530,405 entitled "Controllable Gain Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974.
The amplifier comprises a differential amplifier including NPN transistors 624 and 625 having their bases coupled to terminal 603 via a resistor 626. Chrominance signals, provided by a source of chrominance signals such as chrominance processing unit 120 of FIG. 1, are coupled to terminal 603. The current conduction paths between the collectors and emitters of transistors 624 and 625 are respectively coupled to ground via resistors 628, 629 and 630.
A current splitter circuit comprising an NPN transistor 632 and a diode 634 is coupled to the collector of transistor 624. Diode 634 and the base-emitter junction of transistor 632 are poled in the same direction with respect to the flow of collector current in transistor 624. It desirable that conduction characteristics of transistor 632 and diode 635 be substantially matched. Similarly, the collector of transistor 625 is coupled to a second current splitter comprising a transistor 633 and a diode 635.
An output load circuit comprising series connected resistors 636 and 638 is coupled between the collector of transistor 632 and a source of operating voltage provided by bias supply 610. Amplified chrominance signals are provided at output terminal 640 for coupling, for example, to a chroma demodulator such as chroma demodulator 124 of FIG. 1. Similarly, series connected load resistors 637 and 639 are coupled between the collector of transistor 633 and bias supply 610. An output terminal 641 at the junction of resistors 637 ad 639 provides oppositely phased chrominance signals to those provided at terminal 640. The gain associated with the cascode combination of transistors 624 and 632 is controlled in response to a DC control voltage, such as, for example, vC provided by gain control unit 142 of FIG. 1, coupled to the base of an NPN transistor 646 via terminal 602. Direct control current is supplied from the emitter of transistor 646 to diode 634 and 635 via a se
ries resistor 652. A signal by-pass circuit comprising a series resonant combination 654 of inductance and capacitance is coupled from the anode of diode 634 to ground. Resonant circuit 654 is tuned, for example, to 3.58 MHz to provide a low impedance path to ground for color subcarrier signals.
Bias voltages and currents are supplied to the amplifier arrangement by bias supply 610, illustrated as a series connection of batterys. A voltage B+ is coupled to the collector of transistor 646. A lower bias voltage is coupled to the load circuits of transistors 632 and 633. The bases of transistors 632 and 633 are coupled in common to a still lower bias voltage. The bases of transistors 624 and 625 are coupled to a still lower bias voltage via substantially equal in value resistors 658 and 659. A resistor 694 is coupled from the common junction of resistors 658 and 659 to ground.
In operation, a quiescent operating current is provided through resistor 630. In the absence of an input signal at terminal 603, this current will divide substantially equally between the similarly biased transistors 624 and 625. If the DC control voltage at terminal 602 is near ground potential, transistor 646 will be effectively cut off and no current will flow in resistor 652 and diodes 634 and 635. In that case, neglecting the normally small difference betweeen collector and emitter currents of NPN transistors, the collector currents of transistors 624 and 625 will flow, respectively, in transistors 632 and 633. The transistors 632 and 633 are operated in common base mode and form cascode signal amplifiers with respective transistors 624 and 625. With the DC control voltage near ground potential, one-half of the quiescent current from resistor 630 flows in each of the load circuits and maximum gain for chrominance signals supplied from terminal 603 is provided.
Transistor 646 will conduct when the DC control voltage approaches the bias voltage supplied to the bases of transistors 632 and 633 of the current splitters. By selection of the circuit parameters, diodes 634 and 635 may be arranged to operate in a range between cut off to the conduction of all of the quiescent operating current supplied via resistor 630, thereby cutting off transistors 632 and 633 to provide no output signals at terminals 640 and 641.
At a DC control voltage intermediate to that corresponding to cut off of transistors 632 and 633 on the one hand and cut off of diodes 634 and 635 on the other hand, the voltage gain of the illustrated amplifier will vary in a substantially linear manner with the DC control voltage.
It is noted that although the characteristics shown in FIGS. 2 and 3 were reversed S-shaped characteristics, the characteristics could have other shapes including linear portions. For example, the characteristics could be substantially linear. Furthermore, with reference to FIG. 3, although gC ' was shown as having a linear portion that had a cut off control voltage lower than the cut off control voltage of the linear portion of gL ', the cut off control voltage of the linear portion of gC ' could be greater than the cut off voltage for the linear region of gL '. In addition, the gain control units and associate amplifiers could be arranged to utilize voltages opposite in polarity to those shown. These and other modifications are intended to be within the scope of the invention.
Furthermore it has a programmable realtime digital clock which allows to start the tellye at a prefixed time on a prefixed program.
This chassis is even showing the use of the TEXAS INSTRUMENTS TMS1000 used here as a Remote control decoder /receiver plus realtime programmable clock timer feature.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Texas Instruments TMS1000
General
General Information
Texas Instruments was locked in a race with Intel to create the first microprocessor. By most accounts Intel won with the 4004, but there are a few die hard TI fans who say the TMS1000 was first, because it was the first “computer on a chip” and that the 4004 was just a calculator chip.
Texas Instruments followed the Intel 8080 with the 4-bit TMS1000. So, while Intel was leading the industry in microprocessors, TI led with this industry unique design "a computer on a chip", specifically designed for control and automation purposes. The 1000 was the first MCU (MicroComputer Unit) , which is an MPU (MicroProcessor Unit) with other support chips (such as RAM, ROM, counters, timers, I/O interfaces) integrated on to the same silicon chip.
The original 1000 family consists of 6 chips the TMS1000 and TMS1200 are basic chips, the TMS1070 and TMS1270 are high voltage versions to interface to displays, the TMS1100 and TMS1300 provide twice the on-board ROM and RAM. The TMS1000, TMS1070, and TMS1100 are 28-lead packages, the TMS1200, TMS1270, and TMS1300 are 40-lead versions of the same chips (just 200 to the 28-lead chip numbers).
In the 80's TI added to the 1000 family. The 28-lead TMS1170 started with a TMS1100 base and added fluorescent display drive capability and expanded memory (2KB ROM). The TMS1370 was the same as the TMS1170 and added 27 I/O lines. An expanded memory group based on the original TMS1000 chips was also created. They were the TMS1400, TMS1470, and TMS1700 (64 Bytes RAM, 4KB ROM). There were 40-lead versions of the TMS1400 and TMS1470, which because the TMS1600 and TMS1670. CMOS versions were also added, denoted with a "C" suffix, such as TMS1200C.
The TMS1000 also had system evaluator chips. The original evaluator chips were the TMS1098 and TMS1099. These 64-lead evaluator chips were ROM-less versions of their corresponding standard chips. The TMS1099 supported the TMS1000/TMS1200 and the TMS1070/1270. The TMS1098 supported the TMS1100/1300. Later evaluators were introduced to support the entire TMS1000 family, they were the SE1000P (supports TMS1000,1070,1200,1700), SE2200P (supports TMS1100,1170,1300,1370), and the SE1400P (supports 1400, 1470, 1600, 1670).
The success of the the TMS1000 is demonstrated by its long lifecycle (over 20 years) and its expanded product line. The TMS1000 is found in many appliances, control systems, and games. Most of these chips were sourced by companies for direct use in their products and will have custom or house numbers on the chips (not the standard numbers listed above). Even TI used custom numbers in its products.
The PHILIPS CHASSIS K12 WAS the first PHILIPS monocarrier type. Previous K11 was a dual panel development type.
The PHILIPS chassis K12 doesn't share technology from previous CHASSIS K11 except for the 20AX SYSTEM CRT TUBE.
The chassis is a pretty unique type because it was introducing improvements and technology philosophy kindly singular and unique in it's fashion.
From signal processing to Video Matrixing to power supply technology and many further aspects this chassis was a reference to understand PHILIPS development flexibility.
This chassis has known many further versioning and enhancements even in more sophisticated and complex types with different CRT TUBE like the PHILIPS 30AX FAMILY.
Modularity is the main concept of construction but some Units like the E/W and FRAME UNIT gave problems in the insertion slot which often was burning the contacts producing several faults.
The solution was simple: A complete hardening with soldering and reworking of the enpoints of the Units contacts was a definitive solution for long time. But when the damage was more extended the only solution was to direct wire all contacts from Unit to chassis !
Line Deflection + EHT, Line synchronized Supply, EW Correction + Supply, Frame Deflection, Signal Section Parts.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Channel selector having a plurality of tuning systems:A channel selector characterized in that a plurality of receivers capable of simultaneously performing a receiving operation have a main part of a phase-locked loop frequency synthesizer connected in common thereto, the frequency synthesizer having a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. The frequency synthesizer is controlled so that a local oscillation frequency corresponding to a determined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes the broadcast signal from the local oscillation frequency.
and wherein each of said plurality of receivers has its own low pass filter included in its equivalent phase-locked loop frequency synthesizer, and an output of a phase comparator is switched to an input terminal of one low pass filter from among said plurality of low pass filters by a 3-state switching circuit.
2. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
3. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
5. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said equivalent phase-locked loop frequency synthesizers is controlled so that a local oscillation frequency corresponding to a predetermined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes said broadcast signal from said local oscillation frequency whereby said broadcast signal of said desired receiving channel is tuned.
6. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said phase-locked loop frequency synthesizers selects a desired receiving channel, and wherein a tuning voltage of said desired receiving channel is stored in a voltage memory means, and wherein said channel selector further comprises a tuning means provided for each of said plurality of receivers so that while receiving, said tuning means tunes in accordance with the output of said voltage memory means.
7. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. 8. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
9. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
Description:
BACKGROUND OF THE INVENTIONThis invention relates to a channel selector for use in television receivers, FM (frequency modulation) radio receivers, AM (amplitude modulation) radio receivers and so on.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:
Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
Description:
The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.
Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in theliterature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply
In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.
In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.
This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V i - V o = 0.5 V i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.
The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.
Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.
As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
PHILIPS CHASSIS K12 HIGH-VOLTAGE GENERATING DEVICE / TRANSFORMER:
A high-voltage generating device which comprises a transformer having a secondary coil subdivided into sections which are series-connected via diodes. The beginning of the first section is connected to a point of fixed potential via a further diode. The beginning and the end of the first section are also connected to this fixed potential point via first and second capacitors, respectively. As a result, a tapping lead connected, for example, to the beginning of the second section provides a voltage of from one to two times the voltage difference across a section, as desired.
Inventors: Tol, Franciscus (Eindhoven, NL) Baggermans, Albertus B. A. (Eindhoven, NL) U.S. Philips Corporation (New York, NY)
1. A high-voltage generating device comprising, a transformer having a primary coil and a secondary coil which is divided into a plurality of sections, a plurality of diodes, means connecting the end of each section, except for the end of the last section, to the anode of a diode, the cathode of which is connected to the beginning of the next section, means connecting the end of the last section to the anode of a diode whose cathode is connected to a high-voltage lead, means connecting the cathode of at least one of the other diodes to a tapping lead, means connecting the beginning of the first section to the cathode of a diode whose anode is connected to a point of fixed potential, and means connecting the beginning and the end of the first section to the point of fixed potential via first and second capacitors, respectively.
2. A high-voltage generating device comprising, a transformer having a primary winding and a secondary winding with the secondary winding divided into a plurality of winding sections, a plurality of diodes, a high-voltage output terminal, means connecting said plurality of sections in series with said plurality of diodes between said output terminal and a point of fixed potential with each section coupled to the next section by a diode and with a first diode connecting the beginning of the first section to said point of fixed potential and a second diode connecting the end of the last section to said output terminal, first and second capacitors, means coupling the beginning and end of the first section to said point of fixed potential via said first and second capacitors respectively, and means for coupling the beginning of at least one other section to a further output terminal to supply a voltage of an amplitude determined in part by said capacitors.
3. A device as claimed in claim 2 wherein said first and second capacitors have equal capacitance values.
4. A device as claimed in claim 2 wherein said first and second capacitors have unequal capacitance values.
5. A device as claimed in claim 2 wherein said further output terminal is coupled to the beginning of the second section and wherein the voltage supplied by said further output terminal can be adjusted to a value between one and two times the voltage across a section by the choice of the relative capacitance values of said first and second capacitors.
6. A device as claimed in claims 2, 3 or 4 wherein the end of at least one winding section is directly connected to the beginning of the next winding section via said diode.
7. A device as claimed in claims 2 or 5 wherein said transformer comprises the horizontal deflection transformer of a television receiver, said output terminal supplying the high-voltage for the television receiver cathode ray tube and said further output terminal supplying the focus voltage for the cathode ray tube.
Description:
The invention relates to a high-voltage generating device, notably for a television picture tube, comprising a transformer with a secondary coil which is divided into a number of sections. The end of each section, except for the end of the last section, is connected to the anode of a diode, the cathode of each diode is connected to the beginning of the next section, but the end of the last section is connected to the anode of a diode whose cathode is connected to a high-voltage lead, the cathode of at least one of the other diodes also is connected to a tapping lead.
A device of this kind is known from the magazine "Funkschau" 1976, Heft 24, pages 1051-105
4.
For example, the focus voltage for a picture tube is derived from the
tapping lead. The voltage at the area of this tapping depends on the
number of sections and on the value of the high voltage. When a higher
voltage is required, the tapping lead must be connected behind the next
section on the secondary winding. In many cases, however, the voltage
which is tapped off behind, for example, the first section is just too
low, whereas that tapped off behind the second section is much too high.An object of the invention is to enable a direct voltage to be tapped off behind the first section which amounts to from one to two times the voltage difference between the beginning and the end of this section.
To this end, the device in accordance with the invention is characterized in that the beginning of the first section is connected to the cathode of a diode whose anode is connected to a point carrying a fixed potential, the beginning and the end of the first section also being connected, via capacitors, to the point carrying the fixed potential.
By a suitable choice of the capacitance of the two capacitors, any voltage between one and two times the voltage across a section can be tapped off at the beginning of the second section.
It is to be noted that a transformer whose secondary winding is formed by a number of sections which are connected in series via diodes, the beginning of the first section also being connected to the cathode of a diode, is known per se from U.S. Pat. No. 4,091,349. However, in this transformer none of the intermediate diodes is connected to a tapping lead and the ends of the first section are not connected to capacitors either.
The invention will be described in detail hereinafter with reference to the accompanying diagrammatic drawing in which:
FIG. 1 shows a diagram of a known high-voltage generating device,
FIG. 2 is a diagram of the voltage present at a number of locations in the device shown in FIG. 1 at a given instant,
FIG. 3 shows a diagram of an embodiment of the device in accordance with the invention,
FIG. 4 is a diagram of the voltage present at a number of locations in the device shown in FIG. 3 at a given instant,
FIG. 5 is a diagram which represents the variation with time of the voltage in a number of locations in the device shown in FIG. 3, and
FIG. 6 shows a diagram to illustrate the voltage variation wih time at a location in various versions of the device shown in FIG. 3.
FIG.1 shows a known high-voltage generating device, comprising a transformer 1 with a primary coil 3 to which a pulse-shaped voltage is applied, for example, a line output transformer in a colour television receiver. The secondary coil is subdivided into four sections 5, 7, 9 and 11, the end of each of the first three sections 5, 7, 9 being connected to the anode of a diode 13,15, 17, respectively, the cathode thereof being connected to the beginning of the next section. The end of the last section 11 is connected to the anode of a diode 19, the cathode of which is connected to a high voltage lead 21 which is connected, for example, to the high voltage connection of a picture tube (not shown). The cathode of the first diode 13 is also connected to a tapping lead 23 wherefrom, for example, the focus voltage for said picture tube can be derived. The beginning of the first section 5 is connected, via a connection lead 25, to a point which carries a fixed potential.
FIG. 2 illustrates the voltage variation in each section, the number of turns n being plotted horizontally and the voltage V being plotted vertically. Each section consists of N turns in which voltage pulses 27 are induced. At the beginning of the first section 5, which is connected to a point carrying a fixed potential, the magnitude of the voltage pulses is zero and at the end of the turn N it is maximum and equal to U volts. The envelope 29 of the voltage pulses 27 is a straight line. Due to the strong capacitive coupling between the sections, no alternating voltages occur between corresponding turns of successive sections, so that the voltage pulses in the second section 7 vary across the section in the same manner as the pulses in the first section 5. The beginning of this second section thus carries a direct voltage U (due to the rectification of the voltage across the first section) and a pulse voltage zero, while the end of this section carries a pulse voltage of the magnitude U which is superposed on the direct voltage U. The same is applicable to the subsequent sections so that the voltage at the end of the fourth section 11 amounts to 4 U. It will be clear that the tapping lead 23 carries a voltage U.
FIG. 3 diagrammatically shows an embodiment of a device of the described kind which has been improved in accordance with the invention. Corresponding parts of the device are denoted by the same reference numerals as in FIG. 1. The difference with respect to FIG. 1 consists in that the beginning of the first section 5 is connected, by means of the connection lead 25, to the cathode of a diode 31 whose anode is connected to a point carrying a fixed potential, and in that at the beginning of the first section there is connected a first capacitor 43, a second capacitor 45 being connected to the end thereof, said capacitors also being connected to the point carrying a fixed potential.
If the capacitances of these capacitors are equal, their combined effect corresponds to that of a capacitor 33 which connects the centre of the section to a point carrying a fixed potential (denoted by a broken line).
The result of these steps is shown in FIG. 4 which shows, like FIG. 2, the voltage variation in the various sections. Thanks to the diode 31 and the effective capacitance 33, no longer the beginning but the centre of the first section 5 is maintained at a fixed potential for alternating voltages. As a result, the voltage pulses 35 induced in this section equal zero at the area of the central turn N/2 and are oppositely directed at the two ends of the section: thus
-U/2 at the beginning and +U/2 at the end. The capacitance 33 is charged so far that the diode 31 just becomes a conductive for each pulse, that is to say to a voltage +U/2 with respect to the point of fixed potential to which the anode of this diode is connected. The first section thus carries a mean voltage +U/2 on which there are superposed voltage pulses of the magnitude -U/2 at the beginning and +U/2 at the end of the section. This is shown in FIG. 5 in which the curve 37 represents the voltage variation as a function of the time at the beginning of the section. The curve 39 represents the voltage variation at the end of the section.
Due to the capacitive coupling between the first section 5 and the second section 7, corresponding turns of these two sections do not carry an alternating voltage with respect to each other, so that the voltage variation at the beginning of the second section corresponds to that of the first section, the mean voltage level, of course, being higher by the amount of te rectified voltage across the first section, so U volts. This is represented by the curve 41 in FIG. 5. It follows that the mean voltage on the tapping lead 23 equals 3 U/2 volts. This voltage is a direct voltage on which voltage pulses of -U/2 volts are superposed. If desired, these superposed voltage pulses can be eliminated by an RC network (not shown) connected to the tapping lead. Thus, a voltage is obtained on the tapping lead which is one and a half times that of the device shown in FIG. 1.
As has already been stated, it has been assumed that the capacitances of the capacitors 43, 45 are equal, so that the overall effect thereof can be represented by a capacitor 33 connected to the central turn. However, the voltage carried by the tapping lead 23 can be influenced by choosing these capacitances to be different.
When the values of the capacitors 43 and 45 are not the same, their combined effect corresponds to that of a capacitor 33 which is connected to a turn other than the central turn. The point in the section where the induced voltage pulses have the value zero is shifted accordingly across the section. When the capacitance of the first capacitor 43 is larger than that of the second capacitor 45, this point is situated nearer to the beginning of the section and vice versa. In extreme cases, this point may be situated at the beginning or at the end of the section. This means that the mean voltage level of the first section can vary from 0 to U volts. The direct voltage level of the curve 41 in FIG. 5 can vary accordingly from U to 2 U volts, the peaks of the negative pulses, of course, always reaching the level of the rectified voltage across the first section (U volts).
This is shown in FIG. 6 for a number of cases. The curve 41 in this Figure is identical to the curve 41 in FIG. 5
and relates to the symmetrical condition in which the capacitances of the capacitors 43 and 45 are equal. The curve 47 is obtained when the capacitance of the capacitor 43 (referred to hereinafter as C43) exceeds that of the capacitor 45 (referred to hereinafter as C45), so C43>C45. Curve 49 is obtained when C43<C45. Curve 51 represents an extreme situation where C43 is so large that the diode 31 is actually short-circuited for alternating voltages. This corresponds to the situation shown in FIG. 1. Finally, curve 53 represents the other extreme situation where C45 is so large that C43 can be neglected.
The foregoing demonstrates that the voltage at the tapping lead 23 can be adjusted between U and 2 U Volts by the choice of C43 and C45. The capacitors 43, 45 may consist of discrete components, but they may alternatively be formed during the winding of the section by using an adapted winding technique.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I
PHILIPS TRD (Tuning Remote Digital) Search type tuning system Chassis K12i:Dics-Digital Tuning System For TV Receivers" by N.V. Philips' Gloeilampenfabrieken, Netherlands, 2/1977
Other References:
Olson et al., "The Practical Application of On-Screen Display to a Television Receiver", IEEE Transactions on Broadcast and TV Receivers, _Aug. 1973, pp. 169-175.
Walker, "For TV Tuners a Digital Look", Electronics, Jun. 26, 1975, pp. 65-66.
Evans et al., "Direct Address Television Tuning and Display System Using Digital MOS Large Scale Integration", IEEE Transactions on Consumer Electronics, vol. CE-22, No. 4, pp. 267-288, Nov. 1976.
Electronics, vol. 48, No. 24, Nov. 27, 1975, "Philips TV Set Indicates Station Tuning and Color Settings on Screen", pp. 6E and 8E.
Werner, "Linear Color Bar Display for CTV Sets", Radio Mentor Electronic, vol. 41, No. 9, pp. 350-351, Sep. 1975.
A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past thosechannels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning systemfor a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control)detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.
Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuningsystems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptablereception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.
The present invention relates to a television set which includes a picture display device, an alpha numerical character generating circuit connected to the said device, a control device and means for checking analogue data relating to the operation of the set, such as volume, brightness and color. The system commonly used on television receivers for tuning into the required channels is the so-called FREQUENCY SYNTHESIZER system. This system, made possible by the advent of integrated circuits, offers a number of advantages over other known systems, such as the conventional potentiometer type MECHANICAL MEMORY systems and the more recent so-called VOLTAGE SYNTHESIZER systems. The frequency synthesizer system is fully electronic enabling any channel to be called up directly by the user who formulates the channel number on a keyboard or other control device. The system usually consists of a quartz-controlled reference oscillator, a phase lock loop, a programmable divider and a computer which supplies the number to be sent to the programmable divider in response to the number of the channel set by the user. Thanks to the phase lock loop, for each channel number set by the user, the frequency of the local oscillator on the set is kept so stable and accurate that the set is tuned with great precision to the corresponding channel signal. For further details concerning frequency synthesizer tuning systems, refer to the article entitled "A Frequency Synthesizer for Television Receivers" by E. G. Breeze, published in the November, 1974 issue of the "Transactions BTR" Magazine, or "Digital Television Tuner Uses MOS LSI and Non Volatile Memory" by L. Penner, published in the April 1, 1976 issue of "Electronics".
Channel selection is controlled by a frequency synthesizer a sweep of available channels is made by a channel selecting arrangement and this sweep is arranged to be stopped when a signal is received. When the sweeping is stopped a fine tuning arrangement takes control to respond to the frequency of the received signal and to compensate for any drift of that signal.
According to this invention there is provided a receiver comprising frequency synthesizer controlled channel selection means which includes a fine tuning arrangement; means for initiating a sweep of available channels by the channel selection means; means for stopping the sweep on reception of a signal and means, operable on cessation of sweeping and responsive to the frequency of the signal, and arranged to control the fine tuning arrangement to compensate for frequency drift of the signal.
The receiver may be in the form of a television receiver.
The means operable a cessation of sweeping may comprise level detector means arranged to receive a signal whose level is representative of the frequency of the received signal and to provide an output signal when a predetermined frequency drift is detected.
In a preferred form two level comparators are provided each arranged to receive the frequency representative signal and a respective reference level and to provide an output respectively representative of an upward and downward frequency drift exceeding predetermined limits.
The signal whose level is representative of the frequency of the received signal may be provided by automatic frequency control (A.F.C.) means conveniently in the form of an A.F.C. discriminator.
The means operable or cessation of sweeping may be arranged to control the fine tuning arrangement via a signal path which includes means for blocking said signal path until the said signal is received.
The means for blocking may be in the form of gate means connected to the said signal path and arranged to receive a second input a signal indicative of the receipt of the said signal.
The means for initiating a sweep may comprise an operator control coupled to control input means of the channel selection means, and the means for stopping sweeping is operative to isolate the operator control from the said control input means.
The operator may be coupled to the channel selection means via gating means operative to open an operation of the operator control and the means for stopping sweeping may provide a signal operative to block the gating means or receipt of the said signal.
The means for stopping sweeping may include means for detecting the reception of the said signal which in a preferred form of television receiver comprises a sync comparator operative to compare video signals with line flyback signals and to provide an output signal whose level is indicitive of the reception of the said signal.
The frequency synthesizer system lends itself well to a number of different modes of television channel tuning;
direct selection by formulating the required channel number as described above television channels are numbered: for example, in the European C.C.I.R. standard, V.H.F. band channels are numbered from 2 to 12 and U.H.F. band channels from 21 to 69; in the American Standard, VHF channels are numbered from 2 to 13 and UHF from 14 to 83).
memory selection: each of a certain set of keys corresponds to a preselected and memorised channel;
automatic scanning of all the channels of a given standard, or of all the channels contained in the memory or continuous scanning of all the frequency bands involved.
The first application enables immediate, direct selection of any one of the channels in the relative standard (60 in Europe, 82 in America).
the second enables faster detection of one of a limited number of preferred channels.
The third is a fast, simple way of finding out which standard channels can be received, which channels have been memorised and whether other broadcasting stations exist on non-standard frequencies such as the private broadcasting stations in Italy (there are currently over a hundred operating).
A)- A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A first programmable frequency divider controlled by a reversible counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator, after passing through another programmable frequency divider, also is applied. The phase comparator output is a tuning voltage used to control the tuning of the local oscillator. A logic circuit is coupled to sense predetermined relationships of signals from a picture carrier detector, a sound carrier detector, an AFT discriminator circuit, and the presence of vertical synchronization signal components for changing the count in the reversible binary counter to adjust the first programmable frequency divider to compensate for channel frequency offsets which may occur in excess of the pull-in range of the AFT discriminator circuit. To permit operation of the
1. A frequency synthesizer signal seek tuning system for a tuner of a television receiver capable of receiving a composite television signal, said system including in combination:
reference oscillator means providing a reference signal at a predetermined frequency;
local oscillator means in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider having an input coupled to said reference oscillator means for producing an output signal having a frequency which is a programmable fraction of the frequency of the signal applied to the input thereto from saidreference oscillator means;
means coupled to the output of said programmable frequency divider and the output of said local oscillator means for developing a control signal and applying such control signal to said local oscillator means for controlling the frequency ofoperation thereof;
channel selection means coupled to said programmable frequency divider for establishing a predetermined initial programmable fraction therein each time a new channel is selected by said channel selection means;
control means coupled to the output of the tuner of the television receiver and further coupled to said programmable frequency divider for controlling said frequency divider to change the programmable fraction thereof in response to predeterminedconditions of the signals from the tuner; and
signal seek tuning means coupled to said channel selection means and said control means for causing said channel selection means to select a new channel in response to said predetermined conditions of the tuner signals persisting for a predetermined time period.
2. The combination according to claim 1, wherein the composite television signal has at least carrier signal components and synchronizing signal components and further including carrier sensing means coupled to receive at least the carriersignal components of the composite signal from the tuner and providing an output voltage indicative of the tuning of said receiver to a carrier component of said composite signal; and synchronizing signal component sensing means coupled to receive atleast said synchronizing signal components of the composite signal for providing a first predetermined output with synchronizing signal components sensed thereby; wherein said control means is coupled to the outputs of said carrier sensing means andsaid synchronizing signal components sensing means and further coupled to said programmable frequency divider means for changing the programmable fraction thereof in response to first predetermined conditions of signals at the outputs of said carriersensing means and said synchronizing signal components sensing means and the operation of said signal seek tuning means being terminated in response to second predetermined conditions of signals at the outputs of said carrier sensing means and saidsynchronizing signal components sensing means.
3. The combination according to claim 1, further including first and second switches in said signal seek tuning means for initiating a signal seek operation in the "up" and "down" directions, respectively, operation of one of said first andsecond switches causing said channel selection means to select the next channel in the selected direction and establishing said predetermined initial programmable fraction in said programmable frequency divider in response thereto.
4. The combination according to claim 3, wherein said control means terminates operation of said signal seek means in response to detection of second predetermined conditions of the signals from the tuner.
5. The combination according to claim 1, wherein said predetermined conditions of the tuner signals comprise first and second predetermined conditions, respectively; said programmable frequency divider has its input coupled to the output ofsaid reference oscillator means; and wherein said control means includes reversible digital counter means coupled to said programmable frequency divider, and logic circuit means coupled to the output of the tuner for causing said counter means to countin one direction when said first predetermined conditions exist and to count in the opposite direction when said second predetermined conditions exist.
6. The combination according to claim 5, further including additional means coupled to said counter means and coupled to said logic circuit means for inhibiting operation of said signal seek tuning means and for preventing a change in the countof said counter means when third predetermined signal conditions exist in the tuner output.
7. The combination according to claim 6, further including a second programmable frequency divider coupled to the output of said local oscillator means and producing an output signal having a frequency which is a programmable fraction of thefrequency of the signal applied to the input thereto from said local oscillator means; and wherein said channel selection means is further coupled to said second programmable frequency divider for controlling said second programmable frequency dividerto establish the programmable fraction thereof each time a new channel is selected by said channel selection means.
B)- A tuning system for a television receiver includes a local oscillator which is controlled first by a phase lock loop arrangement and then by an AFT discriminator arrangement for tuning the receiver to non-standard as well as standard frequency carriers. The phase lock loop arrangement includes a programmable divider for dividing the local oscillator frequency by a programmable factor corresponding to the presently selected channel. When the local oscillator is being controlled by the AFT discriminator arrangement, the count accumulated by the programmable divider during a reference interval determines how far the local oscillator frequency has drifted from its nominal value. If a predetermined frequency offset has been exceeded, control is returned to phase lock loop control and the programmable factor is incrementally changed.
1. In a system for tuning a television receiver to the various channels a viewer may select, apparatus comprising:
local oscillator means for generating a local oscillator signal;counter means for generating a frequency divided signal by counting a predetermined number of periods of said local oscillator signal, said predetermined number being proportional to the frequency of said local oscillator signal;
means for generating a reference frequency signal;
phase control means for generating a control signal representing the phase and frequency deviation between said frequency divided signal and said reference frequency signal;
mode switching means for selectively coupling said control signal to said local oscillator means; said mode switching means initially coupling said control signal to said local oscillator means;
said local oscillator means changing the frequency of said local oscillator signal in response to said control signal until said frequency divided signal and said reference frequency signal to be in a predetermined phase and frequency relation;
said counter means accumulating a nominal number of counts during a predetermined portion of said frequency divided signal when said frequency divided signal and said reference signal are in said predetermined phase and frequency relationship;
means for generating a lock signal when said frequency divided signal and said reference frequency signal are in said predetermined phase and frequency relationship;
said mode switching means decoupling said control signal from said local oscillator means in response to said lock signal;
means for generating a count signal when said control signal is decoupled from said local oscillator means, said count signal having a duration with a predetermined time relationship to said reference frequency signal;
means responsive to said count signal for disabling said counter means from counting when said control signal is decoupled from said local oscillator means except during the duration of said count signal; and
means for generating an offset signal representing the deviation between the count accumulated by said counter means during a time interval corresponding to said predetermined portion of said frequency divided signal when said control signal isdecoupled from said local oscillator means and said nominal number of counts, said offset signal being coupled to said mode switching means to control the coupling of said control signal to said local oscillator means.
2. The apparatus recited in claim 1 wherein said means for generating said offset signal includes:
memory means for generating an output signal having a first amplitude when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;
means for resetting said memory means prior to the occurrence of said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillator means;
means for setting said memory means if the count accumulated by said counter during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said local oscillatormeans is less than said nominal number of counts by a first predetermined deviation; and
means for resetting said memory means if the count accumulated by said counter means during said time interval corresponding to said predetermined portion of said frequency divided signal when said control signal is decoupled from said localoscillator means is greater than said nominal number of counts by a second predetermined deviation.
3. The apparatus recited in claim 1 wherein said counter means derives said frequency divided signal by counting a first number of periods during a first portion of said frequency divided signal and by counting a second number of periods duringa second portion of said frequency divided signal.
4. The apparatus recited in claim 3 wherein the various channels a viewer may select are partitioned into frequency bands, said first number is related to the channel selected by a viewer and said second number is related to the frequency bandin which the selected channel resides.
5. The apparatus recited in claim 4 wherein said predetermined portion is at least a part of said second portion.
6. The apparatus recited in claim 5 wherein said counter includes:
variable modulus frequency divider means for selectively dividing the frequency of said local oscillator signal by a first factor or a second factor, said first factor being related to the frequency spacing between channels in at least one ofsaid bands;
decade counter means for counting periods of the output signal of said variable modulus frequency divider;
channel number comparator means for generating a channel match signal when the number of periods counted by said decade counter means equals said first number, said decade counter means being reset in response to said channel match signal;
first factor stop comparator means for generating a first factor stop signal when the number of periods counted by said decade counter means equals a third number, said third number being also related to the band in which the selected channelresides but less than said second number, said variable modulus divider means being caused to divide by said second factor in response to said first factor stop signal; and
added count comparator means for generating an added count match signal when the number of periods counted by said decade counter means equals said second number, said decade counter means being reset in response to said added count match signal,said variable modulus divider means being caused to divide by said first factor in response to said added count match signal.
7. The apparatus recited in claim 6 wherein said nominal number of counts equals said second number.
8. The apparatus recited in claim 7 wherein said means for generating said offset signal includes means for resetting at least said decade counter means and for causing said variable modulus divider to divide by said first factor in response tothe initiation of said count signal.
9. The apparatus recited in claim 7 wherein said means for generating said offset signal includes:
memory means for generating an output signal when said memory means is set and a second amplitude when said memory means is reset, said output signal being coupled to said mode switching means as said offset signal;
means for resetting said memory means prior to the occurrence of said first factor stop signal during the duration of said count signal when said control signal is decoupled from said local oscillator;
means for inhibiting the generation of said added count signal when said control signal is decoupled from said local oscillator;
means for setting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is less than said second number by a first predetermineddeviation; and
means for resetting said memory means if the count accumulated by said counter means after said first factor stop signal when said control signal is decoupled from said local oscillator means is greater than said second number by a secondpredetermined deviation.
10. The apparatus recited in claim 9 wherein said means for generating said offset signal includes means for repetitively generating said offset signal.
11. The apparatus recited in claim 1 wherein said means for disabling said counter means includes input switching means for selectively decoupling said local oscillator signal from said counter means when said control signal is decoupled fromsaid local oscillator means except in response to said count signal; and
said counter means includes means for generating an illegal signal when an illegal channel has been selected;
said input switching means also decoupling said local oscillator signal from said counter means in response to said illegal signal.
12. The apparatus recited in claim 11 wherein:
said means for generating said illegal signal includes band selection means for generating a band traversed signal whenever the count accumulated by said counter corresponds to the boundary of a band and means for generating a band signalrepresenting the band in which the selected channel resides in accordance with which of said band traversed signals have been generated during said first portion of said frequency divided signal, said means for generating a band signal generating saidillegal signal when a band signal is not generated.
13. The apparatus recited in claim 11 wherein said means for generating said reference frequency also includes means for deriving a signal having a predetermined frequency; and said input means includes means for coupling said signal having apredetermined frequency to said counter means in response to said illegal signal.
Description: The present invention pertains to television tuning systems including a phase locked loop frequency synthesizerand particularly pertains to frequency counters which may be utilized in such systems.
In order to reduce the complexity, and therefore the cost, of an implementation of such a tuning system, it is desirable that individual potions of the system be capable of performing more than one function. For example, in copending UnitedStates Patent Application Ser. No. 663,097 filed for R. M. Rast on Feb. 27, 1976, and now U.S. Pat. No. 4,009,439 and assigned to the same assignee as the present invention, which is hereby incorporated by reference, there is described a frequencydivider for a television tuning phase locked loop tuning system. For each channel a viewer selects, the divider divides the frequency of the local oscillator signal by a number proportional to the nominal local oscillator frequency by forming a signalincluding first and second portions having durations respectively equal to first and second numbers of periods of the local oscillator signal. The first number is related to the selected channel number. The second number is related to the frequencyband in which the selected channel resides. To generate signals including in which band the selected channel resides for use in the phase locked loop itself and in the local oscillator to control its frequency range, a band selection unit is included asan integral part of the divider.
In accordance with the present invention, a programmable counter which may be used, for example, in a phase locked loop portion of a tuning system of the type decribed in the concurrently filed Henderson et al. application referenced above todivide the frequency of the local oscillator by a number proportional to the nominal local oscillator frequency for a selected channel is arranged so that it may also serve to generate a signal indicating whether or not the frequency of the localoscillator has drifted beyond a predetermined frequency offset after phase locked loop control of the local oscillator has been terminated. When the local oscillator is under phase locked loop control, the programmable counter accumulates a nominalnumber of counts during a predetermined portion of its output signal. Means are provided for generating a count signal after phase locked loop control of the local oscillator has been terminated. The count signal has a duration with a predeterminedtime relationship to a reference signal to which the local oscillator signal is locked when the local oscillator is under phase locked loop control. The counter is disabled from counting when the local oscillator is not under phase locked loop controlexcept during the duration of the count signal. Offset detection means, in response to the count signal, generates an offset signal representing the deviation between the count accumulated during a time interval corresponding to the predeterminedportion after phase locked loop control of the local oscillator has been terminated to determine how far the frequency of the local oscillator has drifted from the frequency synthesized under phase locked loop control.
C)- A tuning system for a television receiver includes a phase locked loop (PLL) configuration and an automatic fine tuning (AFT) configuration which are selectively enabled to operate to tune the receiver to nonstandard as well as standard frequency RF carriers which may be provided by cable and master antenna systems. After the selection of a new channel, the operations of the PLL and AFT configurations are sequentially enabled by a mode control apparatus. During the operation of the AFT configuration, an offset detector determines when the frequency of the local oscillator signal is caused to be more than a predetermined offset from its value established during the previous operation of the PLL configuration. In response, the mode control unit reestablishes the operation of the PLL configuration. Channel selection apparatus causes a new channel to be selected after a predetermined number of alternate operating cycles of the two configurations.
1. Apparatus for selectively tuning a receiver to any one of a plurality of RF carriers associated with respective channels, comprising:
local oscillator means for generating a local oscillator signal;
mixer means for combining a selected one of said RF carriers with said local oscillator signal to derive an IF signal having at least one carrier with a nominal frequency value;
phase locked loop (PLL) means for selectively controlling said local oscillator means when enabled to operate to cause said local oscillator signal to have a programmed frequency substantially equal to the product of a programmable factor and the frequency of a frequency reference signal;
programmable fac
tor control means for determining programmable factor in accordance with the channel selected and for generating a CHANGE signal when a new channel is selected; lock means for generating a LOCK signal when said local oscillator signal has a frequency substantially equal to said programmed frequency;
automatic fine tuning (AFT) means for selectively controlling said local oscillator means when enabled to operate to reduce a deviation between the actual frequency of said IF carrier and said nominal frequency value;
offset detector means for generating an OFFSET signal when the frequency of said local oscillator signal is caused to be offset from said programmed frequency by a predetermined amount during the operation of said AFT means;
mode control means for enabling the operation of said PLL means in response to said CHANGE signal, for enabling the operation of said AFT means in response to said LOCK signal and for again enabling the operation of said PLL means in response to said OFFSET signal; and
channel selection means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated a predetermined number of times.
2. The appara
tus recited in claim 1 wherein: said predetermined number of times is equal to one.
3. The apparatus recited in claim 1 wherein:
said programmable factor control means is coupled to counter means for counting the number of times said OFFSET signal is generated to change said programmable factor by an increment less than the difference between programmable factors associated with respective adjacent channels when said OFFSET signal is generated a second predetermined number of times less than said first mentioned predetermined number of times; and
said channel selection means is also coupled to said counter means for causing said programmable factor control means to select the programmable factor associated with the next channel when said OFFSET signal is generated said first mentioned predetermined number of times.
4. The apparatus recited in claim 3 wherein:
said programmable factor control means increases said programmable factor by said increment in response to a first generation of said OFFSET signal and decreases said programmable factor by said increment in response to a second generation of said OFFSET signal and changes said programmable factor to the value associated with the next channel in response to a third generation of said OFFSET signal.
5. The apparatus recited in claim 4 wherein:
said programmable factor control means includes inhibiting means for inhibiting said programmable factor control means from changing said programmable factor to the value in response to said OFFSET signal after a predetermined time longer than the time required to tune said receiver to a selected channel.
Description:
BACKGROUND OF THE PRESENT INVENTION The present invention relates to search type tuning systems.
A wide variety of "search" or "signal seeking" tuning systems for radio and television receivers are known which provide for automatically tuning only those channels which have acceptable reception characteristics and for skipping past those channels which have unacceptable reception characteristics. Such tuning systems typically include a number of signal detectors for determining when a received RF carrier has acceptable reception characteristics. For example, a search type tuning system for a television receiver may include: an AFT (automatic fine tuning) detector for determining when an IF carrier derived from the received RF carrier has a frequency within a predetermined range of its desired value; and AGC (automatic gain control) detector for determining when the received RF carrier has an amplitude greater than a predetermined value; and a synchronization detector to determine when synchronization pulses derived from the received RF carrier have the proper frequency.
Tuning systems are also known which include a memory having memory locations associated with each channel in a tuning range for storing information as to whether the associated station or channel is preferred or not. Such "memory" type tuning systems may be utilized as an alternative to the "search" type tuning systems to select only those channels with acceptable reception characteristics in a given location.
Both "search" and "memory" type tuning systems require a considerable amount of complex and expensive circuitry, in addition to the basic tuning system for tuning each channel in a tuning range, for tuning only those channels with acceptable reception characteristics. Thus, there is a need for a tuning system which requires only a relatively small amount of circuitry in addition to the basic tuning system for tuning only channels with acceptable reception characteristics.
SUMMARY OF THE PRESENT INVENTION
The present invention is an improvement to the type of electronic tuning system which includes first tuning means for tuning a tuner to standard frequencies associated with respective channels, second tuning means for tuning the tuner to reduce deviations between the frequency of an IF carrier generated by the tuner and its desired or nominal value that may arise due to, e.g., offsets in the frequencies of received RF carriers, and mode switching means for selectively applying the first and second tuning control signals to the tuner. In this type of electronic tuning system, the operation of the first tuning means is enabled after a new channel is selected and the operation of the second tuning means is enabled after the first tuning means has completed its operation. During the operation of the second tuning means, an offset detector determines when the frequency of a local oscillator signal generated by the tuner becomes offset from value established during the operation of the first tuning means and causes the operation of the first tuning means to again be enabled.
In accordance with the present invention, search means are provided in the above described type of electronic tuning system for causing a new channel to be selected if no RF carrier is tuned by the end of a predetermined number of operating cycles of the second tuning means.
SUPPLY 4822 212 20302 (TDA2581)
MATRIX 3122 133 31460 (TDA2771)
CHROMA 4822 212 20306 (TDA2523/4) + (TDA2560/3)
SOUND 4822 212 20599 (TDA2790)
MULTISTABILIZER 4822 212 20304 (TCA750Q)
IF AMPLIFIER 4822 212 20309 (TDA2750)
3122 133 31490
E/W + 29 /32/225V SUPPLY 4822 212 20305
SYNCRONIZATION 3122 133 31470 (TDA2572A)
IF DETECTOR 3131 118 58690 4822 212 20438 (TDA2760)
FRAME DEFLECTION 20AX 4822 212 20303 (TDA2780AQ)
TRD UNIT 8212 860 06032 ( SAB2015 SAB2024 )
OSD TUNING TRD UNIT 8212 860 06083
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I TDA2581 CONTROL CIRCUIT FOR SMPS/PHILIPS POWER PACK:
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I E/W CORRECTION Circuit arrangement in an image display apparatus for (horizontal) line deflection:
Line deflection circuit in which the deflection coil is east-west modulated. In order to cancel an east-west dependent horizontal linearity defect the inductance value of the linearity correction coil is made independent of the field frequency, for example by means of a compensating current. In an embodiment this current is supplied by the shunt coil of the east-west modulator.
1. Circuit arrangeme
nt for use with a line deflection coil, said circuit comprising a generator means adapted to be coupled to said coil for producing a sawtooth line-deflection current through said line deflection coil, said deflection current having a field-frequency component current, a horizontal linearity correction coil adapted to be coupled in series with said deflection coil and including an inductor having a bias-magnetized core, and means for making the inductance value of the linearity correction coil substantially independent of the field frequency component current. 2. Circuit arrangement as claimed in claim 1, wherein said making means includes a current supply source means for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the compensating current having a field-frequency variation. 3. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is opposite to the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have the same direction. 4. Circuit arrangement as claimed in claim 2, wherein the direction of curvature of the field-frequency envelope of the compensating current is the same as the direction of curvature of the field-frequency component current of the line deflection current, whereby the magnetic fields produced in the core of the correction coil by the two currents have opposite directions. 5. Circuit arrangement as claimed in claim 2, wherein said correction coil further comprises an additional winding disposed on the core, said additional winding being coupled to said supply source means to receive the compensating current. 6. Circuit arrangement as claimed in claim 5, further comprising modulator means for modulating the line deflection current with said field frequency component, said modulator including a compensation coil coupled in series with said additional winding. 7. Horizontal linearity correction coil comprising a core made of a magnetic material and bias-magnetized by at least one permanent magnet, and an additional winding disposed on the core. 8. Image display apparatus including a circuit arrangement as claimed in claim 1.
Description:
The invention relates to a circuit arrangement in an image display apparatus for (horizontal) line deflection, which apparatus also includes a circuit arrangement for (vertical) field deflection, provided with a generator for generating a sawtooth line-frequency deflecting current through a line deflection coil and with a modulator for field-frequency modulation of this current, the deflection coil being connected in series with a linearity correction coil in the form of an inductor having a bias-magnetized core.
By means of the linearity correction coil the linearity error due to the ohmic resistance of the deflection circuit is corrected. The sign of the bias magnetisation is chosen so that it is cancelled by the deflection current at the beginning of the deflection interval, so that the inductance of the correction coil is a maximum, whereas the voltage drop across the deflection coil then is a minimum. This voltage drop is adjustable by adjustment of the starting inductance of the correction coil. During the deflection interval the core gradually becomes saturated so that the inductance of, and the voltage drop across, the correction coil decrease. Thus the linearity error can be cancelled exactly at the beginning of the interval, that is to say on the left on the screen of the image display tube, and with a certain approximation at other locations.
In image display tubes using a large deflection angle, raster distortion, which generally is pincushion-shaped, of the image displayed occurs. This distortion can be removed in the horizontal direction, the so-called east-west direction, by means of field-frequency modulation of the line deflection current, the envelope in the case of pincushion-shaped distortion being substantially parabolic so that the amplitude of the line deflection current is a maximum at the middle of the field deflection interval.
It was found in practice that the said two corrections are not independent of one another, that is to say the adjustment of the east-west modulation affects horizontal linearity. As long as the modulation depth is not excessive, a satisfactory compromise can be found. However, in display tubes having a deflection angle of 110° and particularly in colour display tubes in which the deflection coils have a converging effect also, it is difficult to find such a compromise. A tube of this type is described in "Philips Research Reports," volume Feb. 14, 1959, pages 65 to 97; the distribution of the deflection field is such that throughout the display screen the landing points of the electron beams coincide without the need for a converging device. Owing to this field distribution, however, the pin-cushion-shaped distortion in the image displayed in the east-west direction is greater than in comparable display tubes of another type. Hence there must be east-west modulation of the line deflection current to a greater depth. It is true that under these conditions horizontal linearity can correctly be adjusted over a given horizontal strip after the east-west modulation has been adjusted correctly, i.e., for a rectangular image, but it is found that in other parts of the display screen a serious linearity error remains. When vertical straight lines are displayed as straight lines in the right-hand part of the screen, they are displayed as curved lines in the left-hand part.
It is an object of the present invention to remove the said defect so that horizontal linearity can satisfactorily be adjusted throughout the screen, and for this purpose the circuit arrangement according to the invention is characterized in that it includes means by which the inductance of the linearity correction coil is made substantially independent of the field frequency.
The invention is based on the recognition that the defect to be removed is due to a field-frequency variation of the said inductance because the latter is current-dependent. According to a further recognition of the invention the circuit arrangement is characterized in that it includes a current supply source for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the current being field-frequency modulated. The circuit arrangement according to the invention may further be characterized in that an additional winding is provided on the core of the linearity correction coil and is traversed by the compensating current. A circuit arrangement in which the modulator for modulating the line deflection current includes a compensation or bridge coil may according to the invention be characterized in that the additional winding is connected in series with the said coil.
The invention also relates to a linearity correction coil for use in a line deflection circuit having a core which is made of a magnetic material and is bias magnetized by at least one permanent magnet, which coil is characterized in that an additional winding is provided on the core.
Embodiments of the invention will now be described by way of example, with reference to the accompanying diagrammatic drawings, in which
FIG. 1 is the circuit diagram of a known circuit arrangement for line deflection in which the line deflection current is east-west modulated,
FIG. 2 shows the distorted image which is displayed on the screen when the circuit arrangement of FIG. 1,
FIG. 3 is a graph explaining the observed defect, and
FIGS. 4 and 7 show embodiments of the circuit arrangement according to the invention by which this defect can be cancelled.
FIG. 1 is a greatl
simplified circuit diagram of a line deflection circuit of an image display apparatus, not shown further. The circuit includes the series combination of a line deflection coil L y , a linearity correction coil L and a trace capacitor C t , which series combination is traversed by the line deflection current i y . The collector of an npn switching transistor T r and one end of a choke coil L 1 are connected to a junction point A of a diode D, a capacitor C r and the said series combination. The other end of the choke coil is connected to the positive terminal of a supply voltage source which supplies a substantially constant direct voltage V b and to the negative terminal of which the emitter of transistor Tr is connected. This negative terminal may be connected to earth. The other junction point B of elements D and C r and of the series combination of elements C t , L y and L is connected to one terminal of a modulation source M for east-west correction which has its other terminal connected to earth. Diode D has the pass direction shown in the FIG.
To the base of transistor Tr line-frequency switching pulses are supplied. In known manner the said series combination is connected to the supply voltage source during the deflection interval (the trace time), diode D and transistor Tr conducting alternately. During the retrace time these elements are both cut off. Under these conditions the current i y is a sawtooth current. The coil L, which has a saturable ferrite core which is bias-magnetized by means of at least one permanent magnet, serves to correct the linearity of the current i y during the trace time, whilst the capacitance of the capacitor C t is chosen so that the currenct i y is subjected to what is generally referred to as S correction. During the retrace time, at point A pulses are produced the amplitude of which is much higher than that of the voltage V b and would be constant in the absence of modulation source M. Information from the field deflection circuit, not shown, of the image display apparatus and line retrace pulses, the latter for example by means of a transformer, are supplied in known manner to modulation source M. Amplitude-modulated line retrace pulses having a field-frequency parabolic envelope, as indicated in the FIG., are produced at point B. During the line trace time the voltage at point B is zero. Thus the current i y is given the desired field-frequency modulated form which is also shown in FIG. 1.
The amplitude of the envelope in point B at the beginning and at the end of the field trace time and the amplitude of this envelope at the middle of the said time can both be adjusted so that the image displayed on the display screen of the display tube (not shown) has the correct substantially rectangular form. If, however, the required modulation depth is comparatively large, a linearity error of the line deflection is produced which cannot be removed by means of the correction coil L.
FIG. 2 shows the image of a pattern of vertical straight lines as it is displayed on the screen with the correction coil L adjusted so that horizontal linearity is satisfactory along and near the central horizontal line. In FIG. 2 the defect is exaggerated. It is found that horizontal linearity is defective in other areas of the screen so that the vertical lines are displayed correctly in the right-hand half of the screen but as curves in the left-hand path, the defect increasing as the line is farther to the left.
This phenomenon can be explained with reference to FIG. 3. In this FIG. the inductance L of the linearity correction coil is plotted as a function of the magnetic field strength H. In the absence of current, H has a value H 0 owing to the bias magnetization. If an approximately linear sawtooth current i (t) as shown in the b
ottom left-hand part of FIG. 3 flows through the coil, the field strength H varies proportionally about the value H 0 , for the mean value of the current is zero. Because the curve of L is not linear, the variation L(t) of L, which is shown in the top right-hand part, is not a linear function of time. The resulting curve may be regarded as composed of a linear component and a substantially parabolic component which is to be taken into account when choosing the capacitance of capacitor C t .
Because owing to the east-west modulation the amplitude of current i(t) varies, the amplitude of L(t) also varies. This implies a field-frequency variation of L which is non-linear. This variation is undesirable. In the case of a small variation of the amplitude of current i(t) the variation of L(t) can be more or less neglected, but this is no longer possible when the amplitude of current i(t) varies greatly owing to the east-west modulation. L(t) varies according to different curves. FIG. 3 shows two of such curves and also illustrates the fact that the undesirable variation of L(t) is greatest at the beginning of the trace time and smallest at the end thereof.
FIG. 4 shows a circuit arrangement in which the defect described can be corrected. On the core of the correction coil L of the circuit of FIG. 1 an additional winding L 2 is provided. Winding L 2 is connected to a current source which produces a compensating current i 2 which has a line-frequency sawtooth variation and a field-frequency amplitude modulation. The envelope here also is parabolic, however, with a shape opposite to that of deflection current i y , that is to say having a minimum at the middle of the field trace time. The direction of current i 2 and the winding sense of winding L 2 relative to that of coil L are chosen so that the magnetic field produced in the core by winding L 2 has the same direction as the field produced by coil L. Hence the two field strengths are added. The amplitude of current i 2 and the turns number of winding L 2 can be chosen so that current i y flows through inductances the total value of which is not dependent upon the field frequency. The curve L(t) of FIG. 3 remains substantially unchanged. Consequently the undesirable field-frequency modulation is removed without variation of the bias magnetization, which would have been varied if current i 2 were a field-frequency current. Obviously the same result can be achieved by a choice such of the direction of current i 2 and of the winding sense of winding L 2 that the two field strengths are subtracted one from the other, whilst the curvature of the envelope of current i 2 has the same direction as that of the envelope of current i y .
The current source of FIG. 4 may be formed in known manner by means of a modulator in which a line-frequency sawtooth signal is field-frequency modulated, the envelope being parabolic. FIG. 5 shows a circuit arrangement in which current i 2 is produced by the modulation source which provides the east-west correction. In FIG. 5, the source M of FIG. 1 comprises a diode D', a coil L' and two capacitors C' r and C' t , which elements constitute a network of the same structure as the network formed by elements D, L y , C r and C t . The capacitor C' t is shunted by a modulation source V m which supplies a field-frequency parabolic voltage having a minimum at the middle of the field trace time.
With the exception of the linearity correction means to be described hereinafter, the circuit arrangement of FIG. 5 was described in more detail in U.S. Pat. No. 3,906,305. Hence it will be sufficient to mention that the capacitances of capacitors C r and C' r and of a capacitor C 1 connected between junction point A and earth and the inductance of coil L' are chosen so that the three sawtooth currents flowing through L y , L' and L 1 have the same retrace time. The capacitances of capacitors C t and C' t , which are large, are ignored. When voltage V b is constant, current i y is subjected to the desired east-west modulation having the form shown in FIG. 1.
Coil L y is connected in series with correction coil L, and winding L 2 is connected in series with coil L'. FIG. 5 shows that the current flowing through winding L 2 has the same waveform as the current i 2 of FIG. 4, for its envelope has the same shape as the voltage supplied by source V m . By a suitable choice of the number of turns of winding L 2 it can be ensured that the linearity correction remains the same for every line during the field trace time.
Modified embodiments of the circuit arrangement of FIG. 5 can also be used. FIG. 6 shows such a modified embodiment in which the capacitive voltage divider C r , C' r of FIG. 5 is replaced by an inductive voltage divider by means of a tapping on coil L 1 . A capacitor C 2 is included between the tapping and the junction point of diodes D and D', whilst capacitor C' t here forms part of two networks C t , L y and C' t , L' traversed by a sawtooth current. In FIG. 6 modulation source V m is connected via a choke coil L 3 to the junction point of D, D', C 2 and
C' t . One end of winding L 2 is connected to the junction point of capacitor C' t and the coil L, whilst the other end is connected to earth via coil L'. The capacitances of capacitors C 1 and C 2 and the location of the tapping on coil L 1 are chosen so that the sawtooth currents flowing through L y , and L' and L 1 have the same retrace time, whilst the field-frequency linearity defect of FIg. 2 is cancelled by correctly proportioning winding L 2 .
Other east-west modulators are known in which the step of FIGS. 5 and 6 can be used. An example is the modulator described in the publication by Philips, Electronic Components and Materials: "110° Colour television receiver with A66-140X standard-neck picture tube and DT 1062 multisection saddle yoke," May 1971, pages 19 and 20, which modulator also comprises two diodes and a compensation coil L', which are arranged in a slightly different manner. In another example the east-west modulator and the line deflection generator are included in a bridge circuit whilst they are decoupled from one another by means of a bridge coil which has the same function as coil L' in FIGS. 5 and 6. In these circuit arrangements coil L and winding L 2 may be arranged in the same manner as in FIG. 6. The same applies to an east-west modulator using a transductor the operating winding of which is in series with the deflection coil.
In the abovedescribed embodiments of the circuit arrangement according to the invention the compensating current i 1 is provided by transformer action. In the embodiment of FIG. 7 the current source which supplies the current i 2 is connected in parallel with correction coil L, i.e., without an auxiliary winding. In this embodiment the east-west modulation is achieved not by means of a modulator, but by means of the fact that the supply voltage V b is the super-position of a field-frequency parabolic voltage on the direct voltage. In this known manner the supply source also is the modulator.
It will be seen that in the embodiments of FIGS. 4, 5 and 6 current i 2 counteracts the east-west modulation of deflection current i y . It was found in practice, however, that this counteraction is slight.
By means of the linearity correction coil the linearity error due to the ohmic resistance of the deflection circuit is corrected. The sign of the bias magnetisation is chosen so that it is cancelled by the deflection current at the beginning of the deflection interval, so that the inductance of the correction coil is a maximum, whereas the voltage drop across the deflection coil then is a minimum. This voltage drop is adjustable by adjustment of the starting inductance of the correction coil. During the deflection interval the core gradually becomes saturated so that the inductance of, and the voltage drop across, the correction coil decrease. Thus the linearity error can be cancelled exactly at the beginning of the interval, that is to say on the left on the screen of the image display tube, and with a certain approximation at other locations.
In image display tubes using a large deflection angle, raster distortion, which generally is pincushion-shaped, of the image displayed occurs. This distortion can be removed in the horizontal direction, the so-called east-west direction, by means of field-frequency modulation of the line deflection current, the envelope in the case of pincushion-shaped distortion being substantially parabolic so that the amplitude of the line deflection current is a maximum at the middle of the field deflection interval.
It was found in practice that the said two corrections are not independent of one another, that is to say the adjustment of the east-west modulation affects horizontal linearity. As long as the modulation depth is not excessive, a satisfactory compromise can be found. However, in display tubes having a deflection angle of 110° and particularly in colour display tubes in which the deflection coils have a converging effect also, it is difficult to find such a compromise. A tube of this type is described in "Philips Research Reports," volume Feb. 14, 1959, pages 65 to 97; the distribution of the deflection field is such that throughout the display screen the landing points of the electron beams coincide without the need for a converging device. Owing to this field distribution, however, the pin-cushion-shaped distortion in the image displayed in the east-west direction is greater than in comparable display tubes of another type. Hence there must be east-west modulation of the line deflection current to a greater depth. It is true that under these conditions horizontal linearity can correctly be adjusted over a given horizontal strip after the east-west modulation has been adjusted correctly, i.e., for a rectangular image, but it is found that in other parts of the display screen a serious linearity error remains. When vertical straight lines are displayed as straight lines in the right-hand part of the screen, they are displayed as curved lines in the left-hand part.
It is an object of the present invention to remove the said defect so that horizontal linearity can satisfactorily be adjusted throughout the screen, and for this purpose the circuit arrangement according to the invention is characterized in that it includes means by which the inductance of the linearity correction coil is made substantially independent of the field frequency.
The invention is based on the recognition that the defect to be removed is due to a field-frequency variation of the said inductance because the latter is current-dependent. According to a further recognition of the invention the circuit arrangement is characterized in that it includes a current supply source for producing a compensating line-frequency sawtooth current through a winding of the linearity correction coil, the amplitude of the current being field-frequency modulated. The circuit arrangement according to the invention may further be characterized in that an additional winding is provided on the core of the linearity correction coil and is traversed by the compensating current. A circuit arrangement in which the modulator for modulating the line deflection current includes a compensation or bridge coil may according to the invention be characterized in that the additional winding is connected in series with the said coil.
The invention also relates to a linearity correction coil for use in a line deflection circuit having a core which is made of a magnetic material and is bias magnetized by at least one permanent magnet, which coil is characterized in that an additional winding is provided on the core.
Embodiments of the invention will now be described by way of example, with reference to the accompanying diagrammatic drawings, in which
FIG. 1 is the circuit diagram of a known circuit arrangement for line deflection in which the line deflection current is east-west modulated,
FIG. 2 shows the distorted image which is displayed on the screen when the circuit arrangement of FIG. 1,
FIG. 3 is a graph explaining the observed defect, and
FIGS. 4 and 7 show embodiments of the circuit arrangement according to the invention by which this defect can be cancelled.
FIG. 1 is a greatl
simplified circuit diagram of a line deflection circuit of an image display apparatus, not shown further. The circuit includes the series combination of a line deflection coil L y , a linearity correction coil L and a trace capacitor C t , which series combination is traversed by the line deflection current i y . The collector of an npn switching transistor T r and one end of a choke coil L 1 are connected to a junction point A of a diode D, a capacitor C r and the said series combination. The other end of the choke coil is connected to the positive terminal of a supply voltage source which supplies a substantially constant direct voltage V b and to the negative terminal of which the emitter of transistor Tr is connected. This negative terminal may be connected to earth. The other junction point B of elements D and C r and of the series combination of elements C t , L y and L is connected to one terminal of a modulation source M for east-west correction which has its other terminal connected to earth. Diode D has the pass direction shown in the FIG. To the base of transistor Tr line-frequency switching pulses are supplied. In known manner the said series combination is connected to the supply voltage source during the deflection interval (the trace time), diode D and transistor Tr conducting alternately. During the retrace time these elements are both cut off. Under these conditions the current i y is a sawtooth current. The coil L, which has a saturable ferrite core which is bias-magnetized by means of at least one permanent magnet, serves to correct the linearity of the current i y during the trace time, whilst the capacitance of the capacitor C t is chosen so that the currenct i y is subjected to what is generally referred to as S correction. During the retrace time, at point A pulses are produced the amplitude of which is much higher than that of the voltage V b and would be constant in the absence of modulation source M. Information from the field deflection circuit, not shown, of the image display apparatus and line retrace pulses, the latter for example by means of a transformer, are supplied in known manner to modulation source M. Amplitude-modulated line retrace pulses having a field-frequency parabolic envelope, as indicated in the FIG., are produced at point B. During the line trace time the voltage at point B is zero. Thus the current i y is given the desired field-frequency modulated form which is also shown in FIG. 1.
The amplitude of the envelope in point B at the beginning and at the end of the field trace time and the amplitude of this envelope at the middle of the said time can both be adjusted so that the image displayed on the display screen of the display tube (not shown) has the correct substantially rectangular form. If, however, the required modulation depth is comparatively large, a linearity error of the line deflection is produced which cannot be removed by means of the correction coil L.
FIG. 2 shows the image of a pattern of vertical straight lines as it is displayed on the screen with the correction coil L adjusted so that horizontal linearity is satisfactory along and near the central horizontal line. In FIG. 2 the defect is exaggerated. It is found that horizontal linearity is defective in other areas of the screen so that the vertical lines are displayed correctly in the right-hand half of the screen but as curves in the left-hand path, the defect increasing as the line is farther to the left.
This phenomenon can be explained with reference to FIG. 3. In this FIG. the inductance L of the linearity correction coil is plotted as a function of the magnetic field strength H. In the absence of current, H has a value H 0 owing to the bias magnetization. If an approximately linear sawtooth current i (t) as shown in the b
ottom left-hand part of FIG. 3 flows through the coil, the field strength H varies proportionally about the value H 0 , for the mean value of the current is zero. Because the curve of L is not linear, the variation L(t) of L, which is shown in the top right-hand part, is not a linear function of time. The resulting curve may be regarded as composed of a linear component and a substantially parabolic component which is to be taken into account when choosing the capacitance of capacitor C t . Because owing to the east-west modulation the amplitude of current i(t) varies, the amplitude of L(t) also varies. This implies a field-frequency variation of L which is non-linear. This variation is undesirable. In the case of a small variation of the amplitude of current i(t) the variation of L(t) can be more or less neglected, but this is no longer possible when the amplitude of current i(t) varies greatly owing to the east-west modulation. L(t) varies according to different curves. FIG. 3 shows two of such curves and also illustrates the fact that the undesirable variation of L(t) is greatest at the beginning of the trace time and smallest at the end thereof.
FIG. 4 shows a circuit arrangement in which the defect described can be corrected. On the core of the correction coil L of the circuit of FIG. 1 an additional winding L 2 is provided. Winding L 2 is connected to a current source which produces a compensating current i 2 which has a line-frequency sawtooth variation and a field-frequency amplitude modulation. The envelope here also is parabolic, however, with a shape opposite to that of deflection current i y , that is to say having a minimum at the middle of the field trace time. The direction of current i 2 and the winding sense of winding L 2 relative to that of coil L are chosen so that the magnetic field produced in the core by winding L 2 has the same direction as the field produced by coil L. Hence the two field strengths are added. The amplitude of current i 2 and the turns number of winding L 2 can be chosen so that current i y flows through inductances the total value of which is not dependent upon the field frequency. The curve L(t) of FIG. 3 remains substantially unchanged. Consequently the undesirable field-frequency modulation is removed without variation of the bias magnetization, which would have been varied if current i 2 were a field-frequency current. Obviously the same result can be achieved by a choice such of the direction of current i 2 and of the winding sense of winding L 2 that the two field strengths are subtracted one from the other, whilst the curvature of the envelope of current i 2 has the same direction as that of the envelope of current i y .
The current source of FIG. 4 may be formed in known manner by means of a modulator in which a line-frequency sawtooth signal is field-frequency modulated, the envelope being parabolic. FIG. 5 shows a circuit arrangement in wh
ich current i 2 is produced by the modulation source which provides the east-west correction. In FIG. 5, the source M of FIG. 1 comprises a diode D', a coil L' and two capacitors C' r and C' t , which elements constitute a network of the same structure as the network formed by elements D, L y , C r and C t . The capacitor C' t is shunted by a modulation source V m which supplies a field-frequency parabolic voltage having a minimum at the middle of the field trace time. With the exception of the linearity correction means to be described hereinafter, the circuit arrangement of FIG. 5 was described in more detail in U.S. Pat. No. 3,906,305. Hence it will be sufficient to mention that the capacitances of capacitors C r and C' r and of a capacitor C 1 connected between junction point A and earth and the inductance of coil L' are chosen so that the three sawtooth currents flowing through L y , L' and L 1 have the same retrace time. The capacitances of capacitors C t and C' t , which are large, are ignored. When voltage V b is constant, current i y is subjected to the desired east-west modulation having the form shown in FIG. 1.
Coil L y is connected in series with correction coil L, and winding L 2 is connected in series with coil L'. FIG. 5 shows that the current flowing through winding L 2 has the same waveform as the current i 2 of FIG. 4, for its envelope has the same shape as the voltage supplied by source V m . By a suitable choice of the number of turns of winding L 2 it can be ensured that the linearity correction remains the same for every line during the field trace time.
Modified embodiments of the circuit arrangement of FIG. 5 can also be used. FIG. 6 shows such a modified embodiment in which the capacitive voltage divider C r , C' r of FIG. 5 is replaced by an inductive voltage divider by means of a tapping on coil L 1 . A capacitor C 2 is included between the tapping and the junction point of diodes D and D', whilst capacitor C' t here forms part of two networks C t , L y and C' t , L' traversed by a sawtooth current. In FIG. 6 modulation source V m is connected via a choke coil L 3 to the junction point of D, D', C 2 and
C' t . One end of winding L 2 is connected to the junction point of capacitor C' t and the coil L, whilst the other end is connected to earth via coil L'. The capacitances of capacitors C 1 and C 2 and the location of the tapping on coil L 1 are chosen so that the sawtooth currents flowing through L y , and L' and L 1 have the same retrace time, whilst the field-frequency linearity defect of FIg. 2 is cancelled by correctly proportioning winding L 2 . Other east-west modulators are known in which the step of FIGS. 5 and 6 can be used. An example is the modulator described in the publication by Philips, Electronic Components and Materials: "110° Colour television receiver with A66-140X standard-neck picture tube and DT 1062 multisection saddle yoke," May 1971, pages 19 and 20, which modulator also comprises two diodes and a compensation coil L', which are arranged in a slightly different manner. In another example the east-west modulator and the line deflection generator are included in a bridge circuit whilst they are decoupled from one another by means of a bridge coil which has the same function as coil L' in FIGS. 5 and 6. In these circuit arrangements coil L and winding L 2 may be arranged in the same manner as in FIG. 6. The same applies to an east-west modulator using a transductor the operating winding of which is in series with the deflection coil.
In the abovedescribed embodiments of the circuit arrangement according to the invention the compensating current i 1 is provided by transformer action. In the embodiment of FIG. 7 the current source which supplies the current i 2 is connected in parallel with correction coil L, i.e., without an auxiliary winding. In this embodiment the east-west modulation is achieved not by means of a modulator, but by means of the fact that the supply voltage V b is the super-position of a field-frequency parabolic voltage on the direct voltage. In this known manner the supply source also is the modulator.
It will be seen that in the embodiments of FIGS. 4, 5 and 6 current i 2 counteracts the east-west modulation of deflection current i y . It was found in practice, however, that this counteraction is slight.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Line oscillator synchronizing circuit:A television receiver having a line synchronizing circuit wherein gate pulses for keying the synchronizing signal are derived from the oscillator signal, the gate pulses being positioned, by means of an auxiliary phase control loop, substantially symmetrical relative to
an edge of a reference signal also derived from the oscillator signal. The auxiliary control loop also eliminates the influence of phase variations occurring in the line deflection circuit.1. A television receiver having a line deflection circuit and a line synchronizing circuit, said line synchronizing circuit comprising a controllable oscillator, a signal derived therefrom being applicable to said line deflection circuit; a pulse generator coupled to said oscillator for deriving pulse-shaped gate signals; a coincidence detector; means for applying said pulse-shaped gate signals and pulse-shaped line synchronizing signals to said coincidence detector; a first phase discriminator coupled to said coincidence detector for determining the phase difference between said line synchronizing signal and a reference signal derived from said oscillator signal; a first low-pass filter for smoothing the output voltage from said first phase discriminator, said controllable oscillator being coupled to said first low-pass filter whereby the output therefrom controls the frequency and/or phase of said controllable oscillator; a second phase discriminator for determining the interval between the center instant of a pulse of said pulse-shaped gate signal and the center instant of an edge occurring in said reference signal; a second low-pass filter for smoothing the output voltage from said second phase discriminator; and means for controlling the center instant of the edge in said reference signal using the output from said second low-pass filter; wherein said line synchronizing circuit further comprises gate means having a first input terminal for receiving the output from said pulse generator and a second input terminal for receiving an output signal from said line deflection circuit, said gate means also having an output terminal for generating the gate pulses for said coincidence detector and said second phase dis
Description:
BACKGROUND OF THE INVENTION
The invention relates to a television receiver comprising a line synchronizing circuit and also comprising a line deflection circuit, the line synchronizing circuit comprising a controllable oscillator for generating an oscillator signal applicable to the line deflection circuit and being provided with means for applying a pulse-shaped line synchronizing signal and a pulse-shaped gate, which which is derived from the oscillator signal by means of a pulse generator, to a coincidence stage, an output terminal of which is connected to a first phase discriminator for determining the phase difference between the synchronizing signal and a reference signal which is also derived from the oscil
lator signal, the line synchronizing circuit being further provided with a first low-pass filter for smoothing the output voltage of the first phase discriminator, the frequency and/or phase of the oscillator being controllable by the first smoother voltage thus obtained, with a second phase discriminator for determining the interval between the center instant of a gate pulse and the center instant of an edge occurring in the reference signal, and with a second low-pass filter for smoothing the output voltage of the second phase discriminator, the center instant of said edge being controllable by means of the second smoothed voltage thus obtained. Such a line synchronizing circuit is disclosed in Applicant's Dutch Patent Application No. 7511633 (PHN.8169). In this known circuit a second phase control loop, which comprises the second discriminator and the second low-pass filter ensures that said two instants substantially coincide so that the gate pulses are substantially symmetrical relative to the edge of the reference signal. Consequently, the gate pulses may be of a very short duration, so that the insensitivity to noise is increased. The output signal of the circuit can be applied to the line deflection circuit ensuring that its phase is fixed relative to that of the received line synchronizing pulses.
It may, however, happen that phase variations occur in the line deflection circuit, for example because the turn-off time of a switch, usually a power transistor, present in said circuit is not constant. In order to reinstate the desired fixed phase relation between the deflection and the received synchronizing pulses, it is proposed in said patent application to apply the output signal of the present circuit first to a phase discriminator in which it is compared in known manner to a signal originating from the deflection circuit. This implies a third phase control loop. Consequently, the synchronizing circuit becomes complicated and more difficult to be implemented in integrated form.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a synchronizing circuit comprising only two phase-controlled loops and, to this end, the receiver according to the invention is characterized by a gate having a first input terminal for receivng the output signal of the pulse generator and a second input terminal for receiving an output signal of the line deflection circuit and having an output terminal for applying the gate pulses thus obtained to the coincidence state and to the second phase discriminator.
DESCRIPTION OF THE DRAWINGS
The invention will be further explained by way of non-limitative example with reference to the accompanying figures in which
FIG. 1 shows a block diagram of an implementation of a portion of a television receiver according to the invention and
FIGS. 2 and 3 show wave forms which may be used therein.
In FIG. 1 reference numeral 1 denotes the input terminal of the line synchronizing circuit. Line synchronizing pulses, having the line repetition frequency f H , i.e., for example, 15,625 or 15,750 Hz, are present at the input terminal. These pulses are derived, in known manner in the television receiver, not shown, of which the circuit forms part, from the received signal in a synchronizing-separation stage and are applied to an input terminal of an AND-gate 2. FIG. 2a shows the variation versus the time of these pulses. Herein the symbol T H denotes the line period, i.e. approximately 64 μs.
FIG. 2b shows the variation of gate pulses which are applied to another input terminal of gate 2 and which are generated in the circuit in a manner still to be explained hereafter. FIG. 2b shows each gate pulse symmetrically relative to the center instant t o of the corresponding line synchronising pulse of FIG. 2a. As known this pulse has a duration of, for example, 4.5 to 5 μs. The gate pulses have a somewhat longer duration of, for example, 7.7 μs. The output signal of gate 2 is applied to a controllable switch 3. If the pulses at the inputs of gate 2, as in FIG. 2, occur at least partly simultaneously, then switch 3 is made conductive for the duration of that portion of the line synchronizing pulses.
Switch 3 is supplied with a line frequency reference signal which is generated in a manner still to be explained hereafter and which is shown in FIG. 2c. In the synchronized state it has a falling edge at instant t o and a rising edge at an instant which is, for example, in the center of the time interval between instant t o and the corresponding instant t 1 one cycle later.
In these circumstances the voltage shown in FIG. 2d is present at the output terminal of switch 3. After smoothing by means of a low-pass filter 4, a d.c. voltage is produced which is supplied to a voltage controlled oscillator 5, whose frequency and/or phase is adjusted hereby. Switch 3 behaves as a phase discriminator by means of which the falling edge of the signal of FIG. 2c is adjusted to the center instant t o of the pulse of FIG. 2a. If the frequency of the signal of FIG. 2c deviates from the value f H , then the phase difference between this signal and that of FIG. 2a varies continuously. The control voltage supplied
to oscillator 5 is then an a.c. voltage, namely until the two frequencies are equal again, wherafter the control voltage is a d.c. voltage.
Oscillator 5 is also supplied with a d.c. voltage V o of, for example, 3 V on which the control voltage just mentioned is superimposed. Voltage V o may correspond to the nominal frequency of the line synchronizing pulses in accordance with the television standard for which the television receiver is suited. In the described implementation, however, the signal generated by oscillator 5 has, in the nominal case, a frequency 2f H which is double the line frequency. This signal is applied to a frequency divider circuit 6 in which the frequency is divided by the number of lines per picture in the relevant standard, being, for example, 625 or 525. A field frequency signal of, for example, 50 or 60 Hz, is available at an output terminal of divider circuit 6 in the synchronized state of the line phase-controlled loop, which signal can be applied to a field synchronizing circuit of known type.
The sawtooth signal shown in FIG. 3a is derived from the signal of oscillator 5, the sawtooth signal being applied to a pulse generator 7. By means of a d.c. voltage level V 1 which is applied to generator 7 and which is generated in a manner still tobe explained, the sawtooth signal is converted in this generator into a pulse-shaped signal (FIG. 3b). The leading edges of these pulses and the rising edges in FIG. 3a occur simultaneously; while the instant of occurrence of the trailing edges of the pulses is determined by the value of voltage V 1 . These pulses are applied to a frequency dividing circuit 8 which, for example, is a binary divider circuit of known type, for example a master-slave flip-flop. The output signals thereof have the line frequency f H . The signal at an output terminal Q s thereof (see FIG. 3c) changes levels each time a falling edge occurs in the signal of FIG. 3b, while the signal at an output terminal Q m of circuit 8 (see FIG. 3d) changes levels each time a rising edge occurs in the signal of FIG. 3b. This implies that the signal of FIG. 3b is fixed relative to the time axis while the position of the signal of FIG. 3c depends on the value of voltage V 1 .
The signal at terminal Q m is the signal which is applied as a reference signal to switch 3, while the signal at terminal Q s is applied to a pulse shaper 9. The output signal thereof has the variation which is suitable for being applied, possibly via a driver stage, to a line output stage 10. Stage 10 supplies a line frequency current to the deflection coil, not shown, for the horizontal deflection in the picture display tube. Stage 10 comprises a switch usually a power transistor, whose turn-on time is relatively short, while its turn-off time is considerable, namely in the order of 10 μs. This is caused by the fact that the charge carriers, which are present in an excess in the saturated transistor, must first be removed. As known, the turn-off time depends on variations in the load of stage 10, for example the beam current in the picture display tube. In known manner, the adverse influence of such variations can be compensed for, for example by including a phase-controlled loop between oscillator 5 and the output of stage 10, this loop comprising a phase discriminator, a low-pass filter as well as an oscillator or a phase-shifting network. A signal originating from the output of stage 10 is used as a reference signal for this loop. Dutch Patent Application No. 7103465 (PHN.5499) discloses such a phase-controlled loop. A compensation is effected in the circuit of FIG. 1 in a different manner, which will be explained in the further course of this description.
The sawtooth voltage of FIG. 3a is also applied to a pulse generator 11 in which the sawtooth signal is converted into the pulse-shaped signal of FIG. 3e by means of a d.c. voltage V 2 applied thereto. The rising edges thereof occur simultaneously with those of FIG. 3a while the falling edges occur at the instants at which the sawtooth signal attains the value V 2 . In this manner the frequency of these pulses would have the double line frequency 2f H . However, the signal at the terminal Q m of divider circuit 8 is also applied to generator 11, thus, each rising edge of this signal cuts off generator 11. Other line frequency signals, for example line flyback pulses originating from stage 10, can also be used for this same purpose. The pulses obtained are applied to an input terminal of an OR-gate 12.
FIG. 3f shows line flyback pulses present in output stage 10, for example across a winding of a transformer thereof. For simplicity they are depicted as sine-shaped waves. They occur from approximately the instant at which the switch in stage 10 is switched-off, that is to say a time 96 after the occurrence of a falling edge of signal Q s (FIG. 3c) which time τ may be variable, while the duration of these pulses is substantially constant. The pulses of FIG. 3f are applied to an input terminal of an AND-gate 13, while another input terminal is connected to terminal Q m of the frequencies divider 8. The output terminal of gate 13 is connected to an input terminal of gate 12.
From FIGS. 3d and 3f it appears that the output signal of gate 13 has a leading edge from a time τ after the occurrence of a falling edge of signal Q s , and a trailing edge at the instant at which a falling edge of signal Q m occurs. The output signal of gate 12 has a leading edge at the same instant at which the leading edge of the output signal of gate 13 occurs and a trailing edge at the same instant at which the trailing edge of generator 11 occurs. The pulses at the output terminal of gate 12 are shown in FIG. 3g and are the gate pulses of FIG. 2b which are applied to gate 2. The leading edges thereof occur at instants which depend on the delay τ produced in output stage 10, while the instants at which the trailing edges occur depend only on the, optionally adjustable, voltage V 2 . These pulses do not contain any information concerning the signal Q m , in spite of the fact that Q m is one of the input signals of gate 13, which information is, for the rest not necessary. Said input signal is only used for removing the portion of the pulse of FIG. 3f occurring after the falling edge of signal Q m . The same result can be achieved by means of, for example, a bistable multivibrator, the output signal of which has a leading edge at the same instant as the flyback pulse and a trailing edge at the same instant as the signal of generator 11.
A phase discriminator 14, implemented as a controllable switch, is supplied with the reference signal at the output terminal Q m of divider circuit 8 (FIG. 3d) as well as with the gate pulses originating from gate 12. Switch 14 conducts during the occurrence of the gate pulses and its output voltage is smoothed by a low-pass filter 15.
The smoothed voltage obtained, as well as a d.c. voltage V 3 , derived from the supply voltage of the circuit, are supplied to a differential amplifier 16. The output voltage thereof is the voltage V 1 which is supplied to pulse generator 7. As a result thereof the duration of the pulses of FIG. 3b and, consequently, also the position along the time axis of the edges of signal Q s , depend on the value of the smoothed voltage. Elements 7 to 16 inclusive constitute an auxiliary control loop which operates so that each gate pulse of FIG. 3g remains symmetrical relative to the edge of the reference signal of FIG. 3d and, consequently, also relative to the center instant of the synchronizing pulse of FIG. 2a. This determines the duration of the gatepulse. Since, if the duration of the synchronizing pulse is 4.7 μs while the duration of the flyback pulse is 12 μs and if the interval between the starting instant of the flyback pulse (that is to say that of the blanking pulse in the received video signal) and the starting instant of the synchronizing pulse is equal to 1.5 μs, then the period of time between the leading edge in FIG. 2b and instant t o is equal, in the ideal case, to 1.5 +(4.7/2)=3.85 μs. Due to the action of voltage V 2 in stage 11 and of the auxiliary control loop, the trailing edge in FIG. 2b occurs 3.85 μs after instant t o , so that the duration of the gate pulse is 7.7 μs. In practice the pulse will be somewhat longer but it is obvious that, due to this rather short period of time, it is ensured that the sensitivity of the circuit to noise and disturbances is low, which especially holds for disturbances caused by reflection.
The final state of the auxiliary control loop is attained after a time which is independent of the frequency of oscillator 5, while the auxiliary control loop cannot experience an adverse influence from noise and disturbances. The time constant of filter 15 can therefore be chosen at will. Dutch Patent Application No. 7511633 (PHN.8169) describes all this more extensively. Because, however, the variations of delay τ can be rapid, this time constant must be many times smaller, for example ten times as small as that of filter 4.
If the frequency of oscillator 5 varies, for example due to a variation in the supply voltage, or if the frequency of the received line synchronisation pulses varies, for example because a switch-over to another transmitter is effected, the oscillator 4 is so adjusted by the operation of the control loop formed by elements 3 to 8 inclusive that the situation indicated in FIG. 2 occurs. This implies that the waveforms of the FIGS. 3a, 3b, 3c, 3d and 3e are shifted along the time axis until the leading edges of the pulses of FIG. 3a occur at the center instants of the synchronizing pulses of FIG. 2a. In this way it is ensured that also the trailing edges of the pulses of FIG. 3e and, consequently, also those of the gate pulses of FIGS. 3g and 2b are fixed relative to the synchronizing pulses.
If now the delay τ between the falling edge of the signal of FIG. 3c and the starting instant of the flyback pulse of FIG. 3f vary and/or if a shift of the gate pulses of FIG. 3g occurs relative to the reference signal of FIG. 3d as a result of spread in the properties of the various components and/or of inequalities of the transition times in the various transistors etc., then the pulse generator 7 is so adjusted by the operation of auxiliary control loop 7 to 16 inclusive that the situation shown in FIG. 3d occurs. In this situation the input voltage, originating from filter 15, of differential amplifier 16 is substantially equal to the voltage V 3 . Prior to the occurrence of this situation, said voltages deviate from one another, so that voltage V 1 varies. As a result, the position of the trailing edges of the pulses of FIG. 3b and, consequently, also the position of the edges of the signal Q s of FIG. 3 c change. Thus, the signal Q s is shifted along the time axis until the flyback pulses of FIG. 3f are fixed relative to the synchronizing pulses of FIG. 2a. Therefore, it is ensured, by means of the auxiliary control loop, that the influence of variations in time τ are considerably reduced and that the gate pulses shift only a little relative the reference signal, so that they may be of a short duration.
As in the previously mentioned Dutch Patent Application No. 7511633, the d.c. voltage V o , which is supplied to oscillator 5 in the absence of a control voltage originating from filter 4 and cause the oscillator to generate a signal having the nominal frequency, may be derived from the output voltage of filter 15. Also a pulse may be derived from one of the signals of FIG. 2 or FIG. 3, for example the sawtooth signal of FIG. 3a, for keying out the color synchronizing signal, which pulse may also be used for stabilising the black level. A coincidence detector may be used with which it is possible to reinstate the at least partly simultaneous occurrence of the gate pulses and the synchronizing pulses. In the case of non-coincidence, the gate pulses assume a longer duration, or the supply load for the gate pulses to gate 2 is interrupted, while the loop gain of control loop 3 to 8 inclusive is increased. As known, the locking-in property of the loop is improved by means of this switch-over.
As this loop gain cannot be infinitely large, the situation shown in FIG. 2 does not as a rule occur, that is to say there always remains a residual error. This means that the edge of the reference signal of FIG. 2c occurs, in the nominal state, at an instant which slightly deviates from instant t o , so that the voltage supplied to oscillator 5 slightly deviates from the value V o . The circuit of FIG. 1 is improved in this respect.
The control voltage which is supplied to oscillator 5 is also supplied to an amplifier 17. The output voltage thereof is the voltage V 2 which is supplied to pulse generator 11. Amplifier 17 is so dimensioned that the abovementioned error is corrected. If the error is, for example, such that the falling edge of the signal of FIG. 2c occurs somewhat too early relative to instant t o then amplifier 17 must have a gain of such a value and such a sign that voltage V 2 in FIG. 3a increases by a suitable value. This cause the falling edges in FIG. 3e and, consequently, in FIG. 3g to be shifted to the left. Due to the operation of the auxiliary control loop, when the gate pulses of FIG. 3g are substantially symmetrical in the synchronized state relative to instant t o , the rising edges in FIG. 3g are shifted to the right so that the gate pulses are given a shorter duration. The consequence of the outlined shift is that the flyback pulses occur somewhat later than is the case in FIG. 3f, so that also the signal Q s of FIG. 3c is shifted to the right. This means an identical shift of the falling edges of the signal of FIG. 3b and, consequently, a decrease of voltage V 1 . In this manner a small error is introduced in the auxiliary control loop so that the flyback pulses are slightly shifted relative to the reference signal, whose position along the time axis does not depend on voltage V 1 but, as a consequence of which, with a suitable design of amplifier 17, the flyback pulses are fixed relative to the synchronizing pulses. The center instant of a flyback pulse thus occurs at instant t o . A certain value can be assigned to voltage V 2 in the absence of a control voltage at the input terminal of amplifier 17; the duration of the gate pulses is adjusted by this setting. It will be obvious that a similar adjustment can also be applied in the case amplifier 17 is not present.
The foregoing discusses the idealised wave forms of FIGS. 2 and 3. It is obvious that both the leading and trailing edges in, for example, FIG. 2b and the edges in, for example, FIG. 2c have in practice no infinitely steep slope but a kind of sawtooth shape. Consequently, the symmetry aimed at means that the center instants of the pulses in FIG. 2b and of the edges in FIG. 2c occur substantially simultaneously, wherein center instant must be understood to mean in the first-mentioned case the instant located in the center of the time interval between which the signal is higher than half its maximum value and in the second case the instant at which half of the maximum value is achieved.
During the locking-in of the auxiliary control loop the position of the gate pulses varies in the described circuit along the time axis while that of the reference signal remains unchanged. It is clear that an implementation can be realised in which the position of the gate pulses is not affected
by the control, while the position of the reference signal varies.
With the exception of capacitors which are part of filters 4 and 15, the described circuits can be integrated in a semiconductor body. In the preceding the oscillator has in the nominal state double the line frequency. It will be obvious that this is not essential for the invention, that is to say the invention can also be used if the nominal frequency is the line frequency or another multiple thereof.
The invention relates to a television receiver comprising a line synchronizing circuit and also comprising a line deflection circuit, the line synchronizing circuit comprising a controllable oscillator for generating an oscillator signal applicable to the line deflection circuit and being provided with means for applying a pulse-shaped line synchronizing signal and a pulse-shaped gate, which which is derived from the oscillator signal by means of a pulse generator, to a coincidence stage, an output terminal of which is connected to a first phase discriminator for determining the phase difference between the synchronizing signal and a reference signal which is also derived from the oscil
lator signal, the line synchronizing circuit being further provided with a first low-pass filter for smoothing the output voltage of the first phase discriminator, the frequency and/or phase of the oscillator being controllable by the first smoother voltage thus obtained, with a second phase discriminator for determining the interval between the center instant of a gate pulse and the center instant of an edge occurring in the reference signal, and with a second low-pass filter for smoothing the output voltage of the second phase discriminator, the center instant of said edge being controllable by means of the second smoothed voltage thus obtained. Such a line synchronizing circuit is disclosed in Applicant's Dutch Patent Application No. 7511633 (PHN.8169). In this known circuit a second phase control loop, which comprises the second discriminator and the second low-pass filter ensures that said two instants substantially coincide so that the gate pulses are substantially symmetrical relative to the edge of the reference signal. Consequently, the gate pulses may be of a very short duration, so that the insensitivity to noise is increased. The output signal of the circuit can be applied to the line deflection circuit ensuring that its phase is fixed relative to that of the received line synchronizing pulses. It may, however, happen that phase variations occur in the line deflection circuit, for example because the turn-off time of a switch, usually a power transistor, present in said circuit is not constant. In order to reinstate the desired fixed phase relation between the deflection and the received synchronizing pulses, it is proposed in said patent application to apply the output signal of the present circuit first to a phase discriminator in which it is compared in known manner to a signal originating from the deflection circuit. This implies a third phase control loop. Consequently, the synchronizing circuit becomes complicated and more difficult to be implemented in integrated form.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a synchronizing circuit comprising only two phase-controlled loops and, to this end, the receiver according to the invention is characterized by a gate having a first input terminal for receivng the output signal of the pulse generator and a second input terminal for receiving an output signal of the line deflection circuit and having an output terminal for applying the gate pulses thus obtained to the coincidence state and to the second phase discriminator.
DESCRIPTION OF THE DRAWINGS
The invention will be further explained by way of non-limitative example with reference to the accompanying figures in which
FIG. 1 shows a block diagram of an implementation of a portion of a television receiver according to the invention and
FIGS. 2 and 3 show wave forms which may be used therein.
In FIG. 1 reference numeral 1 denotes the input terminal of the line synchronizing circuit. Line synchroniz
ing pulses, having the line repetition frequency f H , i.e., for example, 15,625 or 15,750 Hz, are present at the input terminal. These pulses are derived, in known manner in the television receiver, not shown, of which the circuit forms part, from the received signal in a synchronizing-separation stage and are applied to an input terminal of an AND-gate 2. FIG. 2a shows the variation versus the time of these pulses. Herein the symbol T H denotes the line period, i.e. approximately 64 μs. FIG. 2b shows the variation of gate pulses which are applied to another input terminal of gate 2 and which are generated in the circuit in a manner still to be explained hereafter. FIG. 2b shows each gate pulse symmetrically relative to the center instant t o of the corresponding line synchronising pulse of FIG. 2a. As known this pulse has a duration of, for example, 4.5 to 5 μs. The gate pulses have a somewhat longer duration of, for example, 7.7 μs. The output signal of gate 2 is applied to a controllable switch 3. If the pulses at the inputs of gate 2, as in FIG. 2, occur at least partly simultaneously, then switch 3 is made conductive for the duration of that portion of the line synchronizing pulses.
Switch 3 is supplied with a line frequency reference signal which is generated in a manner still to be explained hereafter and which is shown in FIG. 2c. In the synchronized state it has a falling edge at instant t o and a rising edge at an instant which is, for example, in the center of the time interval between instant t o and the corresponding instant t 1 one cycle later.
In these circumstances the voltage shown in FIG. 2d is present at the output terminal of switch 3. After smoothing by means of a low-pass filter 4, a d.c. voltage is produced which is supplied to a voltage controlled oscillator 5, whose frequency and/or phase is adjusted hereby. Switch 3 behaves as a phase discriminator by means of which the falling edge of the signal of FIG. 2c is adjusted to the center instant t o of the pulse of FIG. 2a. If the frequency of the signal of FIG. 2c deviates from the value f H , then the phase difference between this signal and that of FIG. 2a varies continuously. The control voltage supplied
Oscillator 5 is also supplied with a d.c. voltage V o of, for example, 3 V on which the control voltage just mentioned is superimposed. Voltage V o may correspond to the nominal frequency of the line synchronizing pulses in accordance with the television standard for which the television receiver is suited. In the described implementation, however, the signal generated by oscillator 5 has, in the nominal case, a frequency 2f H which is double the line frequency. This signal is applied to a frequency divider circuit 6 in which the frequency is divided by the number of lines per picture in the relevant standard, being, for example, 625 or 525. A field frequency signal of, for example, 50 or 60 Hz, is available at an output terminal of divider circuit 6 in the synchronized state of the line phase-controlled loop, which signal can be applied to a field synchronizing circuit of known type.
The sawtooth signal shown in FIG. 3a is derived from the signal of oscillator 5, the sawtooth signal being applied to a pulse generator 7. By means of a d.c. voltage level V 1 which is applied to generator 7 and which is generated in a manner still to
be explained, the sawtooth signal is converted in this generator into a pulse-shaped signal (FIG. 3b). The leading edges of these pulses and the rising edges in FIG. 3a occur simultaneously; while the instant of occurrence of the trailing edges of the pulses is determined by the value of voltage V 1 . These pulses are applied to a frequency dividing circuit 8 which, for example, is a binary divider circuit of known type, for example a master-slave flip-flop. The output signals thereof have the line frequency f H . The signal at an output terminal Q s thereof (see FIG. 3c) changes levels each time a falling edge occurs in the signal of FIG. 3b, while the signal at an output terminal Q m of circuit 8 (see FIG. 3d) changes levels each time a rising edge occurs in the signal of FIG. 3b. This implies that the signal of FIG. 3b is fixed relative to the time axis while the position of the signal of FIG. 3c depends on the value of voltage V 1 . The signal at terminal Q m is the signal which is applied as a reference signal to switch 3, while the signal at terminal Q s is applied to a pulse shaper 9. The output signal thereof has the variation which is suitable for being applied, possibly via a driver stage, to a line output stage 10. Stage 10 supplies a line frequency current to the deflection coil, not shown, for the horizontal deflection in the picture display tube. Stage 10 comprises a switch usually a power transistor, whose turn-on time is relatively short, while its turn-off time is considerable, namely in the order of 10 μs. This is caused by the fact that the charge carriers, which are present in an excess in the saturated transistor, must first be removed. As known, the turn-off time depends on variations in the load of stage 10, for example the beam current in the picture display tube. In known manner, the adverse influence of such variations can be compensed for, for example by including a phase-controlled loop between oscillator 5 and the output of stage 10, this loop comprising a phase discriminator, a low-pass filter as well as an oscillator or a phase-shifting network. A signal originating from the output of stage 10 is used as a reference signal for this loop. Dutch Patent Application No. 7103465 (PHN.5499) discloses such a phase-controlled loop. A compensation is effected in the circuit of FIG. 1 in a different manner, which will be explained in the further course of this description.
The sawtooth voltage of FIG. 3a is also applied to a pulse generator 11 in which the sawtooth signal is converted into the pulse-shaped signal of FIG. 3e by means of a d.c. voltage V 2 applied thereto. The rising edges thereof occur simultaneously with those of FIG. 3a while the falling edges occur at the instants at which the sawtooth signal attains the value V 2 . In this manner the frequency of these pulses would have the double line frequency 2f H . However, the signal at the terminal Q m of divider circuit 8 is also applied to generator 11, thus, each rising edge of this signal cuts off generator 11. Other line frequency signals, for example line flyback pulses originating from stage 10, can also be used for this same purpose. The pulses obtained are applied to an input terminal of an OR-gate 12.
FIG. 3f shows line flyback pulses present in output stage 10, for example across a winding of a transformer thereof. For simplicity they are depicted as sine-shaped waves. They occur from approximately the instant at which the switch in stage 10 is switched-off, that is to say a time 96 after the occurrence of a falling edge of signal Q s (FIG. 3c) which time τ may be variable, while the duration of these pulses is substantially constant. The pulses of FIG. 3f are applied to an input terminal of an AND-gate 13, while another input terminal is connected to terminal Q m of the frequencies divider 8. The output terminal of gate 13 is connected to an input terminal of gate 12.
From FIGS. 3d and 3f it appears that the output signal of gate 13 has a leading edge from a time τ after the occurrence of a falling edge of signal Q s , and a trailing edge at the instant at which a falling edge of signal Q m occurs. The output signal of gate 12 has a leading edge at
the same instant at which the leading edge of the output signal of gate 13 occurs and a trailing edge at the same instant at which the trailing edge of generator 11 occurs. The pulses at the output terminal of gate 12 are shown in FIG. 3g and are the gate pulses of FIG. 2b which are applied to gate 2. The leading edges thereof occur at instants which depend on the delay τ produced in output stage 10, while the instants at which the trailing edges occur depend only on the, optionally adjustable, voltage V 2 . These pulses do not contain any information concerning the signal Q m , in spite of the fact that Q m is one of the input signals of gate 13, which information is, for the rest not necessary. Said input signal is only used for removing the portion of the pulse of FIG. 3f occurring after the falling edge of signal Q m . The same result can be achieved by means of, for example, a bistable multivibrator, the output signal of which has a leading edge at the same instant as the flyback pulse and a trailing edge at the same instant as the signal of generator 11. A phase discriminator 14, implemented as a controllable switch, is supplied with the reference signal at the output terminal Q m of divider circuit 8 (FIG. 3d) as well as with the gate pulses originating from gate 12. Switch 14 conducts during the occurrence of the gate pulses and its output voltage is smoothed by a low-pass filter 15.
The smoothed voltage obtained, as well as a d.c. voltage V 3 , derived from the supply voltage of the circuit, are supplied to a differential amplifier 16. The output voltage thereof is the voltage V 1 which is supplied to pulse generator 7. As a result thereof the duration of the pulses of FIG. 3b and, consequently, also the position along the time axis of the edges of signal Q s , depend on the value of the smoothed voltage. Elements 7 to 16 inclusive constitute an auxiliary control loop which operates so that each gate pulse of FIG. 3g remains symmetrical relative to the edge of the reference signal of FIG. 3d and, consequently, also relative to the center instant of the synchronizing pulse of FIG. 2a. This determines the duration of the gate
pulse. Since, if the duration of the synchronizing pulse is 4.7 μs while the duration of the flyback pulse is 12 μs and if the interval between the starting instant of the flyback pulse (that is to say that of the blanking pulse in the received video signal) and the starting instant of the synchronizing pulse is equal to 1.5 μs, then the period of time between the leading edge in FIG. 2b and instant t o is equal, in the ideal case, to 1.5 +(4.7/2)=3.85 μs. Due to the action of voltage V 2 in stage 11 and of the auxiliary control loop, the trailing edge in FIG. 2b occurs 3.85 μs after instant t o , so that the duration of the gate pulse is 7.7 μs. In practice the pulse will be somewhat longer but it is obvious that, due to this rather short period of time, it is ensured that the sensitivity of the circuit to noise and disturbances is low, which especially holds for disturbances caused by reflection. The final state of the auxiliary control loop is attained after a time which is independent of the frequency of oscillator 5, while the auxiliary control loop cannot experience an adverse influence from noise and disturbances. The time constant of filter 15 can therefore be chosen at will. Dutch Patent Application No. 7511633 (PHN.8169) describes all this more extensively. Because, however, the variations of delay τ can be rapid, this time constant must be many times smaller, for example ten times as small as that of filter 4. If the frequency of oscillator 5 varies, for example due to a variation in the supply voltage, or if the frequency of the received line synchronisation pulses varies, for example because a switch-over to another transmitter is effected, the oscillator 4 is so adjusted by the operation of the control loop formed by elements 3 to 8 inclusive that the situation indicated in FIG. 2 occurs. This implies that the waveforms of the FIGS. 3a, 3b, 3c, 3d and 3e are shifted along the time axis until the leading edges of the pulses of FIG. 3a occur at the center instants of the synchronizing pulses of FIG. 2a. In this way it is ensured that also the trailing edges of the pulses of FIG. 3e and, consequently, also those of the gate pulses of FIGS. 3g and 2b are fixed relative to the synchronizing pulses.
If now the delay τ between the falling edge of the signal of FIG. 3c and the starting instant of the flyback pulse of FIG. 3f vary and/or if a shift of the gate pulses of FIG. 3g occurs relative to the reference signal of FIG. 3d as a result of spread in the properties of the various components and/or of inequalities of the transition times in the various transistors etc., then the pulse generator 7 is so adjusted by the operation of auxiliary control loop 7 to 16 inclusive that the situation shown in FIG. 3d occurs. In this situation the input voltage, originating from filter 15, of differential amplifier 16 is substantially equal to the voltage V 3 . Prior to the occurrence of this situation, said voltages deviate from one another, so that voltage V 1 varies. As a result, the position of the trailing edges of the pulses of FIG. 3b and, consequently, also the position of the edges of the signal Q s of FIG. 3 c change. Thus, the signal Q s is shifted along the time axis until the flyback pulses of FIG. 3f are fixed relative to the synchronizing pulses of FIG. 2a. Therefore, it is ensured, by means of the auxiliary control loop, that the influence of variations in time τ are considerably reduced and that the gate pulses shift only a little relative the reference signal, so that they may be of a short duration.
As in the previously mentioned Dutch Patent Application No. 7511633, the d.c. voltage V o , which is supplied to oscillator 5 in the absence of a control voltage originating from filter 4 and cause the oscillator to generate a signal having the nominal frequency, may be derived from the output voltage of filter 15. Also a pulse may be derived from one of the signals of FIG. 2 or FIG. 3, for example the sawtooth signal of FIG. 3a, for keying out the color synchronizing signal, which pulse may also be used for st
abilising the black level. A coincidence detector may be used with which it is possible to reinstate the at least partly simultaneous occurrence of the gate pulses and the synchronizing pulses. In the case of non-coincidence, the gate pulses assume a longer duration, or the supply load for the gate pulses to gate 2 is interrupted, while the loop gain of control loop 3 to 8 inclusive is increased. As known, the locking-in property of the loop is improved by means of this switch-over. As this loop gain cannot be infinitely large, the situation shown in FIG. 2 does not as a rule occur, that is to say there always remains a residual error. This means that the edge of the reference signal of FIG. 2c occurs, in the nominal state, at an instant which slightly deviates from instant t o , so that the voltage supplied to oscillator 5 slightly deviates from the value V o . The circuit of FIG. 1 is improved in this respect.
The control voltage which is supplied to oscillator 5 is also supplied to an amplifier 17. The output voltage thereof is the voltage V 2 which is supplied to pulse generator 11. Amplifier 17 is so dimensioned that the abovementioned error is corrected. If the error is, for example, such that the falling edge of the signal of FIG. 2c occurs somewhat too early relative to instant t o then amplifier 17 must have a gain of such a value and such a sign that voltage V 2 in FIG. 3a increases by a suitable value. This cause the falling edges in FIG. 3e and, consequently, in FIG. 3g to be shifted to the left. Due to the operation of the auxiliary control loop, when the gate pulses of FIG. 3g are substantially symmetrical in the synchronized state relative to instant t o , the rising edges in FIG. 3g are shifted to the right so that the gate pulses are given a shorter duration. The consequence of the outlined shift is that the flyback pulses occur somewhat later than is the case in FIG. 3f, so that also the signal Q s of FIG. 3c is shifted to the right. This means an identical shift of the falling edges of the signal of FIG. 3b and, consequently, a decrease of voltage V 1 . In this manner a small error is introduced in the auxiliary control loop so that the flyback pulses are slightly shifted relative to the reference signal, whose position along the time axis does not depend on voltage V 1 but, as a consequence of which, with a suitable design of amplifier 17, the flyback pulses are fixed relative to the synchronizing pulses. The center instant of a flyback pulse thus occurs at instant t o . A certain value can be assigned to voltage V 2 in the absence of a control voltage at the input terminal of amplifier 17; the duration of the gate pulses is adjusted by this setting. It will be obvious that a similar adjustment can also be applied in the case amplifier 17 is not present.
The foregoing discusses the idealised wave forms of FIGS. 2 and 3. It is obvious that both the leading and trailing edges in, for example, FIG. 2b and the edges in, for example, FIG. 2c have in practice no infinitely steep slope but a kind of sawtooth shape. Consequently, the symmetry aimed at means that the center instants of the pulses in FIG. 2b and of the edges in FIG. 2c occur substantially simultaneously, wherein center instant must be understood to mean in the first-mentioned case the instant located in the center of the time interval between which the signal is higher than half its maximum value and in the second case the instant at which half of the maximum value is achieved. During the locking-in of the auxiliary control loop the position of the gate pulses varies in the described circuit along the time axis while that of the reference signal remains unchanged. It is clear that an implementation can be realised in which the position of the gate pulses is not affected
by the control, while the position of the reference signal varies.
With the exception of capacitors which are part of filters 4 and 15, the described circuits can be integrated in a semiconductor body. In the preceding the oscillator has in the nominal state double the line frequency. It will be obvious that this is not essential for the invention, that is to say the invention can also be used if the nominal frequency is the line frequency or another multiple thereof.
PHILIPS 26C970/00R REMBRANDT CHAS
SIS K12I RGB HYBRID AMPLIFIER 4822 212 20307 3122 128 58455 CUT-OFF BEAM CONTROL CIRCUIT.
The RGB Amplifier in the chassis PHILIPS K12 is operating on the G1 instead on katode AS in conventional schemes.
These are realized with HYBRID IC'S technology and they're in ceramic substrate.
PHILIPS CHASSIS K12 (20AX) CRT TUBE RGB AMPLIFIER DETAIL RGB HYBRID AMPLIFIER 4822 212 20307 3122 128 58455
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Hybrid RGB Amplifiers on CRT Socket.
Driving directly: G1 blue G1 red G1 green.Hybrid IC Technology on Ceramic substrate.
1. A hybrid IC comprising:
a substrate including a front face, a back face opposite the front face, and side faces interposed between the front face and the back face which define an outer perimeter of the substrate;
at least one inductor formed on at least one of the front face and the back face of the substrate;
a semiconductor chip mounted on the front face of the substrate by flip-chip bonding;
at least one terminal formed in a predetermined portion of the side faces of the substrate,
wherein the semiconductor chip comprises a plurality of circuit elements provided therein, at least one of the plurality of circuit elements being an MIM capacitor having a metal-insulation film-metal (MIM) structure, the insulation film being composed of a highly dielectric material.
2. A hybrid IC according to claim 1 further comprising at least one matching circuit for matching an input signal to the circuit elements provided inside the semiconductor chip, the matching circuit comprising at least one inductor.
3. A hybrid IC according to claim 2, wherein a wiring pattern is formed of a single metal layer on both the front and back faces of the substrate, the wiring patterns on the respective front and back faces of the substrate being interconnected with each other via through holes, and the at least one inductor comprised in the matching circuit is formed in the wiring pattern on one of the respective front and back faces of the substrate.
4. A hybrid IC according to claim 2, wherein the matching circuit is constituted only by inductors and comprises at least one serial inductor and at least one parallel inductor.
5. A hybrid IC according to claim 4, wherein the parallel inductor comprised in the matching circuit is a spiral-type inductor, outermost wiring of the spiral-type inductor being grounded.
6. A hybrid IC according to claim 2, wherein the inductors comprised in the matching circuit are a spiral-type inductor or a meander-type inductor.
7. A hybrid IC according to claim 2, wherein the matching circuit comprises an inductor and a capacitor, the capacitor being formed inside the semiconductor chip.
8. A hybrid IC according to claim 7, wherein the inductor comprised in the matching circuit is a spiral-type inductor or a meander-type inductor.
9. A hybrid IC according to claim 1, wherein the at least one terminal includes at least an RF terminal functioning as an input terminal for an RF si
gnal, an LO terminal functioning as an input terminal for an LO signal, an IF terminal functioning as an output terminal for an IF signal, a ground terminal, and a supply terminal.---------------------------------------
HERE BELOW A DETAILED DESCRIPTION OF THE PHILIPS CHASSIS K12 CRT DRIVING TECHNOLOGY:
PHILIPS CHASSIS K12 Automatic gray scale control circuit for a color television receiver
The present invention relates to a novel automatic gray scale control circuit for a color television receiver. The circuit senses the cut-off voltage of each gun during the blanking interval, and uses a voltage equal to the cut-off voltage to energize the driver and bias the gun during the video field. The effect is to standardize the emission of each of the three guns against variation in gun cut-off voltage and to produce improved gray scale accuracy at the lowest emission levels. Since the gray scale adjustment is optimized at the lowest emission levels, where the eye is most intolerant to error in hue, one may avoid the need for manual adjustment of the cut-off point, and in cases where the gain does not vary widely from gun to gun, avoid the need for separate gain adjustment. Thus, the circuit may be used either to simplify or eliminate the color set up process at the factory when the receiver is manufactured. It may also reduce or avoid the need for readjustment after periods of use.
PHILIPS CHASSIS K12 CRT Beam current control apparatus:TDA2770 TDA2771
Introducing beam current control:
1. A television picture display device for displaying pictures derived from video signals, said display device comprising a picture display tube having a cathode; an emitter-follower device coupled to said cathode for producing a beam current for driving said picture display tube; a beam current reference level control circuit coupled to said emitter-follower device for controlling the black level of the beam current; a blacker-than-black current compensation circuit incorporated in said beam current reference level control circuit for compensating for a leakage current in said cathode caused by a blacker-than-black level in the video signal; and a blacker-than-black current conduction circuit coupled to said cathode to enable compensation of said leakage current when said beam current is blanked.
2. A television picture display device as claimed in claim 1, wherein the blacker-than-black current conduction circuit comprises a direct current source coupled to the cathode of the picture display tube for keeping said emitter-follower device conductive at the occurrence of a blacker-than-black current in the cathode circuit of the picture display tube thereby allowing for the compensation of said blacker-than-black signal.
3. A television picture display device as claimed in claim 2, wherein the direct current source comprises a first and second resistor serially connected to a supply voltage said first resistor being a.c. coupled to the base of the emitter-follower device.
5. A television picture display device as claimed in claim 4, wherein said difference-forming circuit comprises a current mirror circuit having an input and an output, the input of which is coupled to the collector of the second emitter-follower device and the output to the collector of the first-mentioned emitter-follower device.
6. A television picture display device as claimed in claims 2, 3, 4, 5 or 1, which further comprises a heater, a wehnelt electrode connection of the picture display tube and a leakage current conducting circuit, said heater and said wehnelt electrode connection being coupled to the collector of the first-mentioned emitter-follower device through a said leakage current conducting circuit.
Description:
BACKGROUND OF THE INVENTION Dutch Patent Application No. 7604463 discloses a television picture display device of the above-defined type. In this device a control of the black level, serving as the reference level, of the beam current, to a constant value takes inter alia place by means of a voltage produced across the collector resistor of the emitter-follower. Although in principle this control should furnish a very constant black level this appears not to be the case.
SUMMARY OF THE INVENTION
It is an object of the invention to improve the constancy of the controlled reference level of the beam current.
A television picture display device of the above-defined type according to the invention is therefore characterized in that the beam current reference level control circuit comprises a blacker-than-black current compensation circuit by which the influence of the blacker-than-black current on the beam current reference level control circuit is compensated for while a blacker-than-black current conductive circuit is coupled to the cathode of the picture display tube so that the beam current reference level control circuit can also process a blacker-than-black current of the picture display tube occurring in case of a blanked beam current.
DESCRIPTION OF THE DRAWINGS
The invention will now be further explained with reference to the drawing.
In the drawing
FIG. 1 shows a circuit of a picture display device according to the invention in which the emitter-follower can be kept conductive by means of a direct current and
FIG. 2 shows a further circuit of a picture display device according to the invention in which the emitter-follower current can be taken over by another circuit and passed to a control circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In FIG. 1 a video signal is applied to an input of an adder circuit 3. A control signal originating from an output 7 of a beam current reference level control circuit 9 appears at a further input 5 of the adder circuit 3. This control signal is added to the video signal and the sum signal is applied to the base of an emitter-follower 13 via an amplifier 11. The emitter of the emitter-follower 13 drives a cathode of a picture display tube 14. The collector circuit of the emitter-follower 13 comprises a resistor 15, an end of which is connected to an input 17 of the beam current reference level control circuit 9. The beam current supplied by the emitter-follower 13 flows through this resistor 15.
The input 17 is, at the same time, the input of an amplifier 19, an output 21 of which is connected to an input 25 of an amplifier 27 via a switch 23. A capacitor 29 is also connected to the input 25. The switch 23 closes periodically under the influence of a signal derived from an output 31 of a switching signal generator 33 during the occurrence of the reference level, for example the black level, in the video signal.
Consequently a voltage, which is a measure of the cathode current of the picture display tube 14 during the occurrence of the reference level, is produced across the capacitor 29. This cathode current is composed of a beam current and a leakage current. To compensate for the influence of this leakage current, a switch 35, which is also connected to the output 21 of the amplifier 19, is periodically closed during the occurrence of a blacker-than-black level in the video signal, under the influence of a signal originating from an output 37 of the switching signal generator 33.
The switching signal generator 33 is synchronized with the video signal by a synchronisation signal, applied to an input 39 thereof, obtained from the video signal.
A capacitor 41, connected to the output of the switch 35, now has a voltage there across which is a measure of the leakage current of the cathode of the picture display tube 14. This voltage is supplied to an input 43 of the amplifier 27. The amplifier 27 amplifies the difference of the voltages across the capacitors 29 and 41 so that a control signal is produced at the output 7 thereof which is a measure of the beam current of the picture display tube during the occurrence of the reference level in the video signal. This control signal counteracts changes in the beam current reference level which corresponds to the video signal reference level.
To enable also a compensation of this direct current in the the blacker-than-black compensation circuit, constituted by the switch 35, the capacitor 41 and the difference formation in the amplifier 27, the value of this direct current must not be dependent on the video signal. Therefore this video signal is applied, via a capacitor 49, to the junction of the resistors 45, 47 so that the voltage across the resistor 45 becomes independent of the video signal. The variation in the leakage current in the cathode circuit of the picture display tube 14 can be many times larger than that in the beam current, which condition occurs if the reference level in the video signal is present. The variation in the voltage difference across the capacitors 28 and 41 would then be many times smaller than the variation in the voltage across one of the capacitors 28, 41. This might adversely affect the accuracy of the control system. To prevent this, two resistors 53 and 55 are provided which pass the leakage current from the wehnelt circuit and the heater circuit to the resistor 15 and, consequently, compensate the cathode leakage current to a large extent.
It will be obvious that the direct current supplied to the cathode of the picture display tube may be obtained, if so desired, by means of a transistor connected as a current source. This transistor should then be suitable for a rather high voltage because the voltage at the cathode of the picture display tube may change very much.
In FIG. 2 elements corresponding to elements of the circuit of FIG. 1 have been given the same reference numerals as in FIG. 1. The blacker-than-black current compensation circuit of FIG. 2 is arranged somewhat differently then in FIG. 1. The capacitor 41 is now arranged in series with the output 21 of the amplifier 19 and the two switches 23 and 35, and the input 43 of the amplifier 27 is connected to ground. The switch 35 now operates as a clamping switch which ensures that the blacker-than-black level is connected to ground and the voltage across the capacitor 29 becomes a measure of the beam current occurring at the reference level in the video signal.
A further difference relative to the circuit of FIG. 1 is that the collector circuit of the second emitter-follower 51 includes a circuit which acts as blacker-than-black current conduction circuit and supplies any current flowing to the cathode to the input 17 of the beam current reference level control circuit 9 so that also these currents can be measured. The direct current supply circuit (45, 47) at the cathode of the picture display tube can then be dispensed with.
The collector current of the second emitter-follower 51 is supplied to the resistor 15 via two current mirror circuits. A first current mirror circuit is constituted by a series arrangement of a resistor 57 and a diode 59 in parallel with the series arrangement of the base-emitter path of a transistor 61 and a resistor 63 to a positive supply voltage. The collector current of the transistor 61 is supplied to a second current mirror circuit having a transistor 65 and a diode 67, which is in parallel with the base-emitter path of the transistor 65. The collector of the transistor 61 is connected to the resistor 15 through which the difference in the collector currents of the two emitter-followers 13, 51 now flows. Independent of the direction of the cathode currents of the picture display tube 14, a voltage, which is a measure of that cathode current, is now produced across the resistor 15.
Instead of determining the difference current by means of current mirror circuits in the described manner, it is alternatively possible, if so desired, to use other difference-determining circuits.
If so desired also the measuring data for a beam current limiting control of the resistor 15 can be obtained in the described circuits.
The amplifier 19 may comprise a circuit which limits the amplitude of the video signal outside the instants in which measuring takes place. This may be a circuit operated by an auxiliary signal or a self-switching circuit, for example a diode limiter circuit.
If the picture
It will be obvious that the choice of the measuring instants and the associated occurrence of the reference levels and blacker-than-black levels are not important for the essence of the invention and may be chosen in a suitable manner.
The blacker-than-black current compensation circuits 9 of the above-described embodiments are interchangeable.
The amplifier 27 may comprise a level reference circuit so that the value of the beam current is determined which is associated with the corresponding reference level in the video signal.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I System for stabilizing cathode ray tube operation:
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The invention pertains to a video display apparatus which includes a cathode ray tube having at least one electron gun and means for deriving a source of excitatory voltage signal representative of picture information. In accordance with the invention there is provided a system for stabilizing the display intensity attributable to the electron gun comprising means coupling the source of voltage signal to the gun for generating a stabilized current in the gun, the level of current in the gun being substantially independent of variations in the operating characteristics of the gun. In the preferred embodiment of the invention a test signal is periodically applied at a predetermined level to the gun. A sampler samples the beam current of the gun during the test signal and generates a correction signal in accordance with the sample value. The correction signal is applied to the electron gun so as to stabilize its reference current level.
1. In a television display apparatus which includes a cathode ray tube having at least one electron gun and means for applying a television video signal to said electron gun; a system for stabilizing the display intensity attributable to said electron gun, comprising:
means for generating first and second test signals during the vertical blanking intervals of said television video signal;
means for applying said first and second test signals to said electron gun during first and second portions, respectively, of said vertical blanking intervals;
means for sampling the beam current of said electron gun during said first and second portions and for generating first and second correction signals, respectively, in accordance with the sampled values; and
means for applying said first and second correction signals to said electron gun so as to stabilize the reference current level of said electron gun.
2. The system as defined by claim 1 wherein said first and second correction signals are applied to grids of said electron gun.
3. The system as defined by claim 2 wherein means are provided for maintaining the correction signals during the intervals between successive test signals.
4. The system as defined by claim 1 wherein means are provided for maintaining the correction signals during the intervals between the successive test signals.
5. The system as defined by claim 1 wherein said first and second test signals are at white and black level viedo, respectively.
6. The system as defined by claim 5 wherein said first correction signal is applied as a multiplying factor to said television video signal.
7. The system as defined by claim 6 wherein the corrected television video signal is applied to the control grid of said electron gun.
8. The system as defined by claim 6 wherein the corrected television video signal is applied to the cathode of said electron gun.
9. The system as defined by claim 6 wherein said second correction signal is applied as a DC reference level to the corrected television video signal.
10. The system as defined by claim 1 wherein said means for sampling the beam current comprises a resistor in series with the cathode of said gun.
11. In a video display apparatus which includes a cathode ray tube having a plurality of electron guns and means for applying a plurality of television video signals representative of color picture information to said electron guns; a system for balancing the color screen temperature of said cathode ray tube, comprising:
means for generating first and second test signals during the vertical blanking intervals of said television video signal;
means for applying said first and second test signals to said electron guns during first and second portions, respectively, of said vertical blanking intervals;
means for sampling the beam curre
nt of each electron gun during said first and second portions and for generating first and second correction signals, respectively, for each electron gun in accordance with the sampled values; and means for applying said first and second correction signals to their respective electron guns so as to balance the screen color temperature of said cathode ray tube.
12. The system as defined by claim 11 wherein said first and second correction signals are applied to grids of said electron guns.
13. The system as defined by claim 12 wherein means are provided for maintaining the correction signals during the intervals between successive test signals.
14. The system as defined by claim 11 wherein means are provided for maintaining the correction signals during the intervals between successive test signals.
15. The system as defined by claim 11 wherein said first and second test signals are at white and black level video, respectively.
16. The system as defined by claim 15 wherein said first correction signal is applied as a multiplying factor to each of said plurality of television video signals.
17. The system as defined by claim 16 wherein the corrected plurality of television video signals are applied to the control grids of their respective electron guns.
18. The system as defined by claim 16 wherein the corrected plurality of television video signals are applied to the cathodes of their respective electron guns.
19. The system as defined by claim 16 wherein said second correction signals are applied as DC reference levels to the corrected television video signals.
20. The system as defined by claim 11 wherein said means for sampling the beam current comprises a plurality of resistors in series with the cathode of said electron guns.
Description:
BACKGROUND OF THE INVENTION
This invention relates to improvements in video display apparatus and, more particularly, to a system for stabilizing the display intensity or "color temperature" of a cathode ray tube. The subject matter of this invention is related to subject matter disclosed in copending U.S. application Ser. No. 572,128 of C. W. Smith and R. H. McMann, filed of even date herewith and assigned to the same assignee.
Conventional television display systems employing kinescope cathode ray tubes are subject to performance degradation resulting from instabilities in the operating characteristics of the kinescope or the circuits which drive or bias the kinescope. Prior techniques have been developed which serve to stabilize the signals driving a kinescope. For example, the drive voltages applied to the cathodes of a color kinescope can be stabilized using a feedback scheme; e.g., circuitry which periodically senses the drive voltage at input "black" and "white" levels of operation and corrects for deviations from standard reference voltages by gain adjustment. DC voltages applied to the kinescope can also be stabilized by using precise voltage regulation techniques.
There remains, however, the recognized problem of kinescope electron gun drift which manifests itself as a drift in screen color temperature in a three gun color kinescope. As the electron guns age, their generated beam current per unit of applied voltage (which can be considered a transconductance function) varies, the variations being generally non-uniform in the three different guns. This is a cause of noticeable and undesirable drifts in the display screen color.
The major sources of drift are: aging or long term variations caused by a gradual decrease in cathode activity, not necessarily constant or uniform for each cathode; and cathode operating temperature. The relatively long term variations in emission are caused by filament voltage changes and heat build-up in the gun area, generally a function of how many hours a display tube has been operating. Dynamic heating of each gun depends on the ratio of gun currents drawn to provide the colored picture being instantaneously presented. For example, a long persisting mostly red field causes red gun current almost exclusively, thereby causing an unbalanced heating of the red cathode, which changes its emission characteristics to a different degree than the other cathodes, this change remaining until relative cooling occurs.
Cathode thermal current, I th , is represented by the Dushman equation: I th = SA 0 T 2 e - b s /T amperes
where S and A 0 are constants and b 0 = Dushman constant ≉ 11,600° for an oxide coated cathode.
The derivative of the natural logarithm of this equation gives the change in emission with respect to temperature change: dI th /I th = 2 + (b 0 /t ) (dT/T)
the temperature of the CRT cathode is approximately 1,160° K, which yields (dI th /I th) = 12dT/T
typical ambient temperature variations, such as in a display monitor, are about 40° C, so that the net change of gun current is of the order of 12 . 40/1,160 ≉ 40%
Therefore, a 1° C change in cathode temperature yields about a 1% change in gun current, if the gun is fixed bias and not near cut-off.
It is an object of the present invention to provide a stabilizing system which overcomes the problems set forth.
SUMMARY OF THE INVENTION
The invention pertains to a video display apparatus which includes a cathode ray tube having at least one electron gun and means for deriving a source of excitatory voltage signal representative of picture information. In accordance with the invention there is provided a system for stabilizing the display intensity attributable to the electron gun comprising means coupling the source of voltage signal to the gun for generating a stabilized current in the gun, the level of current in the gun being substantially independent of variations in the operating characteristics of the gun.
In the preferred embodiment of the invention a test signal is periodically applied at a predetermined level to the electron gun. A sampler samples the beam current of the gun during the test signal and generates a correction signal in accordance with the sample value. The correction signal is applied to the gun so as to stabilize its reference current level.
Further features and advantages of the invention will become more readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified diagram of a color television display kinescope;
FIGS. 2A, 2B and 2C are block diagrams of embodiments of the invention which utilize periodically applied test signals;
FIG. 3 is a schematic representation of an embodiment of the invention which employs a "constant current" technique;
FIG. 4 is a schematic representation of another embodiment of the invention employing a differential amplifier; and
FIG. 5 is a schematic representation of another embodiment of the invention employing direct cathode temperature sensing and heater control.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, there is shown a simplified diagram of a color television display cathode ray tube or kinescope 10 as driven by excitatory video voltage signals designated R, G and B, these signals having typical ranges of about 100 volts peak-to-peak. The kinescope 10 has three electron guns, each including a cathode and associated grids. For clarity of illustration, only one of the three guns, designated by reference numeral 11, is represented in some detail, but it will be appreciated that two other complete electron guns (indicated in the Figure by only the two dashed cathodes coupled to the G and B inputs) are normally provided and are substantially identical to the gun 11. Hereinafter, and in the description of the embodiments of the invention, the circuitry associated with only one electron gun in a given kinescope will be described for illustrative clarity, but it will be understood that if the kinescope has two or more guns, similar circuitry can be employed in conjunction with the remaining guns.
The electron gun 11 comprises a cathode 21 and first, second and third grids, 22, 23, and 24, which are sometimes designated as "grid 1," "grid 2," and "grid 3," or as the "control electrode," the "accelerating electrode," and the "focusing electrode," respectively. Generated electrons impinge on an anode 25 near display screen 26 which is coated with an electron-sensitive phosphor as is conventional in the art. Typical voltages applied to the cathode, grid 1, grid 2, grid 3 and the anode are about 235 volts, 150 volts, 700 volts, 5000 volts and 25,000 volts, respectively. In alternate modes of operation, the excitatory voltage input signal may be applied to a control grid with the remaining grid and cathode voltages being set at appropriate values.
Referring to FIG. 2A, there is shown an embodiment of the invention which comprises a system for stabilizing the display intensity or "color temperature" of the electron guns in a kinescope 30. An excitatory voltage signal at input terminal 31, which may be the R, B or G signal in a color system or the luminance signal in a black and white system, is coupled through an adder 41 and DC restorer circuit 42 to grid 1 of the kinescope 30. Cathode 43 is coupled through a resistor R 1 to ground reference. A bias voltage is applied to grid 2 via a voltage amplifier 44 which receives a signal on a line 58A which determines the level of the bias voltage applied to grid 2. Suitable focus and anode voltages are applied to grid 3 and the anode from sources not shown.
The vertical and horizontal synchronizing signals of the composite television signal, available in the television receiver, are applied to a line counter 51 which is adapted to count horizontal scanlines of the television field and to be reset to zero at the end of each television field. The counter generates a first output on a line 51A during the scanlines 15-17 of each television field and a signal on line 51B during lines 18-20 of each television field, all of the lines 15-20 occuring during the vertical blanking period. The signal on line 51A enables a gate 55 and also enables a sample-and-hold circuit 56. The signal on line 51B enables a gate 57 and a sample-and-hold circuit 58. The gates 55 and 57 respectively receive voltages at reference "black level" and "white level." The outputs of gates 55 and 57 are coupled over lines 55A and 57A, respectively, to inputs of the adder 41.
Operation of the system of FIG. 2A is as follows: During lines 15-17 of the vertical blanking interval the gate 55 is enabled so that black level voltage is coupled through adder 41 and circuit 42 to grid 1. With this voltage applied to grid 1 the cathode current should ideally have a certain nominal value that does not vary with the tube life or cathode temperature but, as indicated above in the Background, this is not generally the case in actual practice. The actual cathode current is sampled across resistor R 1 , and a voltage representative of this current is coupled to the sample-and-hold circuit 56 which is enabled to sample the voltage across resistor R 1 during the lines 15-17. The circuit 56 holds the sampled voltage through the subsequent video field and couples the held voltage to circuit 42 via line 56A, this voltage serving to adjust the DC reference level of the output of circuit 42. In this manner, the voltage on line 56A controls the bias level at grid 1 so as to correct for any variations in the cathode current at nominal black level. Thus, for example, if at some point in operation the cathode current for a black level input voltage is lower than its nominal value, the voltage drop across sampling resistor R 1 will also be low. This will decrease the output of sample-and-hold circuit 56 fed to circuit 42 which, in turn, will cause the bias level at grid 1 to decrease (typically, to a less negative value with respect to the cathode). A lesser negative bias level on the control grid 1 will, in turn, cause a proportionate increase in the electron current flowing from cathode 43; the desired result.
Similarly, during lines 18-20 of the vertical blanking period white level voltage is applied via adder 41 and amplifier 42 to grid 1, and during this time the cathode current is sampled by circuit 58 which is enabled to sample by the signal on line 51B. During the remainder of the television field, the bias voltage applied to grid 2, via voltage amplifier 33, is a function of the voltage which had been sampled by circuit 58. For example, in an instance where the cathode current sensed at a white level voltage input is lower than the nominal value, the resultant low voltage sampled by circuit 58 will cause the grid 2 accelerating voltage to decrease. This causes the sampled voltage at black level to appear too negative (when next sampled during the succeeding vertical blanking interval) which, in turn, results in a decrease in grid bias by the black level circuit causing the desired increase in beam current over prior conditions, as previously described.
The embodiment of FIG. 2B is similar to that of FIG. 2A except that the output of sample-and-hold circuit 58 (which is a measure of the sampled white level current) is coupled to an analog multiplier circuit 59, which is in series with DC restorer circuit 52. In this embodiment, corrections resulting from both the white level and black level measurements are achieved via grid 1, with operation otherwise being substantially as described above.
In the embodiment of FIG. 2C the electron gun is driven by application of the video signal to the cathode 43 via a complementary emitter-follower 120 which comprises NPN transistor 121 and PNP transistor 122. (The system to the left of blocks 42 and 56 is the same as in FIG. 2B). The transistor emitters are coupled to the cathode 43 of kinescope 30 and the transistor bases receive the video signal from DC restorer circuit 42. The collector of transistor 121 is coupled to a suitable bias voltage, e.g., 150 volts, and the collector of transistor 122 is coupled to ground reference potential through sampling resistor R 1 .
In operation, during the lines 15-20 the test signals are applied via circuit 42 and cathode 43 is driven while the cathode current is sampled by resistor R 1 , a typical value for which is 1K ohm. Transistor 122 is "on" during the white level test signal (output of circuit 42 about 25 volts) and the black level test signal (output of circuit 42 about 125 volts), and the gun current-representative voltages sampled across resistor R 1 are coupled to the appropriate sample-and-hold circuits as previously described. During the active portion of the television field the analog multiplier 59 and DC restorer circuit 42 apply appropriate corrections, with transistor 122 normally "on." During rapid lighter-to-darker transitions of the video signal the transistor 121 turns momentarily "on" and the tube capacitance and stray capacitance (collectively represented by C in the Figure can be thought of as charging. Diode D 1 prevents inordinate voltage drops across R 1 during the active picture area when R 1 is not used for sampling.
In the embodiment of FIG. 3 the video voltage signal at terminal 61 is coupled to cathode 71 of a kinescope 75 by the parallel combination of capacitor 62 and amplifier 63 in a series with resistor R 2 . Amplifier 63 comprises transistors 64 and 65 and has a voltage gain of about 5 and an output capability of about 500 volts. The resistor R 2 is selected to be substantially greater than the input impedance of the cathode 71 and preferably has a resistance at least five times higher than the cathode resistance. Since the effective cathode resistance is the inverse of the gun transconductance (about 8.6 micromhos), a suitable value for R 2 is of the order of 600K ohms. Accordingly, the amplifier 63 in conjunction with resistor R 2 operates as a so-called "constant current" source, which effectively transforms the voltage signal at terminal signal to a current source input to the cathode 71, this current source input being relatively insensitive to variations in the kinescope characteristics. Since normal wiring capacitance and electron gun interelectrode capacitance render high frequency response impractical in a high impedance amplifier drive, the higher frequency portions of the video signal are shunted across the amplifier by capacitor 62 which may have a typical value of about 0.05 microfarads. The higher frequency signals arrive at substantially the same relative level as the low frequencies, thereby preserving their relationship. This is because the lower frequency signals are amplified by a factor of 5 and then undergo a one-fifth loss by virtue of the voltage divider action of resistor R 2 and the cathode impedance.
FIG. 4 shows a further embodiment wherein the video voltage signal at an input terminal 81 is applied to one input of a differential amplifier comprising transistors 82, 83 and 84. The output stage 84 drives the grid 1 electrode of kinescope 90 through series peaking inductor L 1 and shunt peaking inductor L 2 . The cathode 91 of kinescope 90 is coupled to ground reference potential through resistor R 3 which is used to continuously monitor the cathode current, the line 89 coupling a voltage representative of the cathode current to the other input of the differential amplifier; viz., the base of transistor 83.
In operation, the voltage developed across resistor R 3 is proportional to the cathode current. This voltage, for a stable transconductance, should be in a stable relationship with respect to input voltage at terminal 81, and R 3 is selected empirically at a value, typically about 2K ohms, which generates a sample voltage nominally equal to the input voltage at terminal 81. When a deviation exists between the inputs to transistors 82 and 83, the output of the differential amplifier adjusts up or down to correct for the difference, thereby adjusting control of the drive to grid 1 and correcting for drifts in the kinescope transconductance.
A characteristic of the circuit of FIG. 4 is that it linearizes the electron gun transfer function which normally is non-linear, the non-linear function conventionally being known as "gamma" of the kinescope. Television video signals are conventionally precorrected for the gamma of the kinescope. In a color kinescope the gamma may be different for each gun, making it difficult to match the effective light output attributable to each gun over the grey scale; a problem known as "tracking" in the prior art. The present invention allows use of an inverse gamma circuit (which eliminates the precorrection in the conventional television signal) and the linearized gun transfer functions reduce tracking problems.
The invention has been described with reference to particular embodiments, but it will be understood that variations within the spirit and scope of the invention will occur to those skilled in the art. For example, the circuits of the "constant current" generator of FIG. 3 or the differential amplifier of FIG. 4 may be of other suitable forms. Also, in the embodiment of FIG. 2, sampling could be achieved during any suitable blanking or active period. The beam could be deflected off the tube face during sampling time to avoid displaying the trace during this time. Finally, stabilization of cathode temperatures could be achieved directly, such as by providing heater/thermistor stabilization circuits for each cathode. A suitable circuit is shown in FIG. 5 wherein a negative temperature coefficient thermistor 101 is attached to the cathode metal. V 0 is a precision voltage source providing a voltage typically in the range 5-12 volts and R 0 is selected as being substantially equal to the resistance of the thermistor at nominal cathode temperature. If the cathode becomes unduly hot, the resistance of thermistor 101 will decrease which, in turn, causes the voltage at terminal 103 to decrease. This results in a decreased output of operational amplifier 102, so that the cathode heater drive is reduced, as desired. Insufficient cathode temperature can be seen to cause the opposite effect.
This invention relates to improvements in video display apparatus and, more particularly, to a system for stabilizing the display intensity or "color temperature" of a cathode ray tube. The subject matter of this invention is related to subject matter disclosed in copending U.S. application Ser. No. 572,128 of C. W. Smith and R. H. McMann, filed of even date herewith and assigned to the same assignee. Conventional television display systems employing kinescope cathode ray tubes are subject to performance degradation resulting from instabilities in the operating characteristics of the kinescope or the circuits which drive or bias the kinescope. Prior techniques have been developed which serve to stabilize the signals driving a kinescope. For example, the drive voltages applied to the cathodes of a color kinescope can be stabilized using a feedback scheme; e.g., circuitry which periodically senses the drive voltage at input "black" and "white" levels of operation and corrects for deviations from standard reference voltages by gain adjustment. DC voltages applied to the kinescope can also be stabilized by using precise voltage regulation techniques.
There remains, however, the recognized problem of kinescope electron gun drift which manifests itself as a drift in screen color temperature in a three gun color kinescope. As the electron guns age, their generated beam current per unit of applied voltage (which can be considered a transconductance function) varies, the variations being generally non-uniform in the three different guns. This is a cause of noticeable and undesirable drifts in the display screen color.
The major sources of drift are: aging or long term variations caused by a gradual decrease in cathode activity, not necessarily constant or uniform for each cathode; and cathode operating temperature. The relatively long term variations in emission are caused by filament voltage changes and heat build-up in the gun area, generally a function of how many hours a display tube has been operating. Dynamic heating of each gun depends on the ratio of gun currents drawn to provide the colored picture being instantaneously presented. For example, a long persisting mostly red field causes red gun current almost exclusively, thereby causing an unbalanced heating of the red cathode, which changes its emission characteristics to a different degree than the other cathodes, this change remaining until relative cooling occurs.
Cathode thermal current, I th , is represented by the Dushman equation: I th = SA 0 T 2 e - b s /T amperes
where S and A 0 are constants and b 0 = Dushman constant ≉ 11,600° for an oxide coated cathode.
The derivative of the natural logarithm of this equation gives the change in emission with respect to temperature change: dI th /I th = 2 + (b 0 /t ) (dT/T)
the temperature of the CRT cathode is approximately 1,160° K, which yields (dI th /I th) = 12dT/T
typical ambient temperature variations, such as in a display monitor, are about 40° C, so that the net change of gun current is of the order of 12 . 40/1,160 ≉ 40%
Therefore, a 1° C change in cathode temperature yields about a 1% change in gun current, if the gun is fixed bias and not near cut-off.
It is an object of the present invention to provide a stabilizing system which overcomes the problems set forth.
SUMMARY OF THE INVENTION
The invention pertains to a video display apparatus which includes a cathode ray tube having at least one electron gun and means for deriving a source of excitatory voltage signal representative of picture information. In accordance with the invention there is provided a system for stabilizing the display intensity attributable to the electron gun comprising means coupling the source of voltage signal to the gun for generating a stabilized current in the gun, the level of current in the gun being substantially independent of variations in the operating characteristics of the gun.
In the preferred embodiment of the invention a test signal is periodically applied at a predetermined level to the electron gun. A sampler samples the beam current of the gun during the test signal and generates a correction signal in accordance with the sample value. The correction signal is applied to the gun so as to stabilize its reference current level.
Further features and advantages of the invention will become more readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified diagram of a color television display kinescope;
FIGS. 2A, 2B and 2C are block diagrams of embodiments of the invention which utilize periodically applied test signals;
FIG. 3 is a schematic representation of an embodiment of the invention which employs a "constant current" technique;
FIG. 4 is a schematic representation of another embodiment of the invention employing a differential amplifier; and
FIG. 5 is a schematic representation of another embodiment of the invention employing direct cathode temperature sensing and heater control.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, there is shown a simplified diagram of a color television display cathode ray tube or kinescope 10 as driven by excitatory video voltage signals designated R, G and B, these signals having typical ranges of about 100 volts peak-to-peak. The kinescope 10 has three electron guns, each including a cathode and associated grids. For clarity of illustration, only one of the three guns, designated by reference numeral 11, is represented in some detail, but it will be appreciated that two other complete electron guns (indicated in the Figure by only the two dashed cathodes coupled to the G and B inputs) are normally provided and are substantially identical to the gun 11. Hereinafter, and in the description of the embodiments of the invention, the circuitry associated with only one electron gun in a given kinescope will be described for illustrative clarity, but it will be understood that if the kinescope has two or more guns, similar circuitry can be employed in conjunction with the remaining guns. The electron gun 11 comprises a cathode 21 and first, second and third grids, 22, 23, and 24, which are sometimes designated as "grid 1," "grid 2," and "grid 3," or as the "control electrode," the "accelerating electrode," and the "focusing electrode," respectively. Generated electrons impinge on an anode 25 near display screen 26 which is coated with an electron-sensitive phosphor as is conventional in the art. Typical voltages applied to the cathode, grid 1, grid 2, grid 3 and the anode are about 235 volts, 150 volts, 700 volts, 5000 volts and 25,000 volts, respectively. In alternate modes of operation, the excitatory voltage input signal may be applied to a control grid with the remaining grid and cathode voltages being set at appropriate values.
Referring to FIG. 2A, there is shown an embodiment of the invention which comprises a system for stabilizing the display intensity or "color temperature" of the electron guns in a kinescope 30. An excitatory voltage signal at input terminal 31, which may be the R, B or G signal in a color system or the luminance signal in a black and white system, is coupled through an adder 41 and DC restorer circuit 42 to grid 1 of the kinescope 30. Cathode 43 is coupled through a resistor R 1 to ground reference. A bias voltage is applied to grid 2 via a voltage amplifier 44 which receives a signal on a line 58A which determines the level of the bias voltage applied to grid 2. Suitable focus and anode voltages are applied to grid 3 and the anode from sources not shown. The vertical and horizontal synchronizing signals of the composite television signal, available in the television receiver, are applied to a line counter 51 which is adapted to count horizontal scanlines of the television field and to be reset to zero at the end of each television field. The counter generates a first output on a line 51A during the scanlines 15-17 of each television field and a signal on line 51B during lines 18-20 of each television field, all of the lines 15-20 occuring during the vertical blanking period. The signal on line 51A enables a gate 55 and also enables a sample-and-hold circuit 56. The signal on line 51B enables a gate 57 and a sample-and-hold circuit 58. The gates 55 and 57 respectively receive voltages at reference "black level" and "white level." The outputs of gates 55 and 57 are coupled over lines 55A and 57A, respectively, to inputs of the adder 41.
Similarly, during lines 18-20 of the vertical blanking period white level voltage is applied via adder 41 and amplifier 42 to grid 1, and during this time the cathode current is sampled by circuit 58 which is enabled to sample by the signal on line 51B. During the remainder of the television field, the bias voltage applied to grid 2, via voltage amplifier 33, is a function of the voltage which had been sampled by circuit 58. For example, in an instance where the cathode current sensed at a white level voltage input is lower than the nominal value, the resultant low voltage sampled by circuit 58 will cause the grid 2 accelerating voltage to decrease. This causes the sampled voltage at black level to appear too negative (when next sampled during the succeeding vertical blanking interval) which, in turn, results in a decrease in grid bias by the black level circuit causing the desired increase in beam current over prior conditions, as previously described.
The embodiment of FIG. 2B is similar to that of FIG. 2A except that the output of sample-and-hold circuit 58 (which is a measure of the sampled white level current) is coupled to an analog multiplier circuit 59, which is in series with DC restorer circuit 52. In this embodiment, corrections resulting from both the white level and black level measurements are achieved via grid 1, with operation otherwise being substantially as described above.
In the embodiment of FIG. 2C the electron gun is driven by application of the video signal to the cathode 43 via a complementary emitter-follower 120 which comprises NPN transistor 121 and PNP transistor 122. (The system to the left of blocks 42 and 56 is the same as in FIG. 2B). The transistor emitters are coupled to the cathode 43 of kinescope 30 and the transistor bases receive the video signal from DC restorer circuit 42. The collector of transistor 121 is coupled to a suitable bias voltage, e.g., 150 volts, and the collector of transistor 122 is coupled to ground reference potential through sampling resistor R 1 . In operation, during the lines 15-20 the test signals are applied via circuit 42 and cathode 43 is driven while the cathode current is sampled by resistor R 1 , a typical value for which is 1K ohm. Transistor 122 is "on" during the white level test signal (output of circuit 42 about 25 volts) and the black level test signal (output of circuit 42 about 125 volts), and the gun current-representative voltages sampled across resistor R 1 are coupled to the appropriate sample-and-hold circuits as previously described. During the active portion of the television field the analog multiplier 59 and DC restorer circuit 42 apply appropriate corrections, with transistor 122 normally "on." During rapid lighter-to-darker transitions of the video signal the transistor 121 turns momentarily "on" and the tube capacitance and stray capacitance (collectively represented by C in the Figure can be thought of as charging. Diode D 1 prevents inordinate voltage drops across R 1 during the active picture area when R 1 is not used for sampling.
In the embodiment of FIG. 3 the video voltage signal at terminal 61 is coupled to cathode 71 of a kinescope 75 by the parallel combination of capacitor 62 and amplifier 63 in a series with resistor R 2 . Amplifier 63 comprises transistors 64 and 65 and has a voltage gain of about 5 and an output capability of about 500 volts. The resistor R 2 is selected to be substantially greater than the input impedance of the cathode 71 and preferably has a resistance at least five times higher than the cathode resistance. Since the effective cathode resistance is the inverse of the gun transconductance (about 8.6 micromhos), a suitable value for R 2 is of the order of 600K ohms. Accordingly, the amplifier 63 in conjunction with resistor R 2 operates as a so-called "constant current" source, which effectively transforms the voltage signal at terminal signal to a current source input to the cathode 71, this current source input being relatively insensitive to variations in the kinescope characteristics. Since normal wiring capacitance and electron gun interelectrode capacitance render high frequency response impractical in a high impedance amplifier drive, the higher frequency portions of the video signal are shunted across the amplifier by capacitor 62 which may have a typical value of about 0.05 microfarads. The higher frequency signals arrive at substantially the same relative level as the low frequencies, thereby preserving their relationship. This is because the lower frequency signals are amplified by a factor of 5 and then undergo a one-fifth loss by virtue of the voltage divider action of resistor R 2 and the cathode impedance.
FIG. 4 shows a further embodiment wherein the video voltage signal at an input terminal 81 is applied to one input of a differential amplifier comprising transistors 82, 83 and 84. The output stage 84 drives the grid 1 electrode of kinescope 90 through series peaking inductor L 1 and shunt peaking inductor L 2 . The cathode 91 of kinescope 90 is coupled to ground reference potential through resistor R 3 which is used to continuously monitor the cathode current, the line 89 coupling a voltage representative of the cathode current to the other input of the differential amplifier; viz., the base of transistor 83. In operation, the voltage developed across resistor R 3 is proportional to the cathode current. This voltage, for a stable transconductance, should be in a stable relationship with respect to input voltage at terminal 81, and R 3 is selected empirically at a value, typically about 2K ohms, which generates a sample voltage nominally equal to the input voltage at terminal 81. When a deviation exists between the inputs to transistors 82 and 83, the output of the differential amplifier adjusts up or down to correct for the difference, thereby adjusting control of the drive to grid 1 and correcting for drifts in the kinescope transconductance.
A characteristic of the circuit of FIG. 4 is that it linearizes the electron gun transfer function which normally is non-linear, the non-linear function conventionally being known as "gamma" of the kinescope. Television video signals are conventionally precorrected for the gamma of the kinescope. In a color kinescope the gamma may be different for each gun, making it difficult to match the effective light output attributable to each gun over the grey scale; a problem known as "tracking" in the prior art. The present invention allows use of an inverse gamma circuit (which eliminates the precorrection in the conventional television signal) and the linearized gun transfer functions reduce tracking problems.
PHILIPS CHASSIS K12 Color television CRT beam current correction circuit:
Multi-gun color television display apparatus having for each gun an identical beam current reference level control system wherein the relative position of a reference level in the video signal and a setting voltage of the electron guns are periodically shifted for obtaining, for the control system outside the measuring periods, a coincidence of the reference level in the video signal and the cut-off point of each of the electron guns for a proper color rendition at a low brightness.
Inventors:Janssen, Peter J. H. (Eindhoven, NL) U.S. Philips Corporation (New York, NY)
1. A colour television display apparatus including a beam current reference level contro
l
circuit comprising a measuring circuit included in the cathode circuits
of the electron guns of a multi-gun colour display tube for measuring
during a measuring period the beam current reference level to be
corrected, a level insertion circuit for providing during this measuring
period a reference level in a video signal to be applied to each gun of
the display tube, and a beam current level correction circuit coupled
to the measuring circuit and to a control electrode of each gun of the
display tube for obtaining substantially the same beam current reference
level in each of the electron guns, wherein said control circuit
further comprises a level shift circuit coupled to the electron guns of
the display tube for shifting, at each electron gun over substantially
the same amount, the mutual position of the reference level in the video
signal and a setting voltage of the electron gun occurring outside the
measuring period, relative to that mutual position during the measuring
period.2. A colour television display apparatus as claimed in claim 1, wherein the electron guns of the display tube include screen grids which are coupled to the level shift circuit.
3. A colour television display apparatus as claimed in claim 2, wherein each of said screen grids includes a potentiometer for varying the screen grid voltage, said potentiometers each having one end thereof coupled one to the other in a common connection, and wherein the level shift circuit is coupled to said common connection.
4. A colour television display apparatus as claimed in claims 1, 2 or 3 wherein the measuring circuit comprises a plurality of beam current level correction circuits and means for sequentially coupling the cathodes to each of said beam current level correction circuits.
Description:
BACKGROUND OF THE INVENTION
The invention relates to a colour television display apparatus having a beam current reference level control circuit comprising a measuring circuit included in the cathode circuits of the electron guns of a multi-gun colour display tube for measuring during a measuring period the beam current reference level to be corrected, a level insertion circuit for providing during said measuring period a reference level in a video signal to be applied to each gun of the display tube, and a beam current level correction circuit coupled to the measuring circuit and to a control electrode of each gun of the display tube for obtaining substantially the same beam current reference level in each of the electron guns.
The Dutch Patent Application No. 7202401 (PHN 6130) discloses a colour television display apparatus of the above-mentioned type wherein by the use of a sequence circuit a great portion of the beam current reference level control circuits is in common for the different electron guns of the picture display tube. Then the beam current reference levels of these guns cannot substantially differ from one another. The colour rendition of this apparatus is very constant and substantially independent of disturbing influences. However, in general, the phosphors of the picture display tubes do not have the same efficiency so that the colour rendition for low luminance values is not quite correct if this rendition is correctly adjusted for high luminance values. It would be possible to obtain a correct rendition for low luminance values by using a beam current reference level which would be much lower than the presently used value of some μA. This has practical disadvantages. In addition it would, for example, be possible to perform a correction by means of a circuit with which the beam current reference levels could be adjusted in a ratio matched to the efficiency of the phosphors. This would not only require an adjustment for high luminances but also an additional adjustment at a low luminance.
SUMMARY OF THE INVENTION
It is an object of the invention to obtain a correct colour rendition at that low luminance without an additional adjustment at a low luminance.
To this end a colour television diaplay apparatus of the type mentioned in the preamble according to the invention is characterized in that the electron guns of the picture display tube are coupled to a level shift circuit for shifting at each electron gun, over substantially a same value, the mutual position of the reference level in the video signal and a setting voltage of the electron gun outside the measuring period relative to that mutual position during the measuring period.
The value of the voltage with which the level shift is obtained is the same for all three guns because the beam current reference levels are the same. No adjustment of a mutual amplitude ratio is then required. In addition, the value of this voltage depends substantially only on the beam current reference level value and a plurality of other known and constant factors, so that it can be obtained by means of a proper rating of the circuit so that no adjustment is required.
DESCRIPTION OF THE DRAWING
The invention will now be further explained with reference to the drawings.
In the drawings
FIG. 1 shows on the basis of a diagram the underlying principle of the invention,
FIG. 2 shows, with reference to a block diagram, a colour television receiver having a display apparatus including a level shift circuit according to the invention,
FIG. 3 shows wave forms occurring in different points in the circuit of FIG. 2,
FIG. 4 shows, with reference to a principle circuit diagram, an embodiment of a measuring circuit and a sequence circuit for a display apparatus according to the invention,
FIG. 5 shows, with reference to a principle circuit diagram, an embodiment of a blanking circuit and a beam current level correction circuit for a display apparatus according to the invention,
FIG. 6 shows, with reference to a principle circuit diagram, an embodiment of a level insertion circuit for a display apparatus according to the invention,
FIG. 7 shows, with reference to a block diagram, a pulse generator circuit for a display apparatus according to the invention,
FIG. 8 shows, with reference to a concise principle circuit diagram, a possible embodiment of a level shift circuit in the Wehnelt circuits of the picture display tube for a display apparatus according to the invention and
FIG. 9 shows, with reference to a concise principle circuit diagram, a possible embodiment of a level shift circuit in the cathode circuits of the picture display tube for a display apparatus according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In FIG. 1 a curve C shows how the beam current IB of an electron gun of a picture display tube varies as a function of the Wehnelt cathode voltage VGK. Furthermore, a video signal V is shown as a function of the time with which the Wehnelt cathode voltage can be varied. During a measuring period T the video signal V has a reference level R. In a picture display apparatus according to the invention the beam current is measured during this measuring period T and controlled by means of a beam current reference level control circuit to a constant beam current reference value IBR of some μA. To this end the control circuit continuously readjusts, for example, the Wehnelt cathode voltage VBR. The video signal V has a black level B which substantially coincides with the reference level R.
In a colour display apparatus according to the invention a beam current reference control circuit is present for each electron gun of the picture display tube. If these control circuits are mutually equal--which, for example, can be accomplished in a simple manner by using a sequentially measuring circuit which may be in common for a great portion of the three electron guns--then the beam current reference value of each gun is adjusted to the same value IBR. At this beam current value the phosphors of the picture screen of the picture display apparatus emit a very small quantity of light which, however, due to the difference in efficiency of the phosphors, are not equal so that a certain colour will be somewhat more predominant. Due to the control circuits, this colour remains very constant. With a low-level drive of the picture display tube, so if the video signals are near the black level, a colour deviation occurs which is the smaller in proportion, as the amplitude of the video signals are greater because, for a white rendition occurring at the maximum amplitude, the amplitude ratio of the video signals is readjusted.
In order to obtain a proper colour rendition also at a low video signal amplitude, the luminance must occur for all three colours in the same ratio as with a high video signal amplitude. As known, this can be accomplished by having the black levels B in the video signals coincide with the cut-off points Vco of the electron guns. Then, however, no beam current occurs and a control of that current is impossible.
It has appeared that the difference Vs, between the cut-off voltage Vco and the voltage VBR applied by the control circuits to the guns, is substantially constant even if the voltage VBR must vary, due to disturbing influences, to keep IBR constant. This applies to each of the three electron guns. By shifting the video signal and consequently the black level B outside the measuring period T for each of the three guns over an amount Vs, a proper colour rendition for low video signal amplitudes can yet be obtained while maintaining the beam current reference level control system. This shift is shown in the figure by means of a dotted video signal curve V' having a black level B' which substantially coincides with the cut-off position Vco. An additional method is to shift the characteristics of the electron guns of the picture display tube outside the measuring period T to the position indicated by a dashed-dotted line. A combination of these methods is also possible. Some circuit possibilities for obtaining said level shifts will be indicated below. The value Vs can be calculated from ##EQU1## where k is a constant which depends on the construction of the electron gun and which can be easily determined.
For a cut-off voltage of 175 V the following table applies for the electron guns which are used most frequently at the moment
______________________________________
IBR = 2μ A Vs = 11.56 Volts IBR = 3μ A Vs = 13.23 Volts IBR = 4μ A Vs = 14.56 Volts
______________________________________
If the characteristics of the picture display tube are known, this level shift voltage can, if so desired, be converted into a shift
voltage for a screen grid of the picture display tube.
If the amplitude of the level shift voltage deviates somewhat from these values, the displayed colour will indeed not be perfectly identical, during the occurrence of the black level in the video signal, to the colour when the white level occurs but a considerably more accurate colour rendition is yet obtained at low video signal amplitudes than if no level shift were used.
In FIG. 2 an RF, IF and detector section 1 has an input 3 to which a colour television signal to be processed may be applied. This results in a luminance signal Y at an output 5 of section 1, a chrominance signal Chr at an output 7 and a synchronizing signal S at an output 9.
The synchronizing signal S is applied to an input 11 of a time base generator 13. Deflection currents are obtained from two outputs 15 and 17 which are connected to a deflection coil system 19 of a display tube 21, and an EHT, for feeding an anode 25 of the display tube 21, is obtained from an output 23 of the time base generator 13.
An output 27 of the time base generator 13 supplies line flyback pulses to an input 29 of a pulse generator 35 and an output 31 supplies field flyback pulses to an input 33 of the pulse generator 35. In FIG. 3 these pulses are represented by the waveforms 201 and 202, respectively. FIG. 3 furthermore shows a number of waveforms 203, 204 . . . 220 and a number of instants t1, t2 . . . t10 which are of interest for the explanation of the operation of the circuit. The waveforms have not been drawn to scale.
The pulse generator 35 has a number of outputs 37, 39, 41, 43, 45, 47, 49, 51, 53 and 55 at which the waveforms 203, 210, 211, 212, 213, 214, 215, 216, 217 and 218, respectively, are available.
The output 55 of the pulse generator 35 is connected to an input 57 of a level insertion circuit 59 whose input 61 is connected to output 5 of section 1 from which it receives the luminance signal Y. The level insertion circuit 59 has an output 63 at which the modified luminance signal represented by waveform 220 of FIG. 3 is available, which, during three line periods t5 -t6, t7 -t8, t9 -t10 at the beginning of a field, comprises a reference level 221 which has been inserted with the aid of the waveform 218 applied to the input 57.
At a further output 65 of the level insertion circuit 59 the waveform 219 is available which is applied to an input 67 of a chrominance signal amplifier 69 for suppressing the chrominance signal applied to an input 71, which is connected to the output 7 of section 1.
The output 63 of the level insertion circuit 59 is connected to an input 73 of a distributor circuit 75 of which three outputs 79, 81, 83 are connected to inputs 85, 87 and 89, respectively, of three blanking circuits 91, 93 and 95, respectively. Inputs 97, 99 and 101 of these blanking circuits 91, 93, 95 are connected to outputs 51, 49 and 47, respectively, of the pulse generator 35 and inputs 103, 105 and 107 are connected to outputs 109, 111 and 113, respectively, of a demodulation and matrix circuit 115, a chrominance signal coming from an output 119 of the chrominance signal amplifier 69 being applied to an input 117 of said demodulation and matrix circuit 115.
The demodulation and matrix circuit 115 produces (B-Y), (G-Y) and (R-Y) colour difference signals at its outputs 109, 111 and 113, respectively. In the blanking circuits 91, 93 and 95, these colour difference signals are added to a modified luminance signal from the distributor circuit 75 to obtain the colour signals R, G and B; the reference signal 221, derived from the luminance signal, being suppressed in a special sequence due to the signals having the waveforms 214, 215 and 216 at the inputs 97, 99 and 101. In this example, such a sequence is adhered to that, in the R-signal, a reference level is left from t5 till t6 only, in the G-signal from t7 till t8 and in the B-signal from T9 till T10. These signals with the relevant reference level are available at outputs 121, 123 and 125 of the blanking circuits 95, 93 and 91, respectively and are fed to inputs 127, 129 and 131 of beam current level correction circuits 133, 135 and 137, respectively, in which these reference levels are coupled to a certain beam current value of a corresponding electron gun of the display tube 21.
The beam current level correction circuits 133, 135 and 137 have outputs 139, 141 and 143, respectively, which are connected to the Wehnelt electrodes of the "red", the "green" and the "blue" gun, respectively, of the display tube 21. Furthermore, inputs 145, 147 and 149 of said blanking correction circuits are connected to the output 37 of the pulse generator 35 in order to supply a blanking signal which, during the time base flyback periods, prevents a signal from being applied to the display tube 21. Inputs 151, 153 and 155 are furthermore connected to outputs 157, 159 and 161 of storage circuits 163, 165 and 167, respectively, of a sequence circuit.
Inputs 169, 161 and 173 of the storage circuits 163, 165 and 167 are connected to outputs 174, 175 and 176 of switches 177, 178 and 179, respectively, whose control signal inputs 183, 184 and 185 are connected to the outputs 39, 41 and 43, respectively, of the pulse generator 35.
The switch 177 conducts only from t5 till t6, switch 178 from t7 till t8 and switch 179 from t9 till t10. Each of these switches feeds a level applied to one of its inputs 180, 181 and 182, respectively, into the relevant storage circuits 163, 165, 167.
The
inputs 180, 181, 182 are connected to an output 186 of a measuring
circuit 187 having an input terminal 189 connected to the interconnected
cathodes of the display tube 21, an input terminal 190 connected to a
positive voltage of 130 volts, an input 191 connected to the output 45
of the pulse generator 35 and an input 192 connected to the output 53 of
the pulse generator 35.The interconnected cathodes of the display tube 21 are also connected to the positive voltage of +130 volts via a parallel connection of a resistor 193 and a diode 194. The screen grids of the guns are each connected to an adjustable tap of potentiometers 195, 196, 197 which are arranged in series with two potentiometers 801, 803 between +130 v and a higher voltage ++.
The measuring circuit 187 transfers a beam-current dependent voltage, which is consecutively caused by the reference level of the signal at each of the Wehnelt electrodes, to switches 177, 178, 179 which retain these voltages in the memory circuits 163, 165, 167 during the field period and which transfer these voltages to the inputs 151, 153, 155 of the beam current level correction circuits 133, 135, 137. During this transfer, the other guns draw no beam current. This results in a stabilisation of the beam current of each gun corresponding to the reference level in the luminance signal, using only one measuring circuit 187 which influences each of the control loops thus obtained in exactly the same manner.
A beam current control thus obtained on a reference level ensures a very good setting of the three guns of the display tube 21 which, at a sufficient gain in the control loop, always results in a constant colour of signals of low brightness, so-called background brightness, independent of, for example, supply voltage and temperature variations.
To ensure that this colour is the proper colour a pulse is supplied via a capacitor 805 to the tops of the parallel-arranged potentiometers 195, 196, 197 which pulse is obtained via an inverting circuit 809 from the output 45 of the pulse generator 35 and which, consequently, has a waveform which is opposite to waveform 213. Each of the screen grids of the picture display tube 21 is supplied with a pulse of substantially the same amplitude so that the setting of the electron gun of the picture display tube 21, during the occurrence of the video signal, is shifted relative to that during the occurrence of the reference level at which the beam current is stabilised. By means of a proper choice of the amplitude of this pulse the black level in the video signal at each electron gun is substantially placed in the cut-off point of this gun. The screen grid potentiometers 195, 196, 197 are adjusted so that the Wehnels voltages are mutually equal during occurrence of a black level. Because the gain factors of the screen grid can somewhat deviate from a standard value the adjustment of potentiometers 195, 196, 197 may differ somewhat. The level shift voltage is supplied to the tops of the potentiometers 195, 196, 197 and consequently has a somewhat different amplitude at the screen grids in a manner which is then accurately adapted to the relevant gain factors of the screen grids. A customary adjusting procedure for a white-signal is now sufficient to obtain a proper rendition at any level of the video signals.
The circuit 809, 805, 195, 196, 197 is used as a level shift circuit with which the cut-off point of each of the electron guns, outside the measuring period, substantially coincides with the black level in the video signals.
A possible implementation of another circuit with which the same results can be achieved and which is operative in the cathode circuit of the picture display tube is shown in FIG. 9.
It is alternatively possible to perform a level correction in each of the video signals. This is illustrated in FIG. 8.
In FIG. 4 corresponding sections have the same reference numerals as in FIG. 2. FIG. 4 illustrates one of the three beam current reference level-clamping control circuits and the common measuring amplifier 187 for the three reference level-clamping control loops, the sequence switches 177 and the beam current level correction circuit 133.
A signal occurring at the cathodes of the display tube 21 causes a voltage across the resistor 193 which voltage is limited by the protection diode 194, which is cut off during the measuring intervals. This voltage is applied to the input terminals 189, 190 of the measuring amplifier 187. The input terminals 189, 190 are connected to the base and emitter, respectively, of a pnp-transistor 301 whose collector is connected to ground via a resistor 303, is grounded with respect to high frequencies via a capacitor 305 and has a negative feedback coupling to the base via a resistor 307.
A signal amplified by the transistor 301 is fed to the base of an npn-transistor 313 via a series connection of a resistor 309 and a capacitor 311. Connected to the base of transistor 303 is the collector of an npn-transistor 315 which serves as a clamping switch, the emitter of the transistor 315 being connected to ground via a series connection of a resistor 317 and two diodes 319 and 321 and the base of the transistor 315 being connected to the input 191 of the circuit 187.
Due to the waveform 213 which is applied to the input 191, the transistor 315 is cut off only during the occurrence of the signal caused by the reference signal 221 at the cathodes of the display tube 21. During the preceding line periods the capacitor 311 has assumed a constant charge condition, (has been clamped) via transistor 315 which is then conducting, as a result of the absence of a signal at the cathodes of the display tube 21, because both the chrominance signal and the luminance signal are then suppressed. The diodes 319 and 321 then provide a clamping level at the base of transistor 313. During the interval t4 -t10, signals caused by the reference level 221 during time intervals t5 -t6, t7 -t8 and t9 -t10, respectively occur at the successive cathodes of the display tube 21. These signals occur at the base of the transistor 313 in amplified form and, via the emitter of the transistor 313 and a series resistor 323, they drive the base of the an npn-transistor 325. The emitter of transistor 325 is connected to the collector of an npn-transistor 327 whose emitter is connected to ground and whose base is connected to the input 192, and via a resistor 329, to ground.
The waveform 217 is fed to the base of the transistor 327 so that, only during the time intervals t5 -t6, t7 -t8, t9 -t10, the emitter of transistor 325 is grounded via transistor 327; and transistor 325 functions as an amplifier so that only then a signal is produced at its collector across a resistor 331. This signal is fed to the base of an npn-transistor 333 which is connected in emitter follower arrangement and whose emitter is connected to the output 186 and via a resistor 335, to ground.
At the output 186, a signal is obtained having levels which are produced by each of the cathodes in succession during the previously mentioned time intervals. These levels are a measure of the beam current of the relevant gun and are transferred via switches 177, 178 and 179 consecutively, to the memory circuit 163 during the time interval t5 -t6, to the memory circuit 165 during the time interval t7 -t8, and to the memory circuit 167 during the time interval t9 -t10.
Switch 177 is formed by two npn-transistors 337, 339, connected in opposition, whose respective bases are connected via resistors 341, 343 to the input 183 which, during the time interval t5 -t6, receives a positive pulse represented by the waveform 210 from output 39 of pulse generator 35. As a result, the two transistors 337 and 339 are conducting during this time interval. These transistors are cut off for the rest of the time. During the time interval t5 -t6 input 180 of the switch 177 is then connected to output 174 thereat and via input 169 of the memory circuit 163, to a resistor 345 whose other terminal is connected to a capacitor 347 whose other side is connected to ground.
In time interval t5 -t6 capacitor 347 is charged to the level occurring at the output 186 of the measuring amplifier 187 which, via the output 157, is fed to the input 151 of the beam current level correction circuit 133 and, by means of which, the beam current, caused by the reference signal 221 in the gun of the display tube 21 connected to the output 199, is maintained constant.
In a similar manner the beam currents of the other guns are stabilized in the time intervals t7 -t8 and t9 -t10.
In FIG. 5 corresponding sections have the same reference numerals as in FIG. 2 and FIG. 4. In FIG. 5 one of the blanking circuits 95 and the corresponding beam current level correction circuit 133 are shown, as well as their relationship with the reference level control circuit referred to in FIG. 4.
A modified luminance signal Ym with the waveform 220 is applied to the input 89 of the blanking circuit 95 which, during the time intervals t5 -t6, t7 -t8 and t9 -t10, contains the reference level 221 which is suppressed from t1 till t5. The input 89 is connected to the base of an npn-transistor 401 whose emitter is grounded via a resistor 403 and whose collector is connected to the emitter of an npn-transistor 407 via a resistor 405. The collector of the transistor 407 is connected to a positive voltage, and the base is connected to the input 107 and receives a red colour difference signal -(R-Y) which is suppressed from t1 till t10.
The output 121 of the blanking circuit 95 is connected to the collector of the transistor 401. Connected to the emitter of the transistor 401 is the emitter of an npn-transistor 409 whose collector is connected to a positive voltage and whose base is connected to the input 101.
A voltage of the waveform 214 is fed to the input 101 so that transistor 409 is conducting during the time intervals t7 -t8 and t9 -t10 due to which the transistor 401 cuts off and transistor 407 draws no current either and the signal at the output 121 is suppressed.
When transistor 409 is not conducting, a combination of the -(R-Y) signal, supplied via the emitter follower 407 and the-Ym signal, supplied via the amplifier transistor 401, is fed to the output 121. This combination is a -R signal containing a reference level corresponding to level 221 during the time interval t5 -t6, said reference level being suppressed in the time intervals t1 -t5 and t6 -t10. Via the input 127 of the beam current level correction circuit 133, this signal is applied to the base of an npn-transistor 411 whose collector is connected to a positive voltage and whose emitter is connected via a resistor 413 to the collector of an npn-transistor 415 whose emitter is grounded via a resistor 417 and whose base is connected to a reference voltage via a resistor 418.
The emitter of the transistor 415 is furthermore connected to the emitters of two npn-transistors 419 and 421 whose collectors are connected to a positive supply voltage.
Via an npn-transistor 423 which is connected as an emitter follower, a level correction voltage applied to the input 151 is transferred to the base of the transistor 419, while a blanking signal with the waveform 203 applied to the input 145 is transferred to the base of the transistor 421. The blanking signal suppresses the beam currents during the line field flyback periods in the usual manner. As the transistor 421 only becomes conducting during these flyback periods, the transistor 415 is cut off and no signal is supplied to the collector of the transistor 415 because the emitter circuit of the transistor 411 is then interrupted.
The level correction voltage applied to the input 151 is fed to the emitter of the transistor 415 via the emitters of the transistors 423 and 419 and influences the direct current through the resistor 413 which is supplied by the transistor 415 and thus the d.c. level of the -R-signal transferred to the collector of the transistor 415 via the emitter of the transistor 411.
The collector of the transistor 415 is connected to the base of an npn-transistor 425 whose collector is connected to a positive supply voltage via a resistor 427 and whose emitter is connected to the base of an npn-transistor 431 via a variable resistor 429. The emitter of the transistor 431 is connected to ground and the collector is connected to the emitter of an npn-transistor 433 whose collector is connected to a positive supply voltage of +130 V via a resistor 435. The base of the transistor 431 receives a negative feedback voltage from the collector of the transistor 435 via a potential divider of resistors 437, 439.
A red colour signal R, amplified by transistors 431 and 433, is obtained from the collector of transistor 433, which signal is fed via the output 139 to the Wehnelt electrode of the red gun of the display tube 21. The gain of the beam current level correction circuit 133 is adjustable with resistor 429 in order to enable a white-point correction. Due to the clamping control loop, a white-point correction hardly affects the beam current which is caused by the reference signal 221 so that the adjustment of the resistor 429 will not change the black level and, thus, neither the colour of the dark portions in the image.
In FIG. 6 the same reference numerals have been used as in FIGS. 2, 4 and 5 for the corresponding sections of the circuit. FIG. 6 shows a level insertion circuit 59.
A luminance signal is applied to the input 61 of said circuit which signal is fed to an input 501 of an amplifier 503. The amplifier 503 furthermore has an input 507, to which a direct voltage is applied, which is adjustable with a potentiometer 509, and which serves for brightness control, and an input 511 to which a blanking signal is applied having the waveform 219 of FIG. 2. The picture black level 22 in waveform 220 is adjustable by means of the potentiometer 509 relative to the level occurring during the blanking periods. The waveform 220 is the luminance signal occurring at the output 63 across an emitter resistor 513 of an npn-transistor 515, which is connected as an emitter follower and whose base is connected to the output 505 of the amplifier 503.
A signal with the waveform 218 is fed to the input 57 of the level insertion circuit 59. Via a capacitor 517 and a resistor 519, said signal is applied to a splitter, one side of which is connected to the base of an npn-transistor 523 via a resistor 521 and the other side to the basis of an npn-transistor 529 via a potential divider of resistors 525, 527.
During the most positive parts of the waveform 218 a low voltage develops across the collector resistor 531 of the transistor 523. The level of the signal in time intervals t5 -t10 lies below the cutoff point of the transistor 523 so that this signal is not contained in the collector signal 219 of the transistor 523. However, due to the potential divider 525, 527, which is connected to a positive voltage, the transistor 529 only responds to the most negative portions of the signal 218 and the transistor 529 is cut off during time intervals t5 -t6, t7 -t8 and t9 -t10 so that positive-going square-wave voltages will then occur on the collector of the transistor 529.
Via a resistor 533, the collector of the transistor 529 is connected to a potential divider with a resistor 535 and a series connection of a diode 536 and a resistor 537. The voltage on the tap of this potential divider has a constant value of +2.2 V which also occurs on the collector of the transistor 529 in the abovementioned time intervals. Via a resistor 538, this voltage is transferred to the base of an npn-transistor 539 whose collector is connected to a positive supply voltage and whose emitter is connected to the emitter of the transistor 515. In the time intervals t5 -t6, t7 -t8 and t9 -t10 the emitter voltage of transistor 539 becomes +1.5 V due to its base voltage so that the transistor 515 is cut off and the reference level 221 is produced at the output 63. For the rest of the time the transistor 539 is cut off and a signal is applied to the output 63 via the transistor 515.
As becomes apparent from the waveform 220 the black level 222 of the signal is also adjustable relative to the constant reference level 221 which, due to the previously discussed beam current reference level control circuits, corresponds to a constant beam current value in each of the guns of the display tube 21.
In FIG. 7, in which the corresponding sections have the same reference numerals as in FIGS, 2, 4, 5 and 6, a block diagram is shown of a possible embodiment of the pulse generator 35.
Field flyback pulses, with a waveform 202 whose trailing edge sets a first section of the shift register from its 0-state to the 1-state, are applied to input 33, which is connected to an input 601 of a shift register 603. Due to line flyback pulses with a waveform 201 applied to each of the five sections of the shift register 603, the second section of the shift register is set from the 0 to the 1 state and the first section is reset to the zero state upon the first line flyback pulse occurring after the trailing edge of the field flyback pulse. The 1 state is shifted one section further in the shift register 603 upon each subsequent line flyback pulse.
The sections of the shift register 603 have outputs 605, 607, 609, 611 and 613 at which, consecutively, the pulses represented in FIG. 3 by the waveforms 204, 205, 206, 207 and 208 arise, which are applied to five inputs 615, 617, 619, 621 and 623 of a gate circuit 625, of which a sixth input 627 is connected to the input 33 for the field flyback pulse. The gate circuit 625 applies an extended field flyback pulse with a waveform 209 to an output 629 which pulse covers the total duration of the original field flyback pulse 202 and the subsequent shift-register output pulses 204, 205, 206, 207 and 208.
The outputs 609, 611 and 613 of shift register 603 are connected to three inputs 631, 633 and 635 of a gate and inverter circuit 637. At an output 639 of this circuit connected to the output 45, this results in a pulse represented by the waveform 213 in FIG. 2, which has the duration of the three pulses 206, 207 and 208 together. This pulse 213 is applied to the clamping switch 315 of the measuring amplifier 187 as described previously.
The output 609 of the shift register 603 is furthermore connected to an input 641 of a gate circuit 643, the output 611 is connected to an input 645 of a gate circuit 647 and the output 613 is connected to an input 649 of a gate circuit 651. The other inputs 653, 655 and 657 of these gate circuits are connected to the line flyback pulse input 29. At an output 659 of the gate circuit 643, which is connected to the output 39, the waveform 210 arises which corresponds to a waveform 206 which has been suppressed during the line flyback period. An output 661 of the gate circuit 647 is connected to the output 41 and carries the waveform 211, i.e. a waveform 207 which is suppressed during the line flyback period, and the output 663 of the gate circuit 651 connected to the output 43 receives waveform 212, i.e. a waveform 208 which is suppressed during the line flyback period. As previously stated, the pulses 210, 211 and 212 serve for sequentially connecting the relevant memory circuits 163, 165 and 167 via the switches 177, 178 and 179 to the output 186 of the measuring circuit 187 during the corresponding line periods at the beginning of each field.
The outputs 659, 661 and 663 of the gate circuits 643, 647 and 651 are furthermore connected to inputs 665, 667 and 669 of a gating and superimposition circuit 671, to an input 673, 675 and 677 of a gate circuit 679 and the outputs 659, 661 are connected pairwise to inputs 681, 683 of a gate circuit 685, the outputs 659, 663 are connected to inputs 687, 689 of a gate circuit 691, the outputs 661, 663 are connected to inputs 693, 695 of a gate circuit 697.
A further input 699 of the gating and superimposition circuit 671 is connected to the output 629 of the gate circuit 625 and an input 701 is connected to the line flyback pulse input 29. An output 703 is connected to the output 55 and supplies the waveform 218 which is a combination of line flyback pulses 201 with an extended field flyback pulse 209 on which inverted waveforms 206, 207 and 208 are superimposed. The waveform 218 is fed to the level insertion circuit 59 where it is split up into a suppression signal and a level insertion signal by amplitude selection at two levels in the signal 218. It will be evident that for circuits for which there is no need to minimize the number of connections between the pulse generator 35 and the level insertion circuit 59, the two signals may alternatively be produced separately in the pulse generator 35 and transferred to the relevant circuit.
An output 705 of the gate circuit 679 is connected to the output 53 at which the waveform 217 develops which occurs during the common time interval of the waveforms 210, 211 and 212 and which is used to render the measuring circuit 187 conductive for the transfer of the measured beam current values to its output 186.
The gate circuit 685 has an output 707 which is connected to output 51 and at which the waveform 216 appears, the gate circuit 691 has an output 709 connected to the output 49 and supplying the waveform 215 and the gate circuit 697 has an output 711 which is connected to the output 47 and at which the waveform 214 appears. During the measurement of the beam current of a gun these waveforms, as previously stated, serve to suppress the beam currents of the other guns by means of the appropriate suppression circuits 95, 93 and 91.
The line flyback pulse input 29 and the field flyback pulse input 33 are furthermore connected to inputs 713 and 715, respectively, of a gate circuit 717 whose output 719 is connected to the output 37. As a result, a combination of field and line flyback pulses appears at this output having the waveform 203 and being employed for suppressing the signal passage through the amplifiers for the R, G and B-signals 133, 135 and 137.
In FIG. 8 in which corresponding sections have the same reference numerals as in the other figures, the video output amplifiers are shown in a corresponding manner as those in FIG. 5. The reference numerals of corresponding sections in the amplifier which were not shown in FIG. 5 are provided with a prime or a double prime respectively.
Instead of being connected to a fixed voltage, the resistors 439, 439', 439" are now connected to an output 811 of an amplitude correction circuit 813, an input 815 of which is connected to the output 45 of the pulse generator 35 and by means of which the amplitude and the location of the pulse are adjusted to the correct value. As a consequence thereof, a pulse having the same amplitude is supplied to each of the bases of the transistors 431, 431' and 431". Because the output amplifiers are highly fedback via the mutually equal resistors 437, 437', 437", the pulse present on the transistor bases is transferred to the collectors of the transistors 433, 433', 433" without disturbing the mutual equality in amplitude. A level shift of the video signals as shown in FIG. 1 now occurs at the Wehnelt electrodes of the picture tube 21 outside the measuring periods of the beam current reference level control circuit.
FIG. 9 shows a possible circuit for causing a level shift in the cathode circuit of the picture display tube outside the measuring period. Corresponding sections have been given the same reference numerals as in the previous figures. The input circuit is shown of the measuring circuit 187 of FIG. 5. The base of the transistor 301 is now connected via a resistor 817 of approximately 1000 Ω to the interconnected cathodes of the picture display tube 21. These cathodes are furthermore connected to the collector of a pnp-transistor 819 whose emitter is connected to a positive voltage (130+Vs). The base of the transistor 819 is connected via a resistor 821 to an output 823 of an inverting circuit 825, an input of which is connected to the output 45 of the pulse generator 35. As a consequence the transistor 819 is cut off during the measuring period and the cathode current flows via the resistor 817 to the measuring circuit 187. The cathode voltage is then substantially +130 V. The transistor 819, which operates as a switch, is kept fully conducting outside the measuring period by the output voltage of the inverting circuit 825 and the cathode voltage then becomes +(130+Vs) Volts, that is to say a desired level shift of Vs Volts occurs.
It will be evident that some modifications to the pulse generator 35 will enable the measuring times to be transferred to other periods and furthermore, if desired, it is possible to measure during, for example, more consecutive line periods per gun, the sequence in which the gun currents are measured also being optional. For line-sequential colour television systems employing a delay device to make the colour information of one or more preceding line periods available, it is desirable, in order to avoid disturbing effects, to commence the suppression in the chrominance signal at least a number of line periods corresponding to the delay time of the delay device prior to the measuring cycle.
The cathodes of the display tube which in the described embodiment are directly interconnected may be interconnected via a resistive network, if desired.
The variable resistors 195, 196 and 197 for the screen grids, shown in FIG. 2 serve to enable adjustment of a favourable operating point for the colour signal output amplifiers with the transistors 431 and 433 because the permissible voltages for the transistors used at present are not yet sufficiently high. Should this be the case, said variable resistors might be omitted, if desired.
It will be evident that, if desired, the reference level control voltages obtained from the storage circuits 163, 165, 167 may affect the settings of the other electrodes of the guns of the display tube 21 in order to enable the beam currents to be maintained constant when driving the guns with a reference level. To influence the Wehnelt electrode as is the case in the present embodiment, the reference level control voltages may alternatively be applied to other points in the circuit such as, for example, in the colour difference signal circuits prior to combination with the luminance signal channel.
The measuring circuit 187 may, for example, alternatively have an input bridged by a switching transistor instead of by the diode 194.
It is obvious that the term multi-gun colour display tube also includes an assembly of several individual display tubes co-operating in the specified manner.
In the favourable embodiment described above the display tube is used as an input sequence switch for the measuring circuit. It is evident that, if desired, a cathode resistor may be included in each of the cathode circuits of the display tube, in which case a separate input sequence switch may be provided between the cathodes and the input of the measuring circuit.
If no sequence circuit is used in the measuring circuit the control systems must be and must remain mutually equal and they must control the relevant beam current control circuits to the same reference level to enable an advantageous use of the measure according to the invention.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I Television display apparatus including a beam current clamping control circuit:
A beam current clamping control circuit in which in case of a too large deviation of the desired value of the field frequency measured beam current an accelerated correction of this deviation is effected.
1. Television display apparatus including a beam current clamping control circuit having a beam current measuring circuit operable by a pulse generator and coupled to a television display tube for measuring, during at least part of a line scan time of a field blanking time a beam current reference level to be corrected, a level insertion circuit for inserting the reference level during the measuring time into a video signal to be applied to the television display tube and a level correction circuit coupled to an output of the measuring circuit and to a control electrode of the television display tube, the measuring circuit including a threshold circuit and a storage circuit, characterized in that the threshold circuit is a circuit which applies a signal to an output thereof when a too large beam current occurs, said output being coupled to an operation signal input of a circuit means for extending the charge correction time of the storage circuit per field period.
2. Television display apparatus as claimed in claim 1, characterized in that the circuit extending the charge correction time is a circuit means for increasing the measuring frequency, whereby a greater number of measurements per unit time is effected.
3. Television display apparatus as claimed in claim 1, characterized in that the circuit extending the charge correction time is a change-over switch a first input of which is coupled to an input of the measuring circuit, a second input is coupled to a beam current independent charging circuit coupled to a supply source and an output is coupled to the storage circuit.
4. Television display apparatus as claimed in claim 1, characterized in that the pulse generator includes a counting circuit having a feedback which can be switched on by the threshold circuit.
5. A beam current clamping control circuit for a television display tube comprising a beam
Description:
The invention relates to television display apparatus including a beam current clamping control circuit comprising a beam current measuring circuit coupled to a television display tube and operable by a pulse generator for measuring during at least part of a line scan time of a field blanking period a beam current reference level to be corrected, a level insertion circuit for inserting during the measuring time the reference level into a video signal to be applied to the television display tube, and a level correction circuit coupled to an output of the measuring circuit and to a control electrode of the television display tube, the measuring circuit including a threshold circuit and a storage circuit.
Television display apparatus of this type is known from U.S. Patent No. 3,562,409 in which the threshold circuit ensures that in case of a too large deviation of the beam current relative to the desired value the drive of the storage circuit is limited.
It is an object of the invention to provide improved television display apparatus of the kind described in the preamble which is characterized in that the threshold circuit is a circuit which in case of occurrence of a too large beam current applies a signal to an output thereof which output is coupled to an operation signal input of a circuit extending the charge corrections time of the storage circuit per field period.
Due to the limiting circuit in the circuit arrangement described in the abovementioned U.S. Patent Specification, in combination with the short measuring time available it could occur in the known circuit arrangement that, for example, after switching on the apparatus a very brightly lit picture occurred for several seconds. The storage circuit must include a capacitor having a fairly large capacitance the charge of which must be corrected in the known circuit with a current limited by the threshold circuit during the measuring time.
As a result of the step according to the invention the threshold circuit does not serve to limit the current intensity during the correction of the charge but to activate a circuit in case of a too large deviation of the nominal beam current, which circuit accelerates a feedback of the beam current to the nominal value by realising an extended charge correction time for the storage circuit. Consequently a feedback of the beam current to a level which is not troublesome can be obtained in a very quick manner without the current intensity in circuit elements correcting the charge of the storage circuit becoming too large.
The extended charge correction time of the storage circuit can be obtained by applying a correction charge from a current source which is independent of the measuring value under the influence of the threshold circuit during a time which is considerably longer than the measuring time, or by increasing the measuring frequency so that a current source which is dependent on the measuring value can recharge the storage circuit more frequently per unit of time.
The invention will now be described with reference to the drawing and some embodiments.
In the drawing:
FIG. 1 illustrates by way of a block-schematic diagram a television display apparatus according to the invention.
FIG. 2 illustrates by way of a block-schematic diagram a further elaboration of a television display apparatus according to the invention,
FIG. 3 likewise illustrates by way of a block-schematic diagram a further embodiment of a television display apparatus according to the invention,
FIG. 4 illustrates partly by way of a block-schematic diagram and partly by way of a principle circuit diagram a colour television display apparatus according to the invention including a sequential measuring circuit and
FIG. 5 shows a number of wave forms as may occur in the circuit of FIG. 4.
In FIG. 1 a video signal is applied to an input 1 of a level insertion circuit 3 which signal is provided with a reference level every time during some line times of a field some time after a field flyback with the aid of a signal obtained from an output 7 of a pulse generator 9 and applied to a further input 5. The video signal with the reference level is passed from an output 11 of the level insertion circuit 3 to an input 13 of a beam current level correction circuit 15. A level correction quantity obtained from an output 19 of a measuring circuit 21 is applied to a further input 17 of the beam current level correction circuit 15. A video signal having a reference level and an added level correction quantity is obtained from an output 23 and is applied to an input 25 of an amplifier 27 an output 29 of which is connected to the wehnelt electrode of a television display tube 31. A cathode of the television display tube 31 is connected to an input 33 of the measuring circuit 21.
The measuring circuit 21 includes a gating circuit 35 connected to the input 33 which applies a quantity dependent on the beam current to an output 37 during the occurrence of the reference level. The gating circuit 35 is arranged with the aid of a gating signal applied to a gating signal input 39 and originating from an output 41 of the pulse generator 9.
The quantity dependent on the beam current produced during the occurrence of the reference level is applied from the output 37 of the gating circuit 35 to an input 43 of a detection circuit 45 and to an input 47 of a threshold circuit 49.
An output 51 of the detection circuit 45 is connected in the normal operating condition to a storage capacitor 53 which constitutes a storage circuit with the circuit arrangement connected thereto and which has a time constant which is long relative to the field period. The beam current level correction quantity occurring at the output 19 of the measuring circuit 21 is then obtained from the storage capacitor 53 which quantity readjusts the beam current to a constant value.
The threshold circuit 49 has an output 55 which is connected to an operation signal input 57 of a circuit 59 extending the charge correction time of the storage circuit. The circuit 59 extending the charge correction time includes a second storage capacitor 60 which can retain a voltage optionally provided by the threshold circuit for some time and a changeover switch 61 an operation signal input 63 of which is connected to the operation signal input 57 of the circuit 59 extending the recharge time. The changeover switch 61 has an input 67 which is connected to the output 51 of the detection circuit 45 and an input 69 which is connected through a resistor 71 to a positive supply voltage. An output 73 of the change-over switch is connected to the storage capacitor 53 and the output 19 of the measuring circuit 21.
In the normal operating condition the change-over switch 61 occupies the position shown and the above-described beam current control occurs.
When the beam current is very large during the measuring time, which means that the voltage at the storage capacitor 53 is very low, threshold circuit 49 applies a voltage to its output 55 which sets the change-over switch 61 to the position not shown and, dependent on the discharge time of the second storage capacitor 60, retains it in that position for some time, for example, several hundred line times. The resistor 71 then constitutes a current source independent of the measuring value which increases the voltage across the storage capacitor 53. During the next measurement the threshold circuit 49 determines whether this increase has been sufficient or not so that the change-over switch 61 can remain in the position shown or must be reset once more for some time.
The pulse generator 9 has an input 75 to which field frequency pulses derived from field synchronising or field flyback pulses are applied and an input 77 to which pulses derived from line synchronizing or line flyback pulses are applied. The input 75 is connected to an input 79 of a shift register 81 which in this case has four sections but of which the number of sections can of course be chosen arbitrarily. A line frequency pulse originating from the input 77 serves as a clock pulse for the shift register 81 into which, for example, at the end of the field flyback time a one is shifted which is shifted one section further at every subsequently occurring clock pulse. The last two sections of the shift register have outputs 83 and 85 which are connected to inputs 87 and 89, respectively, of a gating circuit 91 which has a further input 93 connected to the input 77. The gating circuit 91 supplies signals to two outputs 95 and 97 which signals are applied to the outputs 7 and 41 of the pulse generator 9 and which have the functions described hereinbefore.
In FIG. 2 corresponding components have the same reference numerals as those in FIG. 1. For the description of this Figure reference is made to FIG. 1.
The circuit arrangement of FIG. 2 differs from that of FIG. 1 in that the second storage capacitor 60 of the circuit 59 extending the recharge time of the first storage capacitor 53 is replaced by a trigger circuit 99 a set input of which is the input 57 which is connected to the output 55 of the threshold circuit and a reset input 101 of which is connected to the input 75 of the pulse generator 9 to which the field frequency pulses are applied. An output 103 of the trigger circuit is connected to the input 63 of the change-over switch 61 and to an operation signal input 105 of a second change-over switch 107 in the pulse generator 9. An input 109 of the second change-over switch 107 is connected to an output 111 of the shift register 81 and an input 113 is connected to the input 75 for field frequency pulses from the pulse generator 9. An output 115 of the change-over switch 107 is connected to the input 79 of the shift register 81.
In the position shown of the change-over switches 61, 107 the operation of the circuit arrangement is the same as in the case of FIG. 1. When a too high beam current is detected by the threshold circuit 49, the trigger circuit 99 will be set and the change-over switches 61 and 107 will be brought to the position not shown. The storage capacitor 53 will then be charged through the resistor 71 likewise as in the case of FIG. 1. The change-over switch 107 connects the output 111 of the shift register 81 to its input 79 so that always a one circulates in the shift register 81 and a continuous measurement of the beam current is effected until the threshold circuit 49 no longer detects a too high beam current and due to the output voltage dropping out or due to the next field frequency pulse at the reset input 101 the trigger circuit 99 is reset and the normal state is restored.
In FIG. 3 corresponding components have the same reference numerals as those in FIGS. 1 and 2 and reference is made to the description associated with the relevent Figures.
The circuit arrangement differs from that of FIG. 2 by the absence of the first change-over switch 61. Consequently, when a too high beam current occurs the normal control loop is maintained and only due to the second change-over switch 107 the shift register 81 is enabled so that a strongly increased measuring frequency and an accelerated feedback occurs through the normal control loop to the normal state. The recharge time of the storage capacitor 53 is in this case extended because per field period a larger number of measurements and associated recharges of this capacitor is effected.
FIG. 4 shows a colour television receiver including a circuit arrangement according to the invention in which the principle as described with reference to FIG. 2 is used. The circuit arrangement has a colour television display apparatus having a sequential beam current measuring circuit whose principle is described in prior application Ser. No. 402,159, filed Oct. 1, 1973, now abandoned.
When a colour television signal is applied to an input 201 of a high frequency-intermediate frequency and detection section 203, a luminance signal Y is produced at an output 205, a chrominance signal Chr is produced at an output 207 and a synchronizing signal S is produced at an output 209.
The synchronizing signal S is applied to an input 211 of a time base generator 213 connected to the output 209. Deflection currents for a television display tube 221 are obtained at two outputs 215 and 217 and an EHT for the supply of the display tube 221 is obtained at an output 223.
An output 227 of the time base generator 213 applies line flyback pulses to an input 229 and an output 231 applies field flyback pulses to an input 233 of a pulse generator 235. These pulses are shown in FIG. 5 by the waveforms 529 and 533, respectively.
Furthermore FIG. 5 shows a number of waveforms 537, 509, 514, 544, 548, 520, 539, 541, 543, 547, 549, 551, 553, 656, 555, 565 and 563 and a number of instants t 1 , t 1 +T 1 , t 3 to t 10 , t 10a , and t 10 + T 2 , t 10 + 2T 2 , T 11 , t 11 + T 1 , t 11 + 2 T 1 , and t 12 which are important for explaining the operation of the circuit arrangement. The waveforms are not shown to scale.
The pulse generator 235 has a number of outputs 237, 239, 241, 243, 244, 245, 247, 249, 251, 253, 255 and an input 256 at which the waveforms 537, 539, 541, 543, 545, 547, 549, 551, 553, 555 and 556, respectively, are present.
The output 255 of the pulse generator 235 is connected to an input 257 of a level insertion circuit 259 an input 261 of which is connected to the output 205 of the section 201 and receives the luminance signal Y therefrom. The level insertion circuit 259 has an output 263 at which the modified luminance signal denoted by the waveform 563 of FIG. 5 is produced which includes a reference level 521 during three line times t 5 -t 6 , t 7 -t 8 , t 9 -t 10 at the commencement of the field, which level is inserted with the aid of the wave-form 555 applied to the input 257.
The waveform 565 is then produced at a further output 265 of the level insertion circuit 259, which waveform is applied to an input 267 of a chrominance signal amplifier 269 for suppressing the chrominance signal applied to an input 271 connected to the output 207 of the section 201.
The output 263 of the level insertion circuit 259 is connected to inputs 285, 287 and 289 of suppression and level correction circuits 291, 293 and 295, respectively, inputs 297, 299 and 301 of which are connected to outputs 247, 249 and 251 of the pulse generator 235 and inputs 303, 305 and 307 of which are connected to outputs 309, 311 and 313, respectively, of a demodulator and matrix circuit 315 to whose input 317 a chrominance signal originating from an output 319 of the chrominance signal amplifier 219 is applied.
The demodulator and matrix circuit applies a (B-Y), (G-Y) and (R-Y) colour difference signal to its outputs 309, 311 and 313, respectively. These colour difference signals are combined in the suppression and level correction circuits 291, 293 and 295 with the modified luminance signal applied to the inputs 285, 287 and 289 to form colour signals R, G and B, while as a result of the signals with the waveforms 547, 549, 551 at the inputs 297, 299 and 301 the reference level 521 originating from the luminance signal is suppressed in a special sequence. In this example a sequence is maintained in which only a reference level is left in the R-signal from t 5 to t 6 , in the G signal from t 7 to t 8 and in the B signal from t 9 to t 10 .
The suppression and level correction circuits 291, 293 and 295 furthermore have outputs 339, 341, 343 connected to the wehnelt electrode of the red, blue and green guns of the display tube 221 and inputs 345, 347 and 349 connected to the output 237 of the pulse generator 235 for receiving a suppression signal of the waveform 537 which prevent a signal supply to the display tube 221 during the time base flyback times. Inputs 351, 353 and 355 are furthermore connected to outputs 357, 359 and 361, respectively, of a measuring circuit 362 which outputs are connected to storage capacitors 363, 365 and 367, respectively, whose other ends are connected to earth. The storage capacitors 363, 365 and 367 are connected to switches 377, 378 and 379 respectively, operation signal inputs 383, 384 and 385 of which are connected to outputs 239, 241 and 243, respectively, of the pulse generator 235.
The switch 377 conducts from t 5 to t 6 , the switch 378 conducts from t 7 to t 8 and the switch 379 conducts from t 9 to t 10 . Each of these switches introduces a level applied to an input 381 thereof into the relevant storage capacitors 363, 365, 367.
The cathodes of the television display tube 221 are interconnected and are connected to an input 389 of the measuring circuit 362. Sequentially by each cathode voltages is generated across a resistor 393 connected to the input 389 which resistor is shunted by a diode 394 and is connected at its other end to a voltage of + 130 Volt during the said periods. This generated voltage produces a corresponding voltage across the storage capacitors 363, 365 and 367 which is retained during the next field flyback time and is passed on for beam current control to the inputs 351, 353 and 355 of the suppression and level correction circuits 291, 293 and 295. The two cathodes which are not measured then do not convey any beam current.
An input 391 of the measuring circuit is connected to the output 245 and an input 392 is connected to the output 253 of the pulse generator 235.
The screen grids of the guns of the television display tube 221 are each connected to an adjusting point of potentiometers 395, 396 and 397 between + 130 Volt and a higher voltage ++.
A signal occurring at the cathodes of the television display tube 221 produces a voltage across the resistor 393 which voltage is limited by the diode 394 blocked during the measuring periods. This voltage is applied to the base of a pnp transistor 401 whose emitter is connected to the other end of the resistor 393. The collector of the transistor 401 is connected to earth through a resistor 403, connected to earth through a capacitor 405 for high frequencies and has a negative feedback to the base through a resistor 407.
A signal amplified by the transistor 401 is applied through a series arrangement of a capacitor 409, a resistor 410 and a resistor 411 to the base of an npn transistor 413. The collector of an npn transistor 415 serving as a clamping switch is connected between the resistors 410 and 411. The emitter is connected to a clamping voltage V kl and the base is connected to the input 391 of the measuring circuit 362.
As a result of the waveform applied to the input 391, which waveform is the inverse form of waveform 544, the transistor 415 is cut off during the occurrence of the signal produced by the reference level 521. During the preceding line periods the capacitor 511 has reached a constant charge condition (clamped) through the then conducting transistor 415 because both the luminance signal and the chrominance signal are suppressed and the cathodes of the display tube 221 do not convey any current.
During the period t 4 -t 10 signals caused by the reference level 521 occur successively during the periods t 5 -t 6 , t 7 - t 8 and t 9 - t 10 at the successive cathodes of the display tube 221 which signals are applied in an amplified manner to the base of the transistor 413 and which furthermore appear at the emitter of an npn transistor 412 connected to the base of the transistor 413.
When the signals have an amplitude which is not too large they are passed on by the transmitter 413 through its emitter and a resistor 423 to the base of an npn transistor 425.
When the signals at the base of the transistor 413 have a too large amplitude the emitter of the transistor 412 will become more negative than its base connected to a threshold voltage V dr and this transistor 412 will start conducting and hence operate a set input of a trigger circuit 414 connected to its collector which then provides a positive voltage for its output 416. This positive voltage (waveform 556) is applied to an output 418 which is connected to the input 256 of the pulse generator 235 and which causes a variation to a free-running state which will be described hereinafter, while this voltage also controls the base of an npn transistor 422 through a resistor 420 and the emitter of this transistor is connected to earth while the collector is connected to the base of the transistor 413. The base of this transistor 413 then is no longer controlled because the transistor 422 acts as a short circuit for its input signal. The trigger circuit 414 furthermore has a reset input 424 to which a field flyback pulse (waveform 533) originating from the output 231 of the time base generator 213 is applied so that the trigger circuit 414 is reset every time at the commencement of the field flyback.
In the state in which the beam current is not too large the transistors 412 and 422 do not conduct and the signal is passed on through the transistor 413 to the base of the transistor 425 whose emitter is connected to the collector of an npn transistor 427 whose emitter is connected to earth and whose base is connected through a resistor 428 to the input 392 of the measuring circuit. The collector of the transistor 425 is connected through a resistor 430 to the base of an npn transistor 433 whose emitter is connected through a resistor 435 to the input 381 of the sequence switches 377, 378 and 379.
The collector of the transistor 425 is connected through a resistor 432 to the emitter of an npn transistor 434 arranged as an emitter follower whose base is connected through a resistor 436 to an input 438 of the measuring circuit 362 which is connected to the output 244 of the pulse generator 235 at which the waveform 544 occurs. This transistor 434 conducts during the measuring period and furthermore every time during a number of line times in the field scan time when the pulse generator 235 has acquired a free-running state (waveform 544) due to a too high beam current with the aid of the trigger circuit 414.
The transistor 427 conducts due to the waveform 553 during the measuring periods so that in the periods t 5 -t 6 , t 7 -t 8 , t 9 -t 10 the emitter of the transistor 425 is connected to earth through the transistor 427 and the transistor 425 acts as an amplifier and passes on a signal to the base of the transistor 433 and recharges through its emitter the storage capacitors 363, 365 and 367 during the corresponding periods t 5 -t 6 , t 7 -t 8 and t 9 -t 10 , respectively.
In the state of the circuit arrangement where a too large beam current has been detected and where the trigger circuit 414 is set, the transistor 425 does not conduct due to the short circuit of the base of the transistor 413 so that then the storage capacitors 363, 365 and 367 are recharged by the emitter follower 434, 433 every time during the periods when the waveform 544 is positive. This is effected a large number of times during field scan periods following the set of the trigger circuit 414 so that the storage capacitors are charged quickly to a higher voltage to reduce the beam current through the control loops as quickly as possible again.
The operation of a control loop will now be described. This control loop not only includes the television dislay tube 221 and the measuring circuit 362 but also the suppression and level correction circuit 295.
A modified luminance signal Y m according to the waveform 563 is applied to the input 289 in which signal the reference level 521 is present during the periods t 5 -t 6 , t 7 -t 8 and t 9 -t 10 and which level is suppressed from t 1 to t 5 . The input 289 is connected to the base of an npn transistor 601 whose emitter is connected to earth through a resistor 603 and whose collector is connected through a resistor 605 to the emitter of an npn transistor 607. The collector of the transistor 607 is connected to a positive voltage. The base is connected to the input 307 and receives a red colour difference signal -(R-Y) which is suppressed from t 1 to t 10a .
Furthermore the emitter of the transistor 601 is connected to the emitter of an npn transistor 609 whose collector is connected to a positive voltage and whose base is connected to the input 301.
A voltage having the waveform 547 is applied to the input 301 so that the transistor 609 conducts during the periods t 7 -t 8 and t 9 -t 10 and thus cuts off the transistor 601 so that also the transistor 607 does not convey current and the signal at the collector of the transistor 601 is suppressed.
When the transistor 609 does not conduct a signal is generated at the collector of the transistor 601 which signal is a combination of the -(R-Y) signal supplied through the emitter follower 607 and the -Y m signal amplified through the transistor 601. This combination is a -R signal in which a level corresponding to the level 521 is present during the period t 5 -t 6 and which is suppressed in the line periods t 1 -t 5 and t 6 -t 10a . This signal is applied to the base of an npn transistor 611 whose collector is connected to a positive voltage and whose emitter is connected through a resistor 613 to the collector of an npn transistor 615 whose emitter is connected to earth through a resistor 617 and whose base is connected to a reference voltage of 1.4 V.
The emitter of the transistor 615 is furthermore connected to the emitters of two npn transistors 619 and 621 whose collectors are connected to a positive supply voltage.
A level correction voltage originating from the capacitor 367 and applied to the input 355 is transferred to the base of the transistor 619 through an npn transistor 623 arranged as an emitter follower while a suppression signal having the waveform 537 applied to the input 349 is passed on to the base of the transistor 621. The latter signal ensures the common suppression of the beam current during the line and field flyback periods. Due to the fact that the otherwise cut-off transistor 621 is blocked during these flyback periods, the transistor 615 is cut off and no signal is passed to the collector of this transistor because then the emitter circuit of the transistor 611 is interrupted.
The level correction voltage applied to the input 355 is then applied through the emitters of the transistors 623 and 619 to the emitter of the transistor 615 and influences the direct current through the resistor 613 provided by the transistor 615 and hence of the direct current level of the -R signal passed through the emitter of the transistor 611 to the collector of the transistor 615.
The collector of the transistor 615 is connected to the base of an npn transistor 625 whose collector is connected to a positive voltage and whose emitter is connected through an adjustable resistor 629 to the base of an npn transistor 631. The emitter of the transistor 631 is connected to earth and the collector is connected to the emitter of an npn transistor 633 whose collector is connected through a resistor 635 to a positive supply voltage of +130 V and whose base is adjusted to a bias voltage of +5 V. The base of the transistor 631 receives a negative feedback voltage from the collector of the transistor 633 through a potential divider 637, 639 to a negative voltage.
A red colour signal amplified by the transistors 631 and 633 is obtained from the collector of the transistor 633 and is applied through the output 343 to the wehnelt electrode of the red gun of the display tube 221. This signal includes the correction level originating from the capacitor 363 with which the beam current in the red gun is adjusted to a desired value.
The amplification of the circuit arrangement is adjustable with the resistor 629 so as to perform for example, a white point correction. Due to the control loop such an adjustment has substantially no influence on the beam current which is produced by the reference level 521 so that the black level and hence the colour of dark picture parts does not change due to the adjustment.
The modified luminance signal Y m for the input 289 is obtained in the level insertion circuit 259.
A luminance signal is applied to the input 261 which signal is applied to an input 701 of an amplifier 703. Furthermore the amplifier 703 has an input 707 to which an adjustable direct voltage is applied with the aid of a potentiometer 709 which serves for luminance adjustment and an input 771 to which a suppression signal is applied as is shown by the waveform 555. The black level of the picture 520 in the waveform 563 is adjustable with the aid of the potentiometer 709 relative to the level occurring during the suppression periods. The waveform 563 is the luminance signal which occurs at the output 263 across an emitter resistor 713 of an npn transistor 715 arranged as an emitter follower whose base is connected to an output 705 of the amplifier 703.
A signal having the waveform 555 is applied to the input 257 of the level insertion circuit through a capacitor 717, which signal is passed at one end through a resistor 721 to the base of an npn transistor 723 and at the other end through a potential divider 725, 727 to the base of an npn transistor 729.
During the most positive parts of the waveform 555 a low voltage is produced across a collector resistor 731 of the transistor 723. The level of the signal during the periods t 5 -t 10 lies below the cut-off point of the transistor 727 so that this is not found back in the collector signal 565 of this transistor. As a result of the potential divider 725, 727 connected to the positive voltage the transistor 729 only reacts to the most negative parts of the signal 555 and the transistor 729 is cut off during the periods t 5 -t 6 , t 7 -t 8 and t 9 -t 10 so that then positive going square-wave voltages occur at the collector of this transistor.
The collector of the transistor 729 is connected through a resistor 733 to a potential divider including a resistor 735 and a series arrangement of a diode 736 and a resistor 737. The voltage at the wiper of this potential divider has a constant value of + 2.2 V which also occurs at the collector of the transistor 729 during the said periods. This voltage is passed on through a resistor 738 to the base of an npn transistor 739 whose collector is connected to a positive supply voltage and whose emitter is connected to the emitter of the transistor 715. During the periods t 5 -t 6 , t 7 -t 8 and t 9 -t 10 the emitter of the transistor 739 is brought to a voltage of +1.5 V due to its base voltage so that the transistor 715 is cut off and the reference level 521 is produced at the output 263. The rest of the period the transistor 739 is cut off and a signal is applied to the output 263 through the transistor 715.
In the waveform 563 arrows show that the black level 520 of the signal is adjustable relative to the constant reference level 521 which as a result of the said control corresponds to a constant beam current valve in the guns of the display tube 221.
The pulses for the various parts of the circuit arrangement are supplied by the pulse generator 235.
This generator has four trigger circuits 801, 803, 805 and 807. A signal which relative to the signal 533 at the input is delayed over a time T 1 is applied to a set input 809 of the trigger 801 from the input 233 through a delay circuit including a resistor 811 and a capacitor 813. This signal is shown in the waveform 509. Before this pulse appears the triggers 801, 803, 805 and 807 are assumed to be in the reset condition. At the instant t 1 + T 1 the trigger 801 is brought to the set condition. A signal represented by the waveform 514 then appears at an output 814 thereof which signal is applied to four AND gate circuits 817, 819, 821 and 823.
Furthermore an inverted set signal from the trigger 801 is applied to the gate 817 as well as a line frequency pulse signal originating from the input 229.
In addition a signal represented by the waveform 544 originating from an output 816 of the trigger 803 and a signal originating from an AND gate 817 are applied to the gate 819.
The gate 821 furthermore receives a signal having a waveform 518 from an output 818 of the trigger 805 and a signal originating from an AND gate 829.
Furthermore the gate 823 receives a signal having a waveform 520 from an output 820 of the trigger 807 and an inverted line frequency pulse signal originating from the input 229. An output of this gate 823 is connected through a delay circuit including a resistor 831 and a capacitor 833 to an AND gate 835 which also receives a line frequency pulse signal from the input 229. The output of this gate 835 is connected to the reset inputs of all four triggers. The gates 827 and 829 receive an inverted signal from the input 229 and an output signal from the triggers 805 and 807, respectively.
Furthermore a switchable feedback is present between the output 814 of the trigger 801 and the set input thereof, which feedback is only switched on when the beam current in the display tube 221 is too high. This feedback starts from the output 814 through a resistor 837 which is connected to the base of an npn transistor 839 whose emitter is connected to earth and whose collector is connected through a resistor 841 to the input 256 and is connected to the output of the trigger circuit 414, the base of a transistor 843 connected to the collector of the transistor 839 having its collector connected to a positive supply voltage and being connected through a resistor 845 connected to the emitter of this transistor 843 to the set input 809 of the trigger 801. Together with the capacitor 813 the resistor 845 constitutes a delay circuit having a time delay T 2 . The feedback is not present when the beam current is so low that the trigger circuit 414 is not set; the voltage at the collector of the transistor 839 is then low and the transistor 843 is cut off. This condition is assumed to be present at the commencement of the time axis in FIG. 5.
When the voltage at the input 256 becomes high due to the trigger 414 coming in the set condition the feedback will be switched on. The transistor 839 will then act as an inverter.
When at the instant t 1 + T 1 the trigger 801 is set, the trigger 803 is blocked at the same time by the inverted set signal from the trigger 801 applied to the gate 817. The triggers 803, 805 and 807 then remain in the reset condition. After the end of the set pulse from the trigger 801, i.e. after the instant t 3 = t 2 +T 1 the gate circuit 817 becomes conducting at the instant t 4 due to the next line frequency pulse and brings the trigger 803 in the set condition. The gate 819 then becomes conducting after the end of the line pulse under the influence of the gate 827 and applies a pulse through a delay network 845, 847 to an input of an AND gate 849 to which also the line frequency signals of the input 229 are applied. At the next line pulse at the instant t 6 the trigger 805 is set so that the gate 821 provides a pulse which is delayed by a network 851, 853 and is applied to an input of an AND gate 855 to which furthermore the line frequency pulse signal from the input 229 is applied. This gate 855 becomes conducting at the next line pulse at the instant t 8 under the influence of the gate 829 and brings the trigger 807 to the set condition.
A pulse is obtained from the output of the gate 823 which begins after termination of the line pulse and which is applied delayed through the network 831, 833 to the gate 835 which then passes the next line pulse at the instant t 10 so that the triggers 801, 803, 805 and 807 are reset.
When meanwhile the trigger circuit 414 has not reached the set condition during the time between t 5 and t 10 in which the beam currents in the display tube are measured, the triggers 801, 803, 805 and 807 remain in the reset condition until the next field pulse.
When the trigger circuit 414 changes to the set condition due to a too high beam current for example between t 5 and t 6 , the described feedback from the output 814 of the trigger 801 is provided at its set input 809 and a positive pulse will appear again at the instant t 10 + T 2 at the input 809 which pulse will bring the trigger 809 to the set condition again so that at an instant t 10 + 2T 2 the trigger 803 is set whereafter the triggers repeat the above-described conditions every time.
At the next field pulse at the instant t 11 , however, the trigger 414 is reset so that the feedback in the pulse generator 235 is interrupted and a set cycle of the triggers 801, 803, 805 and 807 already started is terminated at the instant t 12 when the gate 835 applies a line pulse to the reset input of the trigger 801 so that voltage at the output 814 remains equally low and all triggers are reset. After the line pulse drops out at its reset input the trigger 801 is brought immediately to the set condition so that at the next line pulse which lies after the instant which is T 1 later than the trailing edge of the field pulse 533 the trigger 803 is set again and three line times later everything is reset and remains reset when the beam current has become sufficiently low due to the repeated recharge of the capacitors 363, 365, 367 in the measuring circuit 362.
A number of gate circuits supplying the output signals from the pulse generator 235 are coupled to the outputs of the trigger circuits.
The output 239 is connected to an output of an AND gate 857 which has an input connected to the output 816 of the trigger 803, an inverted input which is connected to the output 818 of the trigger 805 and an inverted input which is connected to the input 229 of the pulse generator. The output of this gate then applies the waveform 539.
The output 241 is connected to an output of an AND gate 859 and input of which is connected to the output 818 of the trigger 805, an inverted input is connected to the output 820 of the trigger 807 and an inverted input is connected to the input 229 of the pulse generator 235. The AND gate 859 provides an output signal having the waveform 541.
The output 243 is connected to an output of an AND gate 861 an input of which is connected to the output 820 of the trigger 807 and an inverted input is connected to the input 229 of the pulse generator 235. The AND gate 861 provides an output signal having the waveform 543.
The output 244 is connected to the output 816 of the trigger 803 and the output 245 is connected to an inverted output of this trigger.
The output 247 is connected to an output of an OR gate 863, the output 249 is connected to an output of an OR gate 865 and the output 251 is connected to an output of an OR gate 867. The inputs of the gate 863 are connected to the outputs of the gates 861 and 859, the inputs of the gate 865 are connected to the outputs of the gates 861 and 857 and the inputs of the gate 867 are connected to the outputs of the gates 857 and 859. The gates 863, 865 and 867 supply the signals 547, 549 and 551, respectively.
The output 253 is connected to an output of an AND gate 869 an input of which is connected to the output 816 of the trigger 803 and an inverted input is connected to the input 219 of the pulse generator 235. The waveform 553 is supplied by this gate.
The output 237 is connected to an output of an OR gate 871 whose inputs are connected to the inputs 229 and 233 of the pulse generator. The waveform 537 is provided by the gate 871.
The output 255 is connected to an output of a gate and superimposition circuit 873 an input of which is connected to an inverted output of the trigger 801, an inverted input is connected to the output of the gate 871 and an inverted input is connected to the output of the gate 869. The gate and superimposition circuit 873 provides the waveform 555.
Since the latter waveform is applied through the capacitor 717 to the input 257 of the level insertion circuit 259, an unsatisfactory amplitude selection will take place when the trigger 801, 803, 805 and 807 run free for a long period so that a charge of the capacitors 363, 365, 367 in the measuring circuit 362 is effected independently of the beam current when it has exceeded a given maximum value as described in the foregoing. The level shift due to this capacitor 717 and the results thereof are not important for the understanding of the invention and are therefore not shown in the waveforms.
Although the control voltage in the described embodiments is applied to a wehnelt electrode of the display tube it may alternatively be applied to a different control electrode.
The insertion of the reference level may of course alternatively be effected in a different manner such as, for example, by clamping the video signal on the control signal.
For switching over the described functions in case of a too large beam current value a schmitt trigger or a monostable multivibrator may be used if desired instead of a bistable trigger circuit having a set and reset, input, or an output signal from the threshold circuit may be used.
The type of measuring circuit is not important for using the step according to the invention. Instead of a sequence measuring circuit it is alternatively possible to use a simultaneous measuring circuit in which all beam currents are simultaneously measured in the case of a multigun display tube. Also the input circuit of the measuring circuit may of course be adapted as desired.
If desired other counting circuits may be used instead of a shift register.
Television display apparatus of this type is known from U.S. Patent No. 3,562,409 in which the threshold circuit ensures that in case of a too large deviation of the beam current relative to the desired value the drive of the storage circuit is limited.
It is an object of the invention to provide improved television display apparatus of the kind described in the preamble which is characterized in that the threshold circuit is a circuit which in case of occurrence of a too large beam current applies a signal to an output thereof which output is coupled to an operation signal input of a circuit extending the charge corrections time of the storage circuit per field period.
Due to the limiting circuit in the circuit arrangement described in the abovementioned U.S. Patent Specification, in combination with the short measuring time available it could occur in the known circuit arrangement that, for example, after switching on the apparatus a very brightly lit picture occurred for several seconds. The storage circuit must include a capacitor having a fairly large capacitance the charge of which must be corrected in the known circuit with a current limited by the threshold circuit during the measuring time.
As a result of the step according to the invention the threshold circuit does not serve to limit the current intensity during the correction of the charge but to activate a circuit in case of a too large deviation of the nominal beam current, which circuit accelerates a feedback of the beam current to the nominal value by realising an extended charge correction time for the storage circuit. Consequently a feedback of the beam current to a level which is not troublesome can be obtained in a very quick manner without the current intensity in circuit elements correcting the charge of the storage circuit becoming too large.
The extended charge correction time of the storage circuit can be obtained by applying a correction charge from a current source which is independent of the measuring value under the influence of the threshold circuit during a time which is considerably longer than the measuring time, or by increasing the measuring frequency so that a current source which is dependent on the measuring value can recharge the storage circuit more frequently per unit of time.
The invention will now be described with reference to the drawing and some embodiments.
In the drawing:
FIG. 1 illustrates by way of a block-schematic diagram a television display apparatus according to the invention.
FIG. 2 illustrates by way of a block-schematic diagram a further elaboration of a television display apparatus according to the invention,
FIG. 3 likewise illustrates by way of a block-schematic diagram a further embodiment of a television display apparatus according to the invention,
FIG. 4 illustrates partly by way of a block-schematic diagram and partly by way of a principle circuit diagram a colour television display apparatus according to the invention including a sequential measuring circuit and
FIG. 5 shows a number of wave forms as may occur in the circuit of FIG. 4.
In FIG. 1 a video signal is applied to an input 1 of a level insertion circuit 3 which signal is provided with a reference level every time during some line times of a field some time after a field flyback with the aid of a signal obtained from an output 7 of a pulse generator 9 and applied to a further input 5. The video signal with the reference level is passed from an output 11 of the level insertion circuit 3 to an input 13 of a beam current level correction circuit 15. A level correction quantity obtained from an output 19 of a measuring circuit 21 is applied to a further input 17 of the beam current level correction circuit 15. A video signal having a reference level and an added level correction quantity is obtained from an output 23 and is applied to an input 25 of an amplifier 27 an output 29 of which is connected to the wehnelt electrode of a television display tube 31. A cathode of the television display tube 31 is connected to an input 33 of the measuring circuit 21.The measuring circuit 21 includes a gating circuit 35 connected to the input 33 which applies a quantity dependent on the beam current to an output 37 during the occurrence of the reference level. The gating circuit 35 is arranged with the aid of a gating signal applied to a gating signal input 39 and originating from an output 41 of the pulse generator 9.
The quantity dependent on the beam current produced during the occurrence of the reference level is applied from the output 37 of the gating circuit 35 to an input 43 of a detection circuit 45 and to an input 47 of a threshold circuit 49.An output 51 of the detection circuit 45 is connected in the normal operating condition to a storage capacitor 53 which constitutes a storage circuit with the circuit arrangement connected thereto and which has a time constant which is long relative to the field period. The beam current level correction quantity occurring at the output 19 of the measuring circuit 21 is then obtained from the storage capacitor 53 which quantity readjusts the beam current to a constant value.
The threshold circuit 49 has an output 55 which is connected to an operation signal input 57 of a circuit 59 extending the charge correction time of the storage circuit. The circuit 59 extending the charge correction time includes a second storage capacitor 60 which can retain a voltage optionally provided by the threshold circuit for some time and a changeover switch 61 an operation signal input 63 of which is connected to the operation signal input 57 of the circuit 59 extending the recharge time. The changeover switch 61 has an input 67 which is connected to the output 51 of the detection circuit 45 and an input 69 which is connected through a resistor 71 to a positive supply voltage. An output 73 of the change-over switch is connected to the storage capacitor 53 and the output 19 of the measuring circuit 21.
In the normal operating condition the change-over switch 61 occupies the position shown and the above-described beam current control occurs.
When the beam current is very large during the measuring time, which means that the voltage at the storage capacitor 53 is very low, threshold circuit 49 applies a voltage to its output 55 which sets the change-over switch 61 to the position not shown and, dependent on the discharge time of the second storage capacitor 60, retains it in that position for some time, for example, several hundred line times. The resistor 71 then constitutes a current source independent of the measuring value which increases the voltage across the storage capacitor 53. During the next measurement the threshold circuit 49 determines whether this increase has been sufficient or not so that the change-over switch 61 can remain in the position shown or must be reset once more for some time.
The pulse generator 9 has an input 75 to which field frequency pulses derived from field synchronising or field flyback pulses are applied and an input 77 to which pulses derived from line synchronizing or line flyback pulses are applied. The input 75 is connected to an input 79 of a shift register 81 which in this case has four sections but of which the number of sections can of course be chosen arbitrarily. A line frequency pulse originating from the input 77 serves as a clock pulse for the shift register 81 into which, for example, at the end of the field flyback time a one is shifted which is shifted one section further at every subsequently occurring clock pulse. The last two sections of the shift register have outputs 83 and 85 which are connected to inputs 87 and 89, respectively, of a gating circuit 91 which has a further input 93 connected to the input 77. The gating circuit 91 supplies signals to two outputs 95 and 97 which signals are applied to the outputs 7 and 41 of the pulse generator 9 and which have the functions described hereinbefore.
In FIG. 2 corresponding components have the same reference numerals as those in FIG. 1. For the description of this Figure reference is made to FIG. 1.The circuit arrangement of FIG. 2 differs from that of FIG. 1 in that the second storage capacitor 60 of the circuit 59 extending the recharge time of the first storage capacitor 53 is replaced by a trigger circuit 99 a set input of which is the input 57 which is connected to the output 55 of the threshold circuit and a reset input 101 of which is connected to the input 75 of the pulse generator 9 to which the field frequency pulses are applied. An output 103 of the trigger circuit is connected to the input 63 of the change-over switch 61 and to an operation signal input 105 of a second change-over switch 107 in the pulse generator 9. An input 109 of the second change-over switch 107 is connected to an output 111 of the shift register 81 and an input 113 is connected to the input 75 for field frequency pulses from the pulse generator 9. An output 115 of the change-over switch 107 is connected to the input 79 of the shift register 81.
In the position shown of the change-over switches 61, 107 the operation of the circuit arrangement is the same as in the case of FIG. 1. When a too high beam current is detected by the threshold circuit 49, the trigger circuit 99 will be set and the change-over switches 61 and 107 will be brought to the position not shown. The storage capacitor 53 will then be charged through the resistor 71 likewise as in the case of FIG. 1. The change-over switch 107 connects the output 111 of the shift register 81 to its input 79 so that always a one circulates in the shift register 81 and a continuous measurement of the beam current is effected until the threshold circuit 49 no longer detects a too high beam current and due to the output voltage dropping out or due to the next field frequency pulse at the reset input 101 the trigger circuit 99 is reset and the normal state is restored.
In FIG. 3 corresponding components have the same reference numerals as those in FIGS. 1 and 2 and reference is made to the description associated with the relevent Figures.
The circuit arrangement differs from that of FIG. 2 by the absence of the first change-over switch 61. Consequently, when a too high beam current occurs the normal control loop is maintained and only due to the second change-over switch 107 the shift register 81 is enabled so that a strongly increased measuring frequency and an accelerated feedback occurs through the normal control loop to the normal state. The recharge time of the storage capacitor 53 is in this case extended because per field period a larger number of measurements and associated recharges of this capacitor is effected.FIG. 4 shows a colour television receiver including a circuit arrangement according to the invention in which the principle as described with reference to FIG. 2 is used. The circuit arrangement has a colour television display apparatus having a sequential beam current measuring circuit whose principle is described in prior application Ser. No. 402,159, filed Oct. 1, 1973, now abandoned.
When a colour television signal is applied to an input 201 of a high frequency-intermediate frequency and detection section 203, a luminance signal Y is produced at an output 205, a chrominance signal Chr is produced at an output 207 and a synchronizing signal S is produced at an output 209.
The synchronizing signal S is applied to an input 211 of a time base generator 213 connected to the output 209. Deflection currents for a television display tube 221 are obtained at two outputs 215 and 217 and an EHT for the supply of the display tube 221 is obtained at an output 223.
An output 227 of the time base generator 213 applies line flyback pulses to an input 229 and an output 231 applies field flyback pulses to an input 233 of a pulse generator 235. These pulses are shown in FIG. 5 by the waveforms 529 and 533, respectively.
Furthermore FIG. 5 shows a number of waveforms 537, 509, 514, 544, 548, 520, 539, 541, 543, 547, 549, 551, 553, 656, 555, 565 and 563 and a number of instants t 1 , t 1 +T 1 , t 3 to t 10 , t 10a , and t 10 + T 2 , t 10 + 2T 2 , T 11 , t 11 + T 1 , t 11 + 2 T 1 , and t 12 which are important for explaining the operation of the circuit arrangement. The waveforms are not shown to scale.The pulse generator 235 has a number of outputs 237, 239, 241, 243, 244, 245, 247, 249, 251, 253, 255 and an input 256 at which the waveforms 537, 539, 541, 543, 545, 547, 549, 551, 553, 555 and 556, respectively, are present.
The output 255 of the pulse generator 235 is connected to an input 257 of a level insertion circuit 259 an input 261 of which is connected to the output 205 of the section 201 and receives the luminance signal Y therefrom. The level insertion circuit 259 has an output 263 at which the modified luminance signal denoted by the waveform 563 of FIG. 5 is produced which includes a reference level 521 during three line times t 5 -t 6 , t 7 -t 8 , t 9 -t 10 at the commencement of the field, which level is inserted with the aid of the wave-form 555 applied to the input 257.
The waveform 565 is then produced at a further output 265 of the level insertion circuit 259, which waveform is applied to an input 267 of a chrominance signal amplifier 269 for suppressing the chrominance signal applied to an input 271 connected to the output 207 of the section 201.The output 263 of the level insertion circuit 259 is connected to inputs 285, 287 and 289 of suppression and level correction circuits 291, 293 and 295, respectively, inputs 297, 299 and 301 of which are connected to outputs 247, 249 and 251 of the pulse generator 235 and inputs 303, 305 and 307 of which are connected to outputs 309, 311 and 313, respectively, of a demodulator and matrix circuit 315 to whose input 317 a chrominance signal originating from an output 319 of the chrominance signal amplifier 219 is applied.
The demodulator and matrix circuit applies a (B-Y), (G-Y) and (R-Y) colour difference signal to its outputs 309, 311 and 313, respectively. These colour difference signals are combined in the suppression and level correction circuits 291, 293 and 295 with the modified luminance signal applied to the inputs 285, 287 and 289 to form colour signals R, G and B, while as a result of the signals with the waveforms 547, 549, 551 at the inputs 297, 299 and 301 the reference level 521 originating from the luminance signal is suppressed in a special sequence. In this example a sequence is maintained in which only a reference level is left in the R-signal from t 5 to t 6 , in the G signal from t 7 to t 8 and in the B signal from t 9 to t 10 .
The suppression and level correction circuits 291, 293 and 295 furthermore have outputs 339, 341, 343 connected to the wehnelt electrode of the red, blue and green guns of the display tube 221 and inputs 345, 347 and 349 connected to the output 237 of the pulse generator 235 for receiving a suppression signal of the waveform 537 which prevent a signal supply to the display tube 221 during the time base flyback times. Inputs 351, 353 and 355 are furthermore connected to outputs 357, 359 and 361, respectively, of a measuring circuit 362 which outputs are connected to storage capacitors 363, 365 and 367, respectively, whose other ends are connected to earth. The storage capacitors 363, 365 and 367 are connected to switches 377, 378 and 379 respectively, operation signal inputs 383, 384 and 385 of which are connected to outputs 239, 241 and 243, respectively, of the pulse generator 235.
The switch 377 conducts from t 5 to t 6 , the switch 378 conducts from t 7 to t 8 and the switch 379 conducts from t 9 to t 10 . Each of these switches introduces a level applied to an input 381 thereof into the relevant storage capacitors 363, 365, 367.
The cathodes of the television display tube 221 are interconnected and are connected to an input 389 of the measuring circuit 362. Sequentially by each cathode voltages is generated across a resistor 393 connected to the input 389 which resistor is shunted by a diode 394 and is connected at its other end to a voltage of + 130 Volt during the said periods. This generated voltage produces a corresponding voltage across the storage capacitors 363, 365 and 367 which is retained during the next field flyback time and is passed on for beam current control to the inputs 351, 353 and 355 of the suppression and level correction circuits 291, 293 and 295. The two cathodes which are not measured then do not convey any beam current.
The screen grids of the guns of the television display tube 221 are each connected to an adjusting point of potentiometers 395, 396 and 397 between + 130 Volt and a higher voltage ++.
A signal occurring at the cathodes of the television display tube 221 produces a voltage across the resistor 393 which voltage is limited by the diode 394 blocked during the measuring periods. This voltage is applied to the base of a pnp transistor 401 whose emitter is connected to the other end of the resistor 393. The collector of the transistor 401 is connected to earth through a resistor 403, connected to earth through a capacitor 405 for high frequencies and has a negative feedback to the base through a resistor 407.
A signal amplified by the transistor 401 is applied through a series arrangement of a capacitor 409, a resistor 410 and a resistor 411 to the base of an npn transistor 413. The collector of an npn transistor 415 serving as a clamping switch is connected between the resistors 410 and 411. The emitter is connected to a clamping voltage V kl and the base is connected to the input 391 of the measuring circuit 362.
As a result of the waveform applied to the input 391, which waveform is the inverse form of waveform 544, the transistor 415 is cut off during the occurrence of the signal produced by the reference level 521. During the preceding line periods the capacitor 511 has reached a constant charge condition (clamped) through the then conducting transistor 415 because both the luminance signal and the chrominance signal are suppressed and the cathodes of the display tube 221 do not convey any current.
During the period t 4 -t 10 signals caused by the reference level 521 occur successively during the periods t 5 -t 6 , t 7 - t 8 and t 9 - t 10 at the successive cathodes of the display tube 221 which signals are applied in an amplified manner to the base of the transistor 413 and which furthermore appear at the emitter of an npn transistor 412 connected to the base of the transistor 413.
When the signals have an amplitude which is not too large they are passed on by the transmitter 413 through its emitter and a resistor 423 to the base of an npn transistor 425.
When the signals at the base of the transistor 413 have a too large amplitude the emitter of the transistor 412 will become more negative than its base connected to a threshold voltage V dr and this transistor 412 will start conducting and hence operate a set input of a trigger circuit 414 connected to its collector which then provides a positive voltage for its output 416. This positive voltage (waveform 556) is applied to an output 418 which is connected to the input 256 of the pulse generator 235 and which causes a variation to a free-running state which will be described hereinafter, while this voltage also controls the base of an npn transistor 422 through a resistor 420 and the emitter of this transistor is connected to earth while the collector is connected to the base of the transistor 413. The base of this transistor 413 then is no longer controlled because the transistor 422 acts as a short circuit for its input signal. The trigger circuit 414 furthermore has a reset input 424 to which a field flyback pulse (waveform 533) originating from the output 231 of the time base generator 213 is applied so that the trigger circuit 414 is reset every time at the commencement of the field flyback.
In the state in which the beam current is not too large the transistors 412 and 422 do not conduct and the signal is passed on through the transistor 413 to the base of the transistor 425 whose emitter is connected to the collector of an npn transistor 427 whose emitter is connected to earth and whose base is connected through a resistor 428 to the input 392 of the measuring circuit. The collector of the transistor 425 is connected through a resistor 430 to the base of an npn transistor 433 whose emitter is connected through a resistor 435 to the input 381 of the sequence switches 377, 378 and 379.
The collector of the transistor 425 is connected through a resistor 432 to the emitter of an npn transistor 434 arranged as an emitter follower whose base is connected through a resistor 436 to an input 438 of the measuring circuit 362 which is connected to the output 244 of the pulse generator 235 at which the waveform 544 occurs. This transistor 434 conducts during the measuring period and furthermore every time during a number of line times in the field scan time when the pulse generator 235 has acquired a free-running state (waveform 544) due to a too high beam current with the aid of the trigger circuit 414.
The transistor 427 conducts due to the waveform 553 during the measuring periods so that in the periods t 5 -t 6 , t 7 -t 8 , t 9 -t 10 the emitter of the transistor 425 is connected to earth through the transistor 427 and the transistor 425 acts as an amplifier and passes on a signal to the base of the transistor 433 and recharges through its emitter the storage capacitors 363, 365 and 367 during the corresponding periods t 5 -t 6 , t 7 -t 8 and t 9 -t 10 , respectively.
In the state of the circuit arrangement where a too large beam current has been detected and where the trigger circuit 414 is set, the transistor 425 does not conduct due to the short circuit of the base of the transistor 413 so that then the storage capacitors 363, 365 and 367 are recharged by the emitter follower 434, 433 every time during the periods when the waveform 544 is positive. This is effected a large number of times during field scan periods following the set of the trigger circuit 414 so that the storage capacitors are charged quickly to a higher voltage to reduce the beam current through the control loops as quickly as possible again.
The operation of a control loop will now be described. This control loop not only includes the television dislay tube 221 and the measuring circuit 362 but also the suppression and level correction circuit 295.
Furthermore the emitter of the transistor 601 is connected to the emitter of an npn transistor 609 whose collector is connected to a positive voltage and whose base is connected to the input 301.
A voltage having the waveform 547 is applied to the input 301 so that the transistor 609 conducts during the periods t 7 -t 8 and t 9 -t 10 and thus cuts off the transistor 601 so that also the transistor 607 does not convey current and the signal at the collector of the transistor 601 is suppressed.
When the transistor 609 does not conduct a signal is generated at the collector of the transistor 601 which signal is a combination of the -(R-Y) signal supplied through the emitter follower 607 and the -Y m signal amplified through the transistor 601. This combination is a -R signal in which a level corresponding to the level 521 is present during the period t 5 -t 6 and which is suppressed in the line periods t 1 -t 5 and t 6 -t 10a . This signal is applied to the base of an npn transistor 611 whose collector is connected to a positive voltage and whose emitter is connected through a resistor 613 to the collector of an npn transistor 615 whose emitter is connected to earth through a resistor 617 and whose base is connected to a reference voltage of 1.4 V.
The emitter of the transistor 615 is furthermore connected to the emitters of two npn transistors 619 and 621 whose collectors are connected to a positive supply voltage.
A level correction voltage originating from the capacitor 367 and applied to the input 355 is transferred to the base of the transistor 619 through an npn transistor 623 arranged as an emitter follower while a suppression signal having the waveform 537 applied to the input 349 is passed on to the base of the transistor 621. The latter signal ensures the common suppression of the beam current during the line and field flyback periods. Due to the fact that the otherwise cut-off transistor 621 is blocked during these flyback periods, the transistor 615 is cut off and no signal is passed to the collector of this transistor because then the emitter circuit of the transistor 611 is interrupted.
The level correction voltage applied to the input 355 is then applied through the emitters of the transistors 623 and 619 to the emitter of the transistor 615 and influences the direct current through the resistor 613 provided by the transistor 615 and hence of the direct current level of the -R signal passed through the emitter of the transistor 611 to the collector of the transistor 615.
The collector of the transistor 615 is connected to the base of an npn transistor 625 whose collector is connected to a positive voltage and whose emitter is connected through an adjustable resistor 629 to the base of an npn transistor 631. The emitter of the transistor 631 is connected to earth and the collector is connected to the emitter of an npn transistor 633 whose collector is connected through a resistor 635 to a positive supply voltage of +130 V and whose base is adjusted to a bias voltage of +5 V. The base of the transistor 631 receives a negative feedback voltage from the collector of the transistor 633 through a potential divider 637, 639 to a negative voltage.
A red colour signal amplified by the transistors 631 and 633 is obtained from the collector of the transistor 633 and is applied through the output 343 to the wehnelt electrode of the red gun of the display tube 221. This signal includes the correction level originating from the capacitor 363 with which the beam current in the red gun is adjusted to a desired value.
The amplification of the circuit arrangement is adjustable with the resistor 629 so as to perform for example, a white point correction. Due to the control loop such an adjustment has substantially no influence on the beam current which is produced by the reference level 521 so that the black level and hence the colour of dark picture parts does not change due to the adjustment.
The modified luminance signal Y m for the input 289 is obtained in the level insertion circuit 259.
A luminance signal is applied to the input 261 which signal is applied to an input 701 of an amplifier 703. Furthermore the amplifier 703 has an input 707 to which an adjustable direct voltage is applied with the aid of a potentiometer 709 which serves for luminance adjustment and an input 771 to which a suppression signal is applied as is shown by the waveform 555. The black level of the picture 520 in the waveform 563 is adjustable with the aid of the potentiometer 709 relative to the level occurring during the suppression periods. The waveform 563 is the luminance signal which occurs at the output 263 across an emitter resistor 713 of an npn transistor 715 arranged as an emitter follower whose base is connected to an output 705 of the amplifier 703.
During the most positive parts of the waveform 555 a low voltage is produced across a collector resistor 731 of the transistor 723. The level of the signal during the periods t 5 -t 10 lies below the cut-off point of the transistor 727 so that this is not found back in the collector signal 565 of this transistor. As a result of the potential divider 725, 727 connected to the positive voltage the transistor 729 only reacts to the most negative parts of the signal 555 and the transistor 729 is cut off during the periods t 5 -t 6 , t 7 -t 8 and t 9 -t 10 so that then positive going square-wave voltages occur at the collector of this transistor.
The collector of the transistor 729 is connected through a resistor 733 to a potential divider including a resistor 735 and a series arrangement of a diode 736 and a resistor 737. The voltage at the wiper of this potential divider has a constant value of + 2.2 V which also occurs at the collector of the transistor 729 during the said periods. This voltage is passed on through a resistor 738 to the base of an npn transistor 739 whose collector is connected to a positive supply voltage and whose emitter is connected to the emitter of the transistor 715. During the periods t 5 -t 6 , t 7 -t 8 and t 9 -t 10 the emitter of the transistor 739 is brought to a voltage of +1.5 V due to its base voltage so that the transistor 715 is cut off and the reference level 521 is produced at the output 263. The rest of the period the transistor 739 is cut off and a signal is applied to the output 263 through the transistor 715.
In the waveform 563 arrows show that the black level 520 of the signal is adjustable relative to the constant reference level 521 which as a result of the said control corresponds to a constant beam current valve in the guns of the display tube 221.
The pulses for the various parts of the circuit arrangement are supplied by the pulse generator 235.
This generator has four trigger circuits 801, 803, 805 and 807. A signal which relative to the signal 533 at the input is delayed over a time T 1 is applied to a set input 809 of the trigger 801 from the input 233 through a delay circuit including a resistor 811 and a capacitor 813. This signal is shown in the waveform 509. Before this pulse appears the triggers 801, 803, 805 and 807 are assumed to be in the reset condition. At the instant t 1 + T 1 the trigger 801 is brought to the set condition. A signal represented by the waveform 514 then appears at an output 814 thereof which signal is applied to four AND gate circuits 817, 819, 821 and 823.
Furthermore an inverted set signal from the trigger 801 is applied to the gate 817 as well as a line frequency pulse signal originating from the input 229.
In addition a signal represented by the waveform 544 originating from an output 816 of the trigger 803 and a signal originating from an AND gate 817 are applied to the gate 819.
The gate 821 furthermore receives a signal having a waveform 518 from an output 818 of the trigger 805 and a signal originating from an AND gate 829.
Furthermore the gate 823 receives a signal having a waveform 520 from an output 820 of the trigger 807 and an inverted line frequency pulse signal originating from the input 229. An output of this gate 823 is connected through a delay circuit including a resistor 831 and a capacitor 833 to an AND gate 835 which also receives a line frequency pulse signal from the input 229. The output of this gate 835 is connected to the reset inputs of all four triggers. The gates 827 and 829 receive an inverted signal from the input 229 and an output signal from the triggers 805 and 807, respectively.
Furthermore a switchable feedback is present between the output 814 of the trigger 801 and the set input thereof, which feedback is only switched on when the beam current in the display tube 221 is too high. This feedback starts from the output 814 through a resistor 837 which is connected to the base of an npn transistor 839 whose emitter is connected to earth and whose collector is connected through a resistor 841 to the input 256 and is connected to the output of the trigger circuit 414, the base of a transistor 843 connected to the collector of the transistor 839 having its collector connected to a positive supply voltage and being connected through a resistor 845 connected to the emitter of this transistor 843 to the set input 809 of the trigger 801. Together with the capacitor 813 the resistor 845 constitutes a delay circuit having a time delay T 2 . The feedback is not present when the beam current is so low that the trigger circuit 414 is not set; the voltage at the collector of the transistor 839 is then low and the transistor 843 is cut off. This condition is assumed to be present at the commencement of the time axis in FIG. 5.
When the voltage at the input 256 becomes high due to the trigger 414 coming in the set condition the feedback will be switched on. The transistor 839 will then act as an inverter.
When at the instant t 1 + T 1 the trigger 801 is set, the trigger 803 is blocked at the same time by the inverted set signal from the trigger 801 applied to the gate 817. The triggers 803, 805 and 807 then remain in the reset condition. After the end of the set pulse from the trigger 801, i.e. after the instant t 3 = t 2 +T 1 the gate circuit 817 becomes conducting at the instant t 4 due to the next line frequency pulse and brings the trigger 803 in the set condition. The gate 819 then becomes conducting after the end of the line pulse under the influence of the gate 827 and applies a pulse through a delay network 845, 847 to an input of an AND gate 849 to which also the line frequency signals of the input 229 are applied. At the next line pulse at the instant t 6 the trigger 805 is set so that the gate 821 provides a pulse which is delayed by a network 851, 853 and is applied to an input of an AND gate 855 to which furthermore the line frequency pulse signal from the input 229 is applied. This gate 855 becomes conducting at the next line pulse at the instant t 8 under the influence of the gate 829 and brings the trigger 807 to the set condition.
A pulse is obtained from the output of the gate 823 which begins after termination of the line pulse and which is applied delayed through the network 831, 833 to the gate 835 which then passes the next line pulse at the instant t 10 so that the triggers 801, 803, 805 and 807 are reset.
When meanwhile the trigger circuit 414 has not reached the set condition during the time between t 5 and t 10 in which the beam currents in the display tube are measured, the triggers 801, 803, 805 and 807 remain in the reset condition until the next field pulse.
When the trigger circuit 414 changes to the set condition due to a too high beam current for example between t 5 and t 6 , the described feedback from the output 814 of the trigger 801 is provided at its set input 809 and a positive pulse will appear again at the instant t 10 + T 2 at the input 809 which pulse will bring the trigger 809 to the set condition again so that at an instant t 10 + 2T 2 the trigger 803 is set whereafter the triggers repeat the above-described conditions every time.
At the next field pulse at the instant t 11 , however, the trigger 414 is reset so that the feedback in the pulse generator 235 is interrupted and a set cycle of the triggers 801, 803, 805 and 807 already started is terminated at the instant t 12 when the gate 835 applies a line pulse to the reset input of the trigger 801 so that voltage at the output 814 remains equally low and all triggers are reset. After the line pulse drops out at its reset input the trigger 801 is brought immediately to the set condition so that at the next line pulse which lies after the instant which is T 1 later than the trailing edge of the field pulse 533 the trigger 803 is set again and three line times later everything is reset and remains reset when the beam current has become sufficiently low due to the repeated recharge of the capacitors 363, 365, 367 in the measuring circuit 362.
A number of gate circuits supplying the output signals from the pulse generator 235 are coupled to the outputs of the trigger circuits.
The output 239 is connected to an output of an AND gate 857 which has an input connected to the output 816 of the trigger 803, an inverted input which is connected to the output 818 of the trigger 805 and an inverted input which is connected to the input 229 of the pulse generator. The output of this gate then applies the waveform 539.
The output 241 is connected to an output of an AND gate 859 and input of which is connected to the output 818 of the trigger 805, an inverted input is connected to the output 820 of the trigger 807 and an inverted input is connected to the input 229 of the pulse generator 235. The AND gate 859 provides an output signal having the waveform 541.
The output 243 is connected to an output of an AND gate 861 an input of which is connected to the output 820 of the trigger 807 and an inverted input is connected to the input 229 of the pulse generator 235. The AND gate 861 provides an output signal having the waveform 543.
The output 244 is connected to the output 816 of the trigger 803 and the output 245 is connected to an inverted output of this trigger.
The output 247 is connected to an output of an OR gate 863, the output 249 is connected to an output of an OR gate 865 and the output 251 is connected to an output of an OR gate 867. The inputs of the gate 863 are connected to the outputs of the gates 861 and 859, the inputs of the gate 865 are connected to the outputs of the gates 861 and 857 and the inputs of the gate 867 are connected to the outputs of the gates 857 and 859. The gates 863, 865 and 867 supply the signals 547, 549 and 551, respectively.
The output 253 is connected to an output of an AND gate 869 an input of which is connected to the output 816 of the trigger 803 and an inverted input is connected to the input 219 of the pulse generator 235. The waveform 553 is supplied by this gate.
The output 237 is connected to an output of an OR gate 871 whose inputs are connected to the inputs 229 and 233 of the pulse generator. The waveform 537 is provided by the gate 871.
The output 255 is connected to an output of a gate and superimposition circuit 873 an input of which is connected to an inverted output of the trigger 801, an inverted input is connected to the output of the gate 871 and an inverted input is connected to the output of the gate 869. The gate and superimposition circuit 873 provides the waveform 555.
Since the latter waveform is applied through the capacitor 717 to the input 257 of the level insertion circuit 259, an unsatisfactory amplitude selection will take place when the trigger 801, 803, 805 and 807 run free for a long period so that a charge of the capacitors 363, 365, 367 in the measuring circuit 362 is effected independently of the beam current when it has exceeded a given maximum value as described in the foregoing. The level shift due to this capacitor 717 and the results thereof are not important for the understanding of the invention and are therefore not shown in the waveforms.
Although the control voltage in the described embodiments is applied to a wehnelt electrode of the display tube it may alternatively be applied to a different control electrode.
The insertion of the reference level may of course alternatively be effected in a different manner such as, for example, by clamping the video signal on the control signal.
For switching over the described functions in case of a too large beam current value a schmitt trigger or a monostable multivibrator may be used if desired instead of a bistable trigger circuit having a set and reset, input, or an output signal from the threshold circuit may be used.
The type of measuring circuit is not important for using the step according to the invention. Instead of a sequence measuring circuit it is alternatively possible to use a simultaneous measuring circuit in which all beam currents are simultaneously measured in the case of a multigun display tube. Also the input circuit of the measuring circuit may of course be adapted as desired.
If desired other counting circuits may be used instead of a shift register.
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I On-screen channel display:An on-screen television display including means internally of the receiver for generating characters to indicate the channel number, time of day or other data. The system includes circuit means responsive to the horizontal and vertical sync signals of a television receiver for positioning and timing of the display. BCD data is coupled to a character generator, and the output of the character generator is then multiplexed with positioning and timing signals. The multiplexed output is coupled to a video interface which supplies the video signal to the cathode ray tube.
1. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding m
eans having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit. 2. A display system in accordance with claim 1 wherein said decoding means comprises a seven segment decoder.
3. A display system in accordance with claim 2 wherein a line counter is provided to count horizontal scans of the cathode ray beam and wherein the output of said counter is coupled to said multiplexer to control the same.
4. A display system in accordance with claim 1 wherein said decoder is a seven segment decoder and wherein means are provided to gate the data output of said decoder which represent the vertical segments of the character to be displayed during given horizontal scans of the beam of the cathode ray tube.
5. A system ,in accordance with claim 1 including timing circuit means, means for multiplexing coded data representing each of said characters in accordance with timing signals from said timing circuit means, a seven segment decoder for decoding said multiplexed data, and means for using said decoded data to apply a video signal to the cathode ray tube of the television receiver.
6. A display system in accordance with claim 5 wherein there is provided an oscillator, means for keying the operation of the oscillator to the horizontal sync of the television receiver, and a counter for counting an output of said oscillator and for producing said timing signals.
7. A channel number display system in accordance with claim 6 wherein said data multiplexer has units digits gates and tens digits gates, said timing signal multiplexing data between said units and tens digits gates into at least four output lines, and means for coupling said multiplexed data to inputs of said seven segment decoder.
8. A channel number display system in accordance with claim 7 wherein means are provided to blank the display system output for a time interval between the switching of said data multiplexer from the units digits gates to the tens digits gates to provide spacing between the units and tens characters on the
raster of the cathode ray tube. 9. A channel number display system in accordance with claim 8 wherein select means are provided to select one of a greater number of variable character displays, said means including a BCD signal responsive select circuit.
10. A channel number display system in accordance with claim 9 wherein said select means includes a four-six character select circuit for selecting either four or six character display.
11. A system for displaying a character on the raster of a television receiver comprising: means for developing coded data indicative of the character to be displayed, a seven segment decoder, means for coupling the coded data to the input of the seven segment decoder, means for using the output of the seven segment decoder to illuminate a seven segment display on the raster of a cathode ray tube, and wherein three outputs of the seven segment decoder represent the horizontal segments of the character to be displayed and the remaining four outputs represent the vertical segments thereof, and wherein there is provided a multiplexer, a horizontal scan counter, means for coupling the counter outputs to the multiplexer, means for coupling the three horizontal segment outputs to the multiplexer, a timing counter, means for using the timing counter to gate the four vertical segment outputs during each scan associated with the character display, and means for coupling the four gated vertical segment outputs to the multiplexer.
12. A display system in accordance with claim 11 wherein there is provided an oscillator, means for keying the oscillator to the horizontal scan of the cathode ray beam, said oscillator having a frequency substantially higher than the horizontal line frequency of the cathode ray tube, means for coupling the output of the oscillator to the timing counter to control the same.
13. A display system in accordance with claim 12 wherein means are provided to use the horizontal sync signal of the television receiver to enable said timing counter.
14. Apparatus for use with a television receiver, said receiver comprising a horizontal scanning circuit, a vertical scanning circuit, a video signal circuit, and a display device coupled to said scanning and video signal circuits, and creating a character on said display device in the form of line segments oriented in generally horizontal and vertical directions and superimposed over other information displayed thereon and comprising:
data means for developing coded data indicative of the character to be displayed;
decoding means having a plurality of outputs and producing at each of said outputs a signal representative of the presence of a corresponding line segment in the character to be displayed;
an oscillator coupled to said horizontal scanning circuit and synchronized to the operation of said horizontal scanning circuit and producing a signal at a frequency greater than the horizontal scanning frequency;
counting means coupled to the output of said oscillator and developing signals representative of the position of the horizontal scan;
gating means coupled to said decoding means and said counting means and gating said signals representative of the presence of a corresponding generally vertical line segment in response to the position of the horizontal scan;
matrix means for matrixing said gated signals representative of the presence of corresponding generally vertical line segments and said signals representative of corresponding generally horizontal line segments to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a horizontal scan;
signal selection means for selecting one of said line signals in accord with the position of the vertical scan; and
combining means coupled to said video signal circuit for combining said selected line signal with a signal representative of said other information displayed on said display device.
15. The apparatus of claim 14 wherein said character is displayed in the form of the presence or absence of seven line segments and said decoding means comprises a seven segment decoder having seven outputs and producing at each of said outputs a signal representative of the presence of a corresponding one of said seven line segments in the character to be displayed.
16. The apparatus of claim 14 creating at least two characters on said display device wherein said data means develops coded data indicative of the characters to be displayed and said apparatus further comprises multiplex means coupled to said data means, said decoding means and said counting circuitry for applying to said decoding means coded data indicative of different characters to be displayed in response to the position of the horizontal scan.
17. The apparatus of claim 16 further comprising means for preventing the display of said characters for a time interval including the switching of said multiplex means to provide spacing between said characters.
18. The apparatus of claim 14 further comprising a time delay circuit coupled between said oscillator and said horizontal scanning circuit and preventing the operation of said oscillator until a predetermined time period has elapsed following the commencement of a horizontal scan.
19. Apparatus for use with a television receiver, said receiver comprising a first scanning circuit for scanning in a first direction, a second scanning circuit for scanning in a second direction generally perpendicular to said first direction, a video signal circuit, and a display device coupled to said scanning and video signal circuits, and creating a character on said display device in the form of line segments oriented in generally said first and second directions and superimposed over other information displayed thereon and comprising:
data means for developing coded data indicative of the character to be displayed;
decoding means having a plurality of outputs and producing at each of said outputs a signal representative of the presence of a corresponding line segment in the character to be displayed;
timing and gating means coupled to said decoding means and said first scanning circuit and gating said signals representative of the presence of a corresponding line segment in said second direction in response to the position of the scan in said first direction;
matrix means for matrixing said gated signals representative of the presence of corresponding line segments in said second direction and signals representative of corresponding line segments in said first direction to form a plurality of line signals each representative of the video signal required to generate said character on said display device during a scan in said first direction;
signal selection means for selecting one of said line signals in accord with the position of the scan in said second direction; and
combining means coupled to said video signal circuit for combining said selected line signal with a signal representative of said other information displayed on said display device.
20. A system for displaying at least two characters on the raster of a television receiver comprising: an oscillator, means for keying
the operation of the oscillator to the horizontal sync of the television receiver, a counter for counting an output of said oscillator and for producing timing signals, means for developing and multiplexing coded data representing each of said characters to be displayed in accordance with said timing signals, a seven segment decoder having a plurality of inputs and outputs for developing signals on a predetermined combination of said outputs in response to each selected coded input, means for coupling the coded data to given inputs of said decoder, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal, and means for adding the generated video signal in the television receiver video circuit to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit. 21. A channel number display system in accordance with claim 20 wherein said data developing and multiplexing means has units digits gates and tens digits gates, said timing signal multiplexing data between said units and tens digits gates into at least four output lines, and means for coupling said multiplexing data to inputs of said seven segment decoder.
22. A channel number display system in accordance with claim 21 wherein means are provided to blank the display system output for a time interval between the switching of said data developing and multiplexing means from the units digits gates to the tens digits gates to provide spacing between the units and tens characters on the raster of the cathode ray tube.
23. A channel number display system in accordance with claim 22 wherein select means are provided to select one of a greater number of variable character displays, said means including a BCD signal responsive select circuit.
24. A channel number display system in accordance with claim 23 wherein said select means includes a four-six character select circuit for selecting either four or six character display.
25. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit. 26. A display system in accordance with claim 25 wherein said circuit means further comprises counting means coupled to the output of said oscillator and developing signals indicative of the horizontal position of the beam of the cathode ray tube of said broadcast television receiver.
27. A display system in accordance with claim 26 further comprising means coupled to the horizontal scan circuitry of said broadcast television receiver and said counting means for resetting said counting means.
28. A system for displaying a character indicating the channel being received on the raster of a broadcast television receiver comprising: means for developing coded data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling the coded data to given inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each selected coded input, circuit means for processing the signal on each of said outputs of said decoder into a given line segment generated video signal and comprising an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver, means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for multiplexing the outputs of said decoding means in accordance with the line of scan of the beam of the cathode ray tube of said broadcast television receiver, and means for adding the generated video signal in a video circuit of said broadcast television receiver to develop a character display on the raster of the television receiver in addition to any other signal being processed by said video circuit.
29. A display system in accordance with claim 28 wherein said decoding means comprises a seven segment decoder.
30. A display system in accordance with claim 28 wherein a line counter is provided to count horizontal scans of the cathode ray beam and wherein the output of said counter is coupled to said multiplexing means to control the same.
31. A display system in accordance with claim 30 further comprising means coupled to the horizontal scan circuitry of said broadcast television receiver and said counting means for resetting said counting means.
32. A system for displaying a character indicative of the channel being received on the picture display device of a broadcast television receiver comprising: means for developing data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling said data to inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each data input, circuit means for processing the signal on said outputs of said decoder into a video signal for generating a line segment character and including an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization signal of received broadcast television signals for keying said oscillator, and means for adding said video signal to other video signals being processed by said broadcast television receiver to develop a character display on said picture display device.
33. A system for displaying a character indicative of the channel being received on the picture display device of a broadcast television receiver comprising: means for developing data indicative of the character to be displayed, decoding means having a plurality of inputs and outputs, means for coupling said data to inputs of said decoding means, said decoding means being a device for developing signals on a predetermined combination of outputs in response to each data input, circuit means for processing the signal on said outputs of said decoder into a video signal for generating a line segment character and including an oscillator having a frequency substantially higher than the horizontal line frequency of said broadcast television receiver and means responsive to the horizontal synchronization circuitry of said broadcast television receiver for keying said oscillator, and means for adding said video signal to other video signals being processed by said broadcast television receiver to develop a character display on said picture display device.
Description:
BACKGROUND OF THE INVENTIONThe use of on-screen display of a channel number, for instance, has been proposed in an article entitled, "Broadcast and Television Receivers" IEEE, Vol. BTR-15, No. 2, July 1969, however, the character generators which are available commercially are generally "read only memories" designed to display either 16 or 64 alpha-numeric characters. These character generators require 350 memory bits for 10 characters. In such a device, all 35 possible positions in a 5 × 7 font are used for the numerals. The character generator is the most expensive element of such a system.
A Co-pending
Patent Application of Ralph Joseph Ludlam entitled, "Electronic Channel Selection & Device", Ser. No. 265,231, now abandoned, describes a system for producing digital information representative of a selected channel. This data may be used by the display system of the present invention. FIELD OF THE INVENTION
The field of art to which this invention pertains is on-screen display of characters in a television receiver with character generation locally in the receiver.
SUMMARY OF THE INVENTION
It is an important feature of the present invention to provide an improved system for the display of characters on the screen of a television receiver using character generating means locally in the receiver.
It is another feature of the present invention to provide a relatively inexpensive means for generating characters in a system as described above.
It is a principal object of the present invention to provide an on-screen character display system for a television receiver which utilizes a character generator having a segment decoder for transforming digital information into line segment information and having means for gating and multiplexing the line segment information into a usable video output signal.
It is a further feature of the present invention to provide a character generator described above including a seven segment decoder having direct coupling from the output of the decoder to a multiplexing stage for the horizontal segments of each character and having coupling to the multiplexer through a gating circuit for the vertical segments of the character.
It is a further feature of the present invention to provide a circuit as described above which includes a vertical and horizontal delay means as well as vertical and horizontal blanking means to properly position the characters at a predetermined location on the screen of the television receiver.
It is an additional feature of the present invention to provide a circuit as described above which includes means for blanking the character generating portion of the video signal between characters to provide adequate spacing.
It is also an object of this invention to provide circuit means for generating additional characters such as characters to indicate the time of day on the screen of a television receiver.
Other References:
Olson et al., "The Practical Application of On-Screen Display to a Television Receiver", IEEE Transactions on Broadcast and TV Receivers, _Aug. 1973, pp. 169-175. Walker, "For TV Tuners a Digital Look", Electronics, Jun. 26, 1975, pp. 65-66.
Evans et al., "Direct Address Television Tuning and Display System Using Digital MOS Large Scale Integration", IEEE Transactions on Consumer Electronics, vol. CE-22, No. 4, pp. 267-288, Nov. 1976.
Electronics, vol. 48, No. 24, Nov. 27, 1975, "Philips TV Set Indicates Station Tuning and Color Settings on Screen", pp. 6E and 8E.
Werner, "Linear Color Bar Display for CTV Sets", Radio Mentor Electronic, vol. 41, No. 9, pp. 350-351, Sep. 1975.
Programmable television receiver controllers which may be manually programmed by a user to select or to limit the viewing selections for random times, typically in one-half hour intervals, throughout a predetermined time period such as a one week time period. Program selections may be made by setting suitable controls for the day, AM or PM, the half hour of the day and the channel desired, and entered into a memory by a push-button control. Thereafter a digital control clock automatically selects the pre-entered information at the appropriate times and provides a control signal which may be used to automatically select the identified channels to the exclusion of all others. Alternatively, the signal may be used to exclude the selected channel from selection manually. In one embodiment, the programmable controller is incorporated in the original design of the television receiver and in a second embodiment, an external controller is disclosed which can be attached to the antenna terminals of a conventional television. Additional embodiments include means for controlling other functions such as the ON-OFF function of the receiver.1. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address for application to said memory means means for generating said write-addresses;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and
control means for controlling the reception of a television receiver according to said data read from said memory means.
2. The controller of claim 1 wherein said memory means is a semiconductor memory. 3. The controller of claim 1 wherein said storing means includes a means for generating said write-addresses which is responsive to the position of at least one first switch and a means for generating said data corresponding to channel selections which is responsive to the position of at least one second switch. 4. The controller of claim 1 wherein said controller means controls the reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 5. A programmable television controller comprising: random-access memory means for storing data;
write-address means selectively generating a write-address corresponding to a future time for application to said memory means;
program means for selectively storing said data in said memory means at said write-address;
read-address means for generating said read-addresses responsive to real time;
memory read means for applying said read-addresses to said memory means for reading out said data stored in said memory means; and
control means for controlling the reception of a television receiver according to said data read from said memory means.
6. The controller of claim 5 wherein said memory means is a semiconductor memory. 7. The controller of claim 5 wherein said data means comprises at least one switch. 8. The controller of claim 5 wherein said write-address means comprises at least one switch. 9. The controller of claim 5 wherein said program means comprises:
means for normally coupling said read-address means to said memory;
means for normally placing said memory in a read mode;
switching means for momentarily decoupling the read-address means from said memory means, coupling said write-address means to said memory means, and switching said memory means from said read mode to a write mode.
10. The controller of claim 5 wherein said read-addresses are binary coded signals which increment on one-half hour intervals. 11. The controller of claim 5 wherein said control means controls said reception of said television receiver by limiting the reception to a channel corresponding to said data read from said memory means if said data is present. 12. The controller of claim 5 wherein said control means controls the reception of said television receiver by limiting the reception to a channel other than the channel corresponding to said data received from said memory means if said data is present. 13. The controller of claim 5 wherein said control means includes a pretuner means having at least one input for coupling to a television receiver antenna and a pretuner output for coupling to an input on a television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal. 14. The controller of claim 13 wherein said control means further includes a disable means for disabling said control means thereby preventing reception of any channel when a power source powering said controller is interrupted, said disable means continuing to disable said controller until said disable means is reset. 15. The controller of claim 13 wherein said controller is installed within a controller housing, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller. 16. The controller of claim 13 wherein said pretuner output is for coupling to an antenna input on the television receiver and the frequency of said fixed frequency signal corresponds to a predetermined television signal. 17. The controller of claim 13 wherein said pretuner output is for coupling to an input of an intermediate frequency amplifier stage in the television receiver and the frequency of said fixed frequency signal corresponds to the intermediate frequency amplifier stage frequency of operation. 18. A programmable television controller comprising:
a random-access memory means for storing data;
storing means for storing data corresponding to channel selections in said memory means at write-addresses corresponding to future time periods, with said storing means including a write-address means for generating said write-addresses for application to said memory means;
read means for reading out said data from said memory means by application of real time related read-addresses thereto when real time coincides with said future time periods and,
control means for controlling the reception of a television receiver according to said data read from said memory means, said control means including a pretuner means having at least one input for coupling to a television receiver antenna and pretuner output for coupling to an input on the television receiver, said pretuner means being a means for selectively converting any one of a plurality of multi-frequency television signals present at said pretuner input to a fixed frequency signal;
a controller housing for housing said controller, said controller housing being located outside a television receiver housing which encloses the television receiver controlled by said controller.
Description:
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to the field of automatic controllers, and more particularly, to programmable controllers for use with television receivers and like equipment.
2. Prior Art
Many systems have been proposed for the automatic control of television receivers, that is, automatic channel selection for particular times of the day based upon programming information entered into the controller at some previous time. Most of these systems, however, are in substantial part mechanical systems which are not particularly easy to program, thereby being relatively expensive to manufacture and difficult to use. Accordingly, such systems have not enjoyed significant commercial use on conventional receivers.
Simple programmable television receiver controllers would provide a number of advantages over conventional channel selectors, and even over remote controlled channel selectors for a number of reasons. There may be programs of particular merit or interest which a viewer does not want to miss. However, the viewer's attention may inadvertently be drawn to another channel at the time, thereby failing to change channels to the more desirable program at the appropriate time. Also at the present time, a number of programs and movies being shown on T.V. are directed toward an adult audience, which programs may be undesirable or outright unsuitable for viewing by children, a situation which may only be expected to increase in the future. In addition, more andmore homes have at least one television receiver controllable at least a substantial amount of the time by children, whereby with conventional channel selectors the "viewers discretion" cannot be exercised by a parent. Accordingly, aprogrammable controller could be programmed periodically, such as once a week, so that those programs of highest merit or viewer interest, will be automatically selected and/or predetermined unobjectionable programs will be selected at times when objectionable programming is being televised on other channels. As an alternative, of course, objectionable programming itself could be programmed for the purposes of locking out such programs from the viewer's selections, e.g., eliminating such programming from the channel selections accessible from the manual channel selector.
U.S. Pat. Nos. 3,215,798 and 3,388,308 disclose automatic television programming systems of the mechanical or electromechanical type, whereby a rotary device mechanically tied to a time clock is programmed to provide some physical movement indicative of the channel to be selected at that time. Devices of the same general type involving some form of motor driven switching unit are also disclosed in U.S. Pat. Nos. 2,755,424, 3,496438, and 3,569,839. In all of these patents the mechanical complexity of the system disclosed is believed to preclude the widespread adoption thereof on receivers intended for consumer use. Further, most of these systems are operative on a number of switching signals equal to the number of selections desired, though some coding to somewhat reduce the complexity of such systems is known, such as that in U.S. Pat. No. 3,496,438. Also, obviously timing mechanisms or the electromechanical type for various other applications are also known, that disclosed in U.S. Pat. No. 3,603,961 being but one example of such devices.
BRIEF SUMMARY OF THE INVENTION
PHILIPS 26C970/00R REMBRANDT CHASSIS K12I AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION
The sensor in this set is incorporated in the contrast button selector above upside right located near the power ON OFF switch.
1. In a color television apparatus, a circuit for varying color display characteristics in accordance with variations in ambient light comprising: 2. In a color picture display system having a display device comprising: 3. The display system of claim 2 with kinescope means having a first set of electrodes and a second set of electrodes, 4. The display system of claim 2 with said light sensing means being responsive to the intensity of the ambient light and said parameter varying in accordance with the intensity of ambient light. 5. The display system of claim 4 with said modifying means increasing the gain of said luminance amplifying means at a greater rate than the gain of said chroma amplifying means as said ambient light intensity is increased. 6. A color television apparatus comprising: 7. In a color television receiver: 8. The receiver of claim 7 with said modifying means comprising a light dependent resistor means, 9. The receiver of claim 8 with second impedance means coupling said light dependent resistor means to said luminance gain means to control the gain of said luminance gain means. 10. The receiver of claim 9 with said second impedance means comprising a parallel combination of capacitance and resistance. 11. The receiver of claim 7 with said modifying means varying the gain of the luminance gain means at a greater rate than the gain of the chroma gain means as ambient light is varied. 12. The receiver of claim 7 with said modifying means being responsive to the intensity of ambient light and said parameter being varied as the intensity of the ambient light is varied. 13. The receiver of claim 7 with said modifying means attenuating the gain of said luminance amplifying means approximately fifty percent more than the gain of said chroma amplifying means, when the attenuation is measured in decibels, as said ambient light intensity is decreased. 14. In a color television receiver: 
Description:
BACKGROUND OF THE INVENTION
The present invention relates generally to a television receiver control system and more particularly to a control system for maintaining proper balance between room lighting conditions and the level of picture tube excitation in a color television receiver. More especially the present invention functions to increase contrast, intensity and chroma signal strength when the room lighting level increases to diminish these parameters when the level of room lighting decreases.
Conventional television receivers, of course, have manually operable controls by means of which a viewer may set the level of contrast, intensity, and chroma signal strength to what he feels to be an optimum level for given room lighting conditions. Under changed room lighting conditions, the viewer will obtain the optimum viewing situation by changing these manual controls to a new preferred level.
It is also known in the prior art to automate this process for a black and white television receiver, for example, as taught in the U.S. Pat. No. 3,165,582 to Korda, issued Jan. 12, 1965, and the French patent 1,223,058 issued in June of 1960.
It is accordingly an object of the present invention to provide an automatic color saturation control for a color television receiver by providing separate, predetermined gains for the luminance and chroma for a given change in ambient light. In the disclosed preferred embodiment, the luminance signal is attenuated 3.3 dB and the chroma signal is attenuated 2.1 dB for a change in ambient light from 100 footcandles to 0.1 footcandles, measured at the display face.
SUMMARY OF THE INVENTION
The foregoing as well as numerous other objects and advantages of the present invention are achieved by providing a light sensitive element in a television receiver exposed to ambient light in the vicinity of the receiver for separately controlling brightness, contrast and chroma signal strength of the displayed picture in accordance with the level of ambient light. The circuit of a preferred embodiment of the present invention, in response to an increase of ambient light level, functions to increase the gain of the luminance amplifier in a relatively greater ratio than the increase in the gain of the chrominance amplifier whereas when the ambient light level decreases the respective gains of these two amplifiers are decreased, again, with the change in the luminance signal being in a greater proportion than the change in the chroma signal strength signal. By using the teaching of this invention, other gain relationships between the luminance components and chroma signal, for a given change in ambient light, may be automatically attained to achieve a desired result of luminance and color saturation.
BRIEF DESCRIPTION OF THE DRAWINGS
The aforementioned and other objects, features and advantages of the present invention will become more apparent from the following detailed description thereof when considered in conjunction with the drawings wherein:
FIG. 1 is a partial block diagram of a color television receiver employing the present invention;
FIG. 2 is a detailed schematic diagram of those portions of FIG. 1 embodying the present invention;
FIG. 3 illustrates chroma gain control characteristic curves for the circuit of FIG. 2; and
FIG. 4 is a graph showing changes in luminance and chroma signal strength according to changes in ambient light.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Considering first FIG. 1 which
illustrates generally in block diagram form a color television receiver embodying the present invention, this receiver is seen to comprise a tuner and radio frequency amplifier 11 for detecting and amplifying incoming signals received on the antenna 13 and supplying those signals through an appropriate heterodyning process to an intermediate frequency amplifier 15. After detection in the detector 17, the luminance signals are passed through a delay 19 which compensates for the delays experienced by the chroma signal strength signals and then to the luminance amplifier 21, which, of course, corresponds to the video amplifier of a black and white receiver, to then be supplied to the cathode ray tube 23. The luminance or video amplifier may also be provided with gain control circuitry 25. An appropriate band pass amplifier 27 may be employed to separate out the chroma signal strength signals which are demodulated by the demodulator 29 in well known fashion to provide the three color difference signals to grids in the color cathode ray tube 23. While the present invention will be described with respect to such color difference signals, it is equally applicable to direct RGB color separation systems. An ambient light level detector 31 such as a light dependent resistor of the cadmium sulphide variety is physically located on the front of the television receiver in such a position as to be exposed to the light levels in the vicinity of the receiver so that its resistance varies inversely in accordance with variations in the ambient light levels around the receiver. These resistance variations are then employed to control the gain of the luminance amplifier 21 by way of gain control 25 and to control the gain of the chroma signal strength amplifier circuitry.
The entire color demodulation process is only generally depicted in the block diagram of FIG. 1 and is illustrated as a closed loop burst gain controlled chroma amplifier system with auxiliary chroma gain control introduced by way of the detector 33 from the ambient light level detector 31. A burst gain controlled chroma amplifier circuit is somewhat analogous to a black and white keyed AGC circuit and functions to set the gain level of the amplifier 27 in accordance with the color sync burst rather than the chroma signal level associated with a particular picture. While the present invention is being described with respect to this preferred type of gain control, it would, of course, be possible, in television circuits employing DC gain controls for chroma and/or contrast, to connect the ambient light tracking means to these direct current control circuits. The gain controlled chroma band pass amplifier, of course, supplies an output to a burst amplifier 35 which in turn drives an automatic phase control system 37 for synchronizing the 3.58 megacycle oscillator 39 the output of which is used in the color demodulation process.
C
onsidering now FIG. 2 which illustrates schematically in detail those portions of the receiver of FIG. 1 necessary for a complete understanding of the present invention, the light dependent resistor 41 is mounted near the front of the television receiver in such a position as to adequately receive the ambient lighting conditions in the vicinity of the receiver. The resistance of this device is inversely proportional to the intensity of light incident thereon. If the room ambient light experiences an increase in level, the resistance of light dependent resistor 41 will decrease which decrease in turn lowers the voltage at the base of transistor 43 which in turn lowers the voltage at the emitter due to increased conduction through that transistor. This in turn increases the gain of the chroma amplifier transistor stage 45. More precisely the lowering the voltage at the emitter of transistor 43 raises a threshold in the automatic chroma control detector 33 so that the chroma signal strength signal, and hence the color saturation level, to the picture tube is increased. In the absence of a chroma signal with its synchronizing burst, the gain of the chroma amplifier is set at a maximum by the voltage divider comprising resistors 47 and 49. At this time there is no output from the automatic chroma control detector to the base of transistor 51 and that transistor is non-conducting.
When a color signal is received, the detector provides an output signal proportional to the color sync burst level which turns on the transistor 51 to control the gain of the chroma amplifier stage 45 so as to maintain the desired output level. The turn on level of transistor 51 represents a fairly well defined knee in the chroma gain control characteristic curves illustrated in FIG. 3. Operation beyond the knee or threshold of such a curve operates to maintain a nearly constant chroma output level while operation below the knee of the curve and its extension as the almost vertical dotted line represents the open loop characteristic wherein there is no automatic gain control to the chroma amplifier. Since transistor 51 is non-conducting below the knee of this curve, gain control is delayed until the output signal reaches this threshold point. Since variations in the potential at the emitter of transistor 43 cause corresponding variations in the potential at the base of transistor 51, it is clear that a variation in the resistance of the light dependent resistor 41 will, for example, cause the gain control characteristic curve to shift from that depicted by curve A to that depicted by curve B and that for a given burst level input as represented by the vertical dotted line, two different levels of chroma output which, in turn, cause two different levels of color saturation will be achieved by a change in the light intensity incident on the resistor 41.
To better understand the operation of detector 33, assume that the burst voltage induced across the top half of the secondary of transformer 34 is in phase with the 3.58 megacycle reference signal and that the burst voltage induced across the bottom half of the secondary of transformer 34 is 180° out of phase with this reference signal. Assuming further that the diodes 36 and 38 have equal characteristics, that the resistors 40 and 42 are equal, that the capacitors 44 and 46 are equal, and that the two portions of the secondary winding on transformer 34 are equal when no burst is being received, diodes 36 and 38 will conduct equally but during opposite portions of a cycle. Diode 36 conducts during negative excursions of the reference signal whereas diode 38 conducts during positive portions of that reference wave form. Thus during the negative portions of the reference wave form diode 36 conducts to charge capacitor 44 so that its right hand plate is negative and its left hand plate is positive. During the positive excursions, diode 38 conducts to charge capacitor 46 with its right hand plate positive and its left hand plate negative. Under this assumed no burst input condition the net charge on these capacitors yields a voltage on line 48 which is zero. If noise is introduced into the system, it will be of equal amplitude but opposite phase across the two diodes and both diodes will be affected to an equal extent resulting in no change in the voltage on line 48. When during a color telecast a burst signal is present, we may assume that the burst voltage induced across the two portions of the secondary of transformer 34 are of equal amplitude to the 3.58 megacycle reference signal. With this situation the diode 36 will not conduct since the burst voltage is equal in phase and amplitude to the reference signal and its anode and cathode remain at the same potential. The diode 38
will, however, conduct readily since the burst and reference signals have an additive rather than a cancelling effect on it resulting in the diode 38 conducting twice as much as in the previous no burst example and resulting in the capacitor 46 charging to about twice its previous voltage which voltage is presented on line 48 as a control signal.
Suppose now that the burst signal amplitude is reduced to one half that of the foregoing example. With this new assumption the phase relationships remain as before but now diode 36 will conduct about one half its previous amount while diode 38 conducts about one and one half times its previous amount resulting in a voltage on line 48 which is about one half the previous voltage.
The voltage on line 48 which is approximately proportional to the burst voltage is applied to the base of transistor 51 which biases the base of the chroma amplifier transistor 45 thereby controlling the gain of that chroma amplifier stage.
A variation in threshold can be achieved by altering the conduction points of the diodes 36 and 38. This is accomplished by applying a bias voltage to the junction of these two diodes to alter their respective points of conduction thereby changing the output voltage on line 48. For example, if a positive 2-volt direct current bias is applied to the junction of the two diodes, under a no burst input condition, diode 38 will conduct sooner and turn off later than with no bias applied, while diode 36 will turn on later and off sooner than under the no bias condition. This results in a control voltage on line 48 under the no burst condition. In other words, a bias voltage applied to the junction of the two diodes acts as an additional bias on the chroma amplifier stage thereby affecting its gain.
The control of brightness (intensity) and contrast is achieved in the present invention by a second light dependent resistor 53 which is optically coupled to a light emitting diode 55. LIght emitting diode 55 and light dependent resistor 53 are encapsulated in a light impervious housing illustrated by the dotted line 57. As the room ambient light changes, the change in the resistance of light dependent resistor 41 causes a change in the current through light emitting diode 55. Variations in the current through the light emitting diode cause corresponding variations in the light emitted thereby which in turn cause variations in the resistance of the light dependent resistor 53. The luminance or video amplifier is here illustrated as a three transistor amplifier with the output of the first amplifier stage being across resistor 59. A diminution in the resistance of light dependent resistor 53 causes a lowering of this output impedance and thus a diminution in the gain of the luminance amplifier. In other words, if the light intensity in the room increases, the resistance of resistor 41 will decrease causing a decrease in the current through light emitting diode 55 and, therefore, a decrease in its light output level and this decreased light will cause an increase in the resistance of light dependent resistor 53 thus increasing the effective output load resistor for the transistor 61 thus increasing the gain of the video amplifier as desired.
Variable resistor 63 being effectively in series with the light dependent resistor 41 may be varied to compensate for differences in specific light dependent resistors so as to establish a desired level of picture brightness, contrast and color saturation for a given level of ambient light. Variable resistance 65 which is in parallel with the light dependent resistor 41 may be varied so as to effectively change the range of variation in brightness, contrast and color saturation for a specific range of variations in the ambient light conditions. The entire automatic control circuit of the present invention may be bypassed by closing the defeat switch 67.
Looking now at FIGS. 2 and
4, the relative attenuation of the chroma channel and luminance channel will become apparent. Looking first at FIG. 4, the abscissa is the measure of ambient illumination in foot candles on a log scale, and the ordinate is the measure of attenuation of signal amplitude in dB. At 100 footcandles there is 0 dB attenuation of luminance and chroma signals and as the ambient illumination decreases to 0.1 foot candles, it is seen that the chroma signal line 72 is down 2.1 dB while the luminance signal line 72 is down 3.3 dB. This ratio has been found to be a highly satisfactory ratio giving a very pleasing picture at all ambient light levels between 0.1 footcandles and 100 footcandles of ambient light.
The manner in which this variation in luminance attenuation is achieved may be seen by looking at FIG. 2. As mentioned, the chroma channel signal is varied by the conduction level of transistor 43. As light dependent resistor 41 changes in resistance, the conduction level of transistor 43 will also change with the degree of change being determined by divider resistances 75 and 76. Further the luminance channel gain is determined by resistor 77 since it is this resistor which will control the signal level of light emitting diode 55 which in turn will control the gain to luminance transistor 61. It is these resistors which determine the relative amount of attenuation of gain in the chroma and luminance channels as the ambient light is changed. In this embodiment, resistance 75 is 5.6 k ohms, resistance 76 is 4.3 k ohms, resistance 77 is 3.9 k ohms, resistance 78 is 7.5 k ohms, the voltage applied to the upper terminal of resistance 78 is 35 volts, resistance 63 is 500 ohms, resistance 65 is 25 k ohms, resistance 69 is 4.7 k ohms, capacitance 71 is 47 microfarads, resistance 59 is 1 k ohm, resistance 59a is 6.8 k ohms, resistance 62a is 1 k ohms, resistance 64a is 100 ohms, resistance 64b is 6.8 k ohms. Light dependent resistor 41 is a Clariex CL-11360, photocoupler unit 57 is Magnavox Part Number 701482. Transistors 43, 61, 62, and 64 are 2N3962, 2N4916, MPSA20 and 25C685A, respectively. This invention has been incorporated in a Magnavox Company T979 color television chassis.
The effective load resistance for the transistor 61 under direct current conditions is the parallel combination of the resistor 59 and the series pair of resistors 53 and 69 whereas due to the presence of capacitor 71 this effective load resistance under alternating current conditions is the parallel combination of resistors 59 and 53. Thus the ratio of AC to DC gain for this video amplifier stage may be selected by proper selection of these parameters so as to maintain the black level of the picture essentially constant.
Thus while the present invention has been described with respect to a specific embodiment, numerous modifications will suggest themselves to those of ordinary skill in the art. Since the luminance and chroma gains are individually controlled for a given change in ambient light, the gain ratios between the luminance and chroma channels may be selected as desired to achieve a desired effect for a given change in ambient light. Also, while the present invention has been described in the environment of a television receiver, the invention could equally well be used in television monitors as well as many other types of display devices. Accordingly the scope of the present invention is to be measured only by that of the appended claims.
Conventional television receivers, of course, have manually operable controls by means of which a viewer may set the level of contrast, intensity, and chroma signal strength to what he feels to be an optimum level for given room lighting conditions. Under changed room lighting conditions, the viewer will obtain the optimum viewing situation by changing these manual controls to a new preferred level.
It is also known in the prior art to automate this process for a black and white television receiver, for example, as taught in the U.S. Pat. No. 3,165,582 to Korda, issued Jan. 12, 1965, and the French patent 1,223,058 issued in June of 1960.
SUMMARY OF THE INVENTION
BRIEF DESCRIPTION OF THE DRAWINGS
The aforementioned and other objects, features and advantages of the present invention will become more apparent from the following detailed description thereof when considered in conjunction with the drawings wherein:
FIG. 1 is a partial block diagram of a color television receiver employing the present invention;
FIG. 2 is a detailed schematic diagram of those portions of FIG. 1 embodying the present invention;
FIG. 3 illustrates chroma gain control characteristic curves for the circuit of FIG. 2; and
FIG. 4 is a graph showing changes in luminance and chroma signal strength according to changes in ambient light.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Considering first FIG. 1 which
illustrates generally in block diagram form a color television receiver embodying the present invention, this receiver is seen to comprise a tuner and radio frequency amplifier 11 for detecting and amplifying incoming signals received on the antenna 13 and supplying those signals through an appropriate heterodyning process to an intermediate frequency amplifier 15. After detection in the detector 17, the luminance signals are passed through a delay 19 which compensates for the delays experienced by the chroma signal strength signals and then to the luminance amplifier 21, which, of course, corresponds to the video amplifier of a black and white receiver, to then be supplied to the cathode ray tube 23. The luminance or video amplifier may also be provided with gain control circuitry 25. An appropriate band pass amplifier 27 may be employed to separate out the chroma signal strength signals which are demodulated by the demodulator 29 in well known fashion to provide the three color difference signals to grids in the color cathode ray tube 23. While the present invention will be described with respect to such color difference signals, it is equally applicable to direct RGB color separation systems. An ambient light level detector 31 such as a light dependent resistor of the cadmium sulphide variety is physically located on the front of the television receiver in such a position as to be exposed to the light levels in the vicinity of the receiver so that its resistance varies inversely in accordance with variations in the ambient light levels around the receiver. These resistance variations are then employed to control the gain of the luminance amplifier 21 by way of gain control 25 and to control the gain of the chroma signal strength amplifier circuitry.C
onsidering now FIG. 2 which illustrates schematically in detail those portions of the receiver of FIG. 1 necessary for a complete understanding of the present invention, the light dependent resistor 41 is mounted near the front of the television receiver in such a position as to adequately receive the ambient lighting conditions in the vicinity of the receiver. The resistance of this device is inversely proportional to the intensity of light incident thereon. If the room ambient light experiences an increase in level, the resistance of light dependent resistor 41 will decrease which decrease in turn lowers the voltage at the base of transistor 43 which in turn lowers the voltage at the emitter due to increased conduction through that transistor. This in turn increases the gain of the chroma amplifier transistor stage 45. More precisely the lowering the voltage at the emitter of transistor 43 raises a threshold in the automatic chroma control detector 33 so that the chroma signal strength signal, and hence the color saturation level, to the picture tube is increased. In the absence of a chroma signal with its synchronizing burst, the gain of the chroma amplifier is set at a maximum by the voltage divider comprising resistors 47 and 49. At this time there is no output from the automatic chroma control detector to the base of transistor 51 and that transistor is non-conducting.To better understand the operation of detector 33, assume that the burst voltage induced across the top half of the secondary of transformer 34 is in phase with the 3.58 megacycle reference signal and that the burst voltage induced across the bottom half of the secondary of transformer 34 is 180° out of phase with this reference signal. Assuming further that the diodes 36 and 38 have equal characteristics, that the resistors 40 and 42 are equal, that the capacitors 44 and 46 are equal, and that the two portions of the secondary winding on transformer 34 are equal when no burst is being received, diodes 36 and 38 will conduct equally but during opposite portions of a cycle. Diode 36 conducts during negative excursions of the reference signal whereas diode 38 conducts during positive portions of that reference wave form. Thus during the negative portions of the reference wave form diode 36 conducts to charge capacitor 44 so that its right hand plate is negative and its left hand plate is positive. During the positive excursions, diode 38 conducts to charge capacitor 46 with its right hand plate positive and its left hand plate negative. Under this assumed no burst input condition the net charge on these capacitors yields a voltage on line 48 which is zero. If noise is introduced into the system, it will be of equal amplitude but opposite phase across the two diodes and both diodes will be affected to an equal extent resulting in no change in the voltage on line 48. When during a color telecast a burst signal is present, we may assume that the burst voltage induced across the two portions of the secondary of transformer 34 are of equal amplitude to the 3.58 megacycle reference signal. With this situation the diode 36 will not conduct since the burst voltage is equal in phase and amplitude to the reference signal and its anode and cathode remain at the same potential. The diode 38
Suppose now that the burst signal amplitude is reduced to one half that of the foregoing example. With this new assumption the phase relationships remain as before but now diode 36 will conduct about one half its previous amount while diode 38 conducts about one and one half times its previous amount resulting in a voltage on line 48 which is about one half the previous voltage.
The voltage on line 48 which is approximately proportional to the burst voltage is applied to the base of transistor 51 which biases the base of the chroma amplifier transistor 45 thereby controlling the gain of that chroma amplifier stage.
A variation in threshold can be achieved by altering the conduction points of the diodes 36 and 38. This is accomplished by applying a bias voltage to the junction of these two diodes to alter their respective points of conduction thereby changing the output voltage on line 48. For example, if a positive 2-volt direct current bias is applied to the junction of the two diodes, under a no burst input condition, diode 38 will conduct sooner and turn off later than with no bias applied, while diode 36 will turn on later and off sooner than under the no bias condition. This results in a control voltage on line 48 under the no burst condition. In other words, a bias voltage applied to the junction of the two diodes acts as an additional bias on the chroma amplifier stage thereby affecting its gain.
Variable resistor 63 being effectively in series with the light dependent resistor 41 may be varied to compensate for differences in specific light dependent resistors so as to establish a desired level of picture brightness, contrast and color saturation for a given level of ambient light. Variable resistance 65 which is in parallel with the light dependent resistor 41 may be varied so as to effectively change the range of variation in brightness, contrast and color saturation for a specific range of variations in the ambient light conditions. The entire automatic control circuit of the present invention may be bypassed by closing the defeat switch 67.
Looking now at FIGS. 2 and
4, the relative attenuation of the chroma channel and luminance channel will become apparent. Looking first at FIG. 4, the abscissa is the measure of ambient illumination in foot candles on a log scale, and the ordinate is the measure of attenuation of signal amplitude in dB. At 100 footcandles there is 0 dB attenuation of luminance and chroma signals and as the ambient illumination decreases to 0.1 foot candles, it is seen that the chroma signal line 72 is down 2.1 dB while the luminance signal line 72 is down 3.3 dB. This ratio has been found to be a highly satisfactory ratio giving a very pleasing picture at all ambient light levels between 0.1 footcandles and 100 footcandles of ambient light.The manner in which this variation in luminance attenuation is achieved may be seen by looking at FIG. 2. As mentioned, the chroma channel signal is varied by the conduction level of transistor 43. As light dependent resistor 41 changes in resistance, the conduction level of transistor 43 will also change with the degree of change being determined by divider resistances 75 and 76. Further the luminance channel gain is determined by resistor 77 since it is this resistor which will control the signal level of light emitting diode 55 which in turn will control the gain to luminance transistor 61. It is these resistors which determine the relative amount of attenuation of gain in the chroma and luminance channels as the ambient light is changed. In this embodiment, resistance 75 is 5.6 k ohms, resistance 76 is 4.3 k ohms, resistance 77 is 3.9 k ohms, resistance 78 is 7.5 k ohms, the voltage applied to the upper terminal of resistance 78 is 35 volts, resistance 63 is 500 ohms, resistance 65 is 25 k ohms, resistance 69 is 4.7 k ohms, capacitance 71 is 47 microfarads, resistance 59 is 1 k ohm, resistance 59a is 6.8 k ohms, resistance 62a is 1 k ohms, resistance 64a is 100 ohms, resistance 64b is 6.8 k ohms. Light dependent resistor 41 is a Clariex CL-11360, photocoupler unit 57 is Magnavox Part Number 701482. Transistors 43, 61, 62, and 64 are 2N3962, 2N4916, MPSA20 and 25C685A, respectively. This invention has been incorporated in a Magnavox Company T979 color television chassis.
The effective load resistance for the transistor 61 under direct current conditions is the parallel combination of the resistor 59 and the series pair of resistors 53 and 69 whereas due to the presence of capacitor 71 this effective load resistance under alternating current conditions is the parallel combination of resistors 59 and 53. Thus the ratio of AC to DC gain for this video amplifier stage may be selected by proper selection of these parameters so as to maintain the black level of the picture essentially constant.
Thus while the present invention has been described with respect to a specific embodiment, numerous modifications will suggest themselves to those of ordinary skill in the art. Since the luminance and chroma gains are individually controlled for a given change in ambient light, the gain ratios between the luminance and chroma channels may be selected as desired to achieve a desired effect for a given change in ambient light. Also, while the present invention has been described in the environment of a television receiver, the invention could equally well be used in television monitors as well as many other types of display devices. Accordingly the scope of the present invention is to be measured only by that of the appended claims.PHILIPS 26C970/00R REMBRANDT CHASSIS K12I AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION Gain control arrangement useful in a television signal processing system
1. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut-off at predetermined voltages which may or may not be the same voltage;
a gain controlling voltage source;
means for coupling said gain controlling voltage to said first amplifier to control its gain;
potentiometer means coupled between a fixed voltage substantially equal to the extrapolated cut-off voltage of said second amplifier and to said gain controlling voltage source to recieve a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut-off voltages of said first and second amplifiers; and
2. The apparatus recited in claim 1 wherein said means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut-off voltage of said first amplifier and said gain controlling voltage source. 3. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain control voltage characteristics including linear portions extrapolated to cut-off at substantially the same predetermined voltage;
a source of gain controlling voltage; and
means for coupling said gain controlling voltage to said first and second amplifiers.
4. Apparatus comprising:
first variable gain amplifying means for amplifying a first signal in response to a first DC control signal, said first amplifying means having a first gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to VO ;
second variable gain amplifying means for amplifying a second signal in response to a second DC control signal, said second amplifying means having a second gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to AVO, where A is a number greater than 0;
a first source of fixed voltage substantially equal to VO ;
a second source of fixed voltage substantially equal to AVO ;
means for developing a third DC control voltage v;
means for developing a portion Av of said third control voltage v;
first means for deriving said first control voltage including means for providing the difference between said third control voltage v and said fixed voltage VO and means for adding a predetermined portion of the difference between said third control voltage v and said fixed voltage VO to said DC control voltage v; and
second means for deriving said second control voltage including means for providing the difference between a portion Av of said third control voltage v and said fixed voltage AVO and means for adding a predetermined portion of the difference between said portion Av and said fixed voltage AVO to said DC control voltage v.
Description:
The present invention pertains to gain controlling apparatus and particularly to apparatus for controlling the gains of amplifiers included in the luminance and chrominance channels of a television signal processing system.Recently, the maximum brightness available from television receivers has increased sufficiently so that a pleasing image may be reproduced under conditions of high ambient light as well as under conditions of low ambient light. Apparatus is known for automatically controlling the contrast and brightness properties of a television receiver in response to ambient light to provide a pleasing image over a range of ambient light conditions. Such apparatus is described in U.S. Pat. Nos. 3,027,421, entitled "Circuit Arrangements For Automatically Adjusting The Brightness And The Contrast In A Television Receiver," issued to H. Heijligers on Mar. 27, 1962 and 3,025,345, entitled "Circuit Arrangement For Automatic Readjustment Of The Background Brightness And The Contrast In A Television Receiver," issued to R. Suhrmann on Mar. 13, 1962.
Apparatus is also known for automatically controlling the contrast and saturation properties of a color television receiver by controlling the gains of luminance and chrominance channel amplifiers, respectively, in response to ambient light. Such apparatus is described in U.S. Pat. Nos. 3,813,686 entitled "Ambient Light Responsive Control Of Brightness, Contrast And Color Saturation," issued to Eugene Peter Mierzwinski, on May 28, 1974 and 3,814,852 entitled "Ambient Light Responsive Control Of Brightness, Contrast and Color Saturation," issued to Eugene P. Mierzwinski on June 4, 1974.
Also of interest is apparatus for manually controlling the gains of luminance and chrominance channel amplifiers. Such apparatus is described in U.S. Pat. Nos. 3,374,310, entitled "Color Television Receiver with Simultaneous Brightness and Color Saturation Controls," issued to G.L. Beers on Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic Control Circuit," issued to DuMonte O. Voigt on June 7, 1966; and 3,715,463, entitled "Tracking Control Circuits Using a Common Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When the gain of luminance channel is adjusted to control the contrast of an image, either manually or automatically, in response to ambient light, it is desirable to simultaneously control the gain of the chrominance channel in such a manner that the ratio of the gains of the luminance and chrominance channels is substantially constant over a wide range of contrast control to maintain constant saturation. If the proper ratio between the amplitudes of the chrominance and luminance signals is not maintained incorrect color reproduction may result. For instance, if the amplitude of the luminance signals are increased without correspondingly increasing the amplitude of the chrominance signals, colors may become desaturated, i.e., they will appear washed out or pastel in shade. Furthermore, it may be desirable to provide controls for presetting the gains of the luminance and chrominance channels to compensate for tolerance variations in other portions of the television signal processing apparatus.
In accordance with another feature of the present invention, the means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of said first amplifier and said gain controlling voltage source.
In accordance with still another feature of the present invention the gain controlling voltage source includes an element responsive to ambient light .
These and other aspects of the present invention may best be understood by references to the following detailed description and accompanying drawing in which:
FIG. 1 shows the general arrangement, partly in block diagram form and partly in schematic diagram form, of a color television receiver employing an embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG. 2 shows graphical representation of gain versus control voltage characteristics of amplifiers utilized in the embodiment shown in FIG. 1;
FIG. 3 shows graphical representations of gain versus control voltage characteristics of amplifiers which may be utilized in the receiver shown in FIG. 1;
FIG. 4 shows, in schematic form, another embodiment of the present invention which may be utilized to control the amplifiers whose gain versus control voltage characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now
to FIG. 1, the general arrangement of a color television receiver employing the present invention includes a video signal processing unit 112 responsive to radio frequency (RF) television signals for generating, by means of suitable intermediate frequency (IF) circuits (not shown) and detection circuits (not shown), a composite video signal comprising chrominance, luminance, sound and synchronizing signals. The output of signal processing unit 112 is coupled to chrominance channel 114, luminance channel 116, a channel 118 for processing the synchronizing signals and a channel (not shown) for processing sound signals.Chrominance processing channel 114 includes chrominance processing unit 120 which serves to remove chrominance signals from the composite video signal and otherwise process chrominance signals. Chrominance signal processing unit 120 may include, for example, automatic color control (ACC) circuits for adjusting the amplitude of the chrominance channels in response to amplitude variations of a reference signals, such as a color burst signal, included in the commposite video signal. Chrominance signal processing circuits of the type described in the U.S. Pat. No. 3,740,462, entitled "Automatic Chroma Gain Control System," issued to L.A. Harwood, on June 19, 1973 and assigned to the same assignee as the present invention are suitable for use as chrominance processing unit 120.
The output of the chrominance signal processing unit 120 is coupled to chrominance amplifier 122 which serves to amplify chrominance signals in response to a DC signal vC generated by gain control network 142. As illustrated, chrominance amplifier 122 provides chrominance signals to a chroma demodulator 124. An amplifier suitable for use as chrominance amplifier 122 will subsequently be described with reference to FIG. 6.
Chroma demodulator 124 derives color difference signals representing, for example, R-Y, B-Y and G-Y information from the chrominance signals. Demodulator circuits of the general type illustrated by the chrominance amplifier CA 3067 integrated circuit manufactured by RCA Corporation are suitable for use as chrominance demodulator 124.
The color difference signals are applied to a video driver 126 where they are combined with the output signals -Y of luminance channel 116 to produce color signals of the appropriate polarity, representing for example, red (R), green (G) and blue (B) information. The color signals are coupled to kinescope 128.
Luminance channel 116 includes a first luminance signal processing unit 129 which relatively attenuates undesirable signals, such as chrominance or sound signals or both, present in luminance channel 116 and otherwise processes the luminance signals. The output of first luminance processing unit 129 is coupled to luminance amplifier 130 which serves to amplify the luminance signals in response to a DC control signal vL generated by gain control unit 142 to thereby determine the contrast of a reproduced image. An amplifier suitable for use as luminance amplifier 130 will subsequently be described with reference to FIG. 5. The output of luminance amplifier 130 is coupled to second luminance signal processing unit 132 which serves to further process luminance signals. A brightness control unit 131 is coupled to luminance signal processing unit 132 to control the DC content of the luminance signals. The output -Y of luminance processing unit 132 is coupled to kinescope driver 126.
The base of transistor 152 is coupled to the wiper of a potentiometer 146. One end of potentiometer 146 is coupled to the source of positive supply voltage VO through a fixed resistor 144. The other end of potentionmeter 146 is coupled to ground through a light dependent resistor (LDR) 148. LDR 148 is a resistance element whose impedance varies in inverse relationship with light which impinges on it. LDR 148 may comprise a simple cadmium sulfide type of light dependent element or other suitable light dependent device. LDR 148 is desirably mounted to receive ambient light in the vicinity of the screen of kinescope 128.
A single pole double-throw switch 150 has a pole coupled to the junction of potentiometer 146 and LDR 148. A resistor 151 is coupled between the wiper of potentiometer 146 and the other pole of switch 150. The arm of switch 150 is coupled to ground.
The general arrangement shown in FIG. 1 is suitable for use in a color television receiver of the type shown, for example, in RCA Color Television Service Data 1973 No. C -8 for a CTC-68 type receiver, published by RCA Corporation, Indianapolis, Indiana.
When switch 140 is in the MANUAL position, the gains of chrominance amplifier 122 and luminance amplifier 130 are controlled by adjustment of the position of potentiometer 146. When switch 150 is in the AUTO position the gain of the chrominance amplifier 122 and luminance amplifier is automatically controlled by the response of LDR 148 to ambient light conditions. The voltage developed at the wiper of potentiometer 146 (base of transistor 152) when switch 150 is in the AUTO position is inversely related to the ambient light recieved by LDR 148. It is noted that the values of resistors 114, potentiometer 146, LDR 148 and resistor 151 are desirably selected such that the adjustment of the wiper arm of potentiometer 146 when switch 150 is in the MANUAL position does not substantially affect the voltage developed at the base of transister 152 when switch 150 is placed in the AUTO position.
The control voltage v developed at the wiper arm of potentiometer 146 is coupled through emitter-follower transistor 152 to the common junction of potentiometer 156 and variable resistor 159. A control voltage vL comprising v plus a predetermined portion of the difference VO -v developed across the series connection of fixed resistor 154 and potentiometer 156, depending on the setting of potentiometer 156, is coupled to luminance amplifier 130 to control its gain. Similarly, a control voltage vC comprising v plus a predetermined portion of the difference voltage VO -v developed across the series connection of potentiometer resistor 158 and variable resistor 159, depending on the setting of the wiper of potentiometer 158, is coupled to chrominance amplifier 122 to control its gain.
The gain of luminance amplifier 130 may be pre-set to a desired value by the factory adjustment of potentiometer 156. Similarly, variable resistor 159 is provided to allow factory pre-set of the gain of the chrominance amplifier 122. Potentiometer 158 is provided to allow customer control of saturation.
R
eferring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (gC) and luminance amplifier 130 (gL) are shown. The characteristic gC has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of gC intersects the GAIN axis at GC and intersects the CONTROL VOLTAGE axis at VO. Similarly, the characteristics gL has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of gL intersects the GAIN axis at GL and intersects the CONTROL VOLTAGE axis at VO.From FIG. 2, the expression for linear portion 212 of gL is ##EQU1## The expression for linear portion 214 of gC is ##EQU2## From FIG. 1, the expression for vL is vL = v + (VO -v) K1 [3]
where K1 is determined by the voltage division of fixed resistor 154 and potentiometer 156 at the wiper of potentiometer 156. When the wiper of potentiometer 156 is at the emitter of transistor 152, K1 =0. The expression for vC is vC = v + (VO -v)K2 [4]
where K2 is determined by the voltage division of potentiometer 158 and fixed resistor 159 at the wiper of potentiometer 158. By combining equations [1] and [3], the equation for gL becomes ##EQU3## By combining equations [2] and [4], the equation for gC becomes ##EQU4## The ratio of gL to gC is thus ##EQU5## It is noted that this ratio is independent of DC control voltage v. Thus, although DC control voltage v may be varied either manually or in response to ambient light to control the contrast of an image reproduced by kinescope 128, the saturation remains constant.
With re
ference to FIG. 2, it is noted that although the linear portion 214 of gC has an extrapolated gain equal to 0 at a control voltage equal to VO, the non-linear portion of gC does not attain a gain equal to 0 until a control voltage equal to VB. That is, a control voltage of VO will not cut-off chrominance amplifier 122.In FIG. 1A there is shown, in schematic form, a modification to the arrangement of gain control network 142 of FIG. 1 with provisions which allow a viewer to cut off chrominance amplifier 122 to produce a more pleasing image under conditions of poor color reception due, for example, to noise or interference. The modifications to gain control unit 142 shown in FIG. 1A include coupling potentiometer resistor 158 between a source of positive supply voltage VB, the value of VB being greater than the value of VO, and coupling a resistor 160 from a tap-off point 162 along potentiometer 158 to ground. The value of potentiometer 158 and resistor 160 and the location of tap 162 are selected so that voltage VO is developed at tap 162.
The arrangement shown in FIG. 1A allows for the adjustment of contrast while constant saturation is maintained and additionally allows a viewer, by adjusting the wiper of potentiometer 158 to voltage VB, to cut off chrominance amplifier 122.
Referring to FIG. 3 there are shown gain versus DC control voltage characteristics of chrominance and luminance amplifiers which do not have the same extrapolated linear cut off control voltage. The gain versus control voltage characteristic gL ' of the luminance amplifier has a reverse S-shape characteristic including a linear portion 312. Extrapolated linear portion 312 of gL ' intersects the GAIN axis at a gain GL ' and intersects the CONTROL VOLTAGE axis at a voltage VO '. The gain versus control voltage characteristic gC ' of the chrominance amplifier has a reverse S-shape characteristic having a linear portion 314. Extrapolated linear portion 314 of gC ' intersects the GAIN axis at a gain GC ' and intersects the CONTROL VOLTAGE axis at a voltage AVO ', where A is a number greater than zero.From FIG. 3, the expression for linear portion 312 of gL ' is ##EQU6## where vL ' is the DC conrol voltage coupled to the luminance amplifier. The expression for linear portion 314 of gC ' is ##EQU7## where vC ' is the DC control voltage coupled to the chrominance amplifier.
A modified form of the control network 142 of FIG. 1 suitable for controlling the gain of a chrominance and a luminance amplifier having characteristics such as shown in FIG. 3 is shown in FIG. 4. Similar portions of FIGS. 1 and 4 are identified by reference numbers having the same last two significant digits and primed (') designations. The modified portions of FIG. 1 shown in FIG. 4 include the series connection resistors 460 and 462 coupled between the emitter of transistor 452 to ground. The values of resistors 460 and 462 are selected so that a portion Av' of the DC control voltage v' developed at the emitter of transistor 452 is developed at the junction of resistors 460 and 462. Furthermore, the series connection of potentiometer 458 and variable resistor 459 is coupled between the junction of resistor 460 and 462 and a source of positive supply voltage AVO '.
From FIG. 4, the expression for control voltage vL ' developed at the wiper of potentiometer 456 is vL ' = v' + (vO '-v')K1 ' [10]where K1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage vC ' developed at the wiper of potentiometer 458 is VC ' = Av' + (AVO ' - Av')K 2 ' [11]
where K2 ' is determined by the voltage division at the wiper of potentiometer 458. By combining equations [8] and [10], ##EQU8## By combining equations [9] and [11], ##EQU9## The ratio of gL ' to gC ' is given by the expression ##EQU10## It is noted that this ratio is independent of DC control voltage v'. Therefore, gain control network 442 of FIG. 4 also allows for the adjustment of contrast while maintaining constant saturation.
It is noted that if A were made equal to 1, the arrangement gain control unit 442 would be suitable to control the gains of chrominance and luminance amplifiers having the characteristics shown in FIG. 2.
In FIG. 5, there is shown an amplifier suitable for use as luminance amplifier 130 of FIG. 1. The amplifier includes a differential amplifier comprising NPN transistors 532 and 534. The commonly coupled emitters of transistors 532 and 534 are coupled to the collector of an NPN transistor 528. The emitter of transistor 528 is coupled via a resistor 530 to ground. The collector of transistor 532 and the collector of transistor 534, via load resistor 536, is coupled to a bias voltage provided by bias supply 546, illustrated as a series connection of batteries. The bases of transistors 532 and 534 are respectively coupled to a lower bias voltage through resistors 533 and 535 respectively.
An input signal, such as, for example, the output signal provided by first luminance processing circuit 129 of FIG. 1 is coupled to the base of transistor 532 via terminal 542. The output signal of the amplifier is developed at the collector of transistor 534 and coupled to output terminal 544.
A DC control voltage, such as vL provided by gain control unit 142 of FIG. 1, is coupled to the base of an NPN transistor 514, arranged as an emitter-follower, via terminal 512. The collector of transistor 514 is coupled to bias supply 546. The emitter o
f transistor 514 is coupled to ground through the series connection of resistor 516, a diode connected transistor 518 and resistor 520.The anode of diode 520 is coupled to the base of an NPN transistor 538. The collector of transistor 538 is coupled to the collector of transistor 534 while its emitter is coupled to ground through resistor 540. Transistor 538, resistor 540, diode 518 and resistor 520 are arranged in a current mirror configuration.
The emitter of transistor 514 is coupled to the base of a PNP transistor 522. The emitter of transistor 522 is coupled to bias supply 546 while its collector is coupled to the base of transistor 528 and to ground through the series connection of a diode connected transistor 524 and resistor 526. Transistor 528, resistor 530, diode 524 and resistor 526 are arranged in a current mirror configuration
In operation, the DC control voltage coupled to terminal 512 is coupled in inverted fashion to the anode of diode 524 by transistor 522. As a result, current directly related to the voltage developed at the anode of diode 524 flows through diode 524 and resistor 526. Due to the operation of the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530, a similar current flows through the emitter circuit of transistor 528. The gain of the differential amplifier comprising transistors 532 and 534 is directly related to this current flowing in the emitter circuit of transistor 528, and therefore is inversely related to the DC control voltage at terminal 512. The gain versus DC control voltage characteristics of the differential is similar to gL shown in FIG. 2.
Further, a current is developed through the series connection of resistor 516, diode 518 and resistor 520 in direct relationship to the DC control coupled to terminal 512. A similar current is developed through resistor 540 due to the operation of the current mirror comprising diode 518, resistor 520, transistor 538 and resistor 540. This current is of the opposite sense to that provided by the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530 and is coupled to the collector of transistor 534 so that the DC voltage at output terminal 544 does not substantially vary with the DC control voltage.
In FIG. 6, ther
e is shown an amplifier suitable for use as chroma amplifier 120 of FIG. 1. The amplifier shown in FIG. 6 is of the type described in U.S. patent application Ser. No. 530,405 entitled "Controllable Gain Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974.The amplifier comprises a differential amplifier including NPN transistors 624 and 625 having their bases coupled to terminal 603 via a resistor 626. Chrominance signals, provided by a source of chrominance signals such as chrominance processing unit 120 of FIG. 1, are coupled to terminal 603. The current conduction paths between the collectors and emitters of transistors 624 and 625 are respectively coupled to ground via resistors 628, 629 and 630.
A current splitter circuit comprising an NPN transistor 632 and a diode 634 is coupled to the collector of transistor 624. Diode 634 and the base-emitter junction of transistor 632 are poled in the same direction with respect to the flow of collector current in transistor 624. It desirable that conduction characteristics of transistor 632 and diode 635 be substantially matched. Similarly, the collector of transistor 625 is coupled to a second current splitter comprising a transistor 633 and a diode 635.
An output load circuit comprising series connected resistors 636 and 638 is coupled between the collector of transistor 632 and a source of operating voltage provided by bias supply 610. Amplified chrominance signals are provided at output terminal 640 for coupling, for example, to a chroma demodulator such as chroma demodulator 124 of FIG. 1. Similarly, series connected load resistors 637 and 639 are coupled between the collector of transistor 633 and bias supply 610. An output terminal 641 at the junction of resistors 637 ad 639 provides oppositely phased chrominance signals to those provided at terminal 640. The gain associated with the cascode combination of transistors 624 and 632 is controlled in response to a DC control voltage, such as, for example, vC provided by gain control unit 142 of FIG. 1, coupled to the base of an NPN transistor 646 via terminal 602. Direct control current is supplied from the emitter of transistor 646 to diode 634 and 635 via a se
Bias voltages and currents are supplied to the amplifier arrangement by bias supply 610, illustrated as a series connection of batterys. A voltage B+ is coupled to the collector of transistor 646. A lower bias voltage is coupled to the load circuits of transistors 632 and 633. The bases of transistors 632 and 633 are coupled in common to a still lower bias voltage. The bases of transistors 624 and 625 are coupled to a still lower bias voltage via substantially equal in value resistors 658 and 659. A resistor 694 is coupled from the common junction of resistors 658 and 659 to ground.
Transistor 646 will conduct when the DC control voltage approaches the bias voltage supplied to the bases of transistors 632 and 633 of the current splitters. By selection of the circuit parameters, diodes 634 and 635 may be arranged to operate in a range between cut off to the conduction of all of the quiescent operating current supplied via resistor 630, thereby cutting off transistors 632 and 633 to provide no output signals at terminals 640 and 641.
At a DC control voltage intermediate to that corresponding to cut off of transistors 632 and 633 on the one hand and cut off of diodes 634 and 635 on the other hand, the voltage gain of the illustrated amplifier will vary in a substantially linear manner with the DC control voltage.
It is noted that although the characteristics shown in FIGS. 2 and 3 were reversed S-shaped characteristics, the characteristics could have other shapes including linear portions. For example, the characteristics could be substantially linear. Furthermore, with reference to FIG. 3, although gC ' was shown as having a linear portion that had a cut off control voltage lower than the cut off control voltage of the linear portion of gL ', the cut off control voltage of the linear portion of gC ' could be greater than the cut off voltage for the linear region of gL '. In addition, the gain control units and associate amplifiers could be arranged to utilize voltages opposite in polarity to those shown. These and other modifications are intended to be within the scope of the invention.
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Fair people are getting fair reply. Spam and useless crap and filthy comments / scrapers / observations goes all directly to My Private HELL without even appearing in public !!!
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Resisting the tide of post-modernity may be difficult, but I will attempt it anyway.
Your choice.........Live or DIE.
That indeed is where your liberty lies.
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