GRUNDIG SUPER COLOR 8800 CHASSIS 29301-114.41 UNITS VIEW.

- Abstimm-Anzeige-BST / Tuning Search OSD Bar Unit: 29301-059.01

- RGB Baustein / RGB Matrix : 29301-046.01 with TCA660 TBA530 (PHILIPS)

- Station-Memory / Tuning Search - Program Memory: 29301-045.01 with
TMS3748 + SN16965 + SN16966 + TP4398N + TP4398N + TP4398N

- TP BST / Remote control decoder: 29301-47.01 with MC6527 (Motorola)

- NF Baustein / Audio Amplifier: 29301-004.01 with TBA800

- Horizontal-Baustein / Line Osc + Synch : 29301-008.02 with TBA920

- Sicherung Bst / Safety Unit 29301-410.01

- OW Dioden Baustein / E/W Correction diode Mod. Unit: 29301-041.01

- Regelbaustein / regulator unit: 20301-035.01



THE TBA800, TBA810 AUDIO integrated circuits:

AUDIO integrated circuits are being increasingly used in television chassis and certainly represent the simplest approach to improving the audio side of a TV set. A number of such i.c.s have appeared during the 70's.

Here describes the use of two fairly recent ones, the SGS-ATES TBA800 and TBA8I0S. Both devices can provide reasonably high outputs into a suitable loudspeaker-the TBA800 will give up to 5W and the TBA810S up to 7W.
The main difference between them being that the TBA800 is a somewhat higher voltage, lower current device. The TBA800 is used in the current Grundig and ASA 110° colour chassis while the Finlux 110' colour chassis uses a TBA810. In each of these chassis the audio i.c. is driven from a TBA120 intercarrier sound i.c. The TBA800 and TBA810S can also be used as the field output stage in 110' monochrome chassis with c.r.t.s of up to l7in. and as the field driver stage in larger screen monochrome sets.
The TBA800 is designed to provide up to 5W into a 16 Ohm load when operated from a 24V supply. It is encapsulated in the type cf quad -in -line case shown in Fig. I: the tabs at the centre are to assist in cooling the device and must be earthed. The TBA800 can be operated from power supply voltages up to the absolute maximum permissible value of 30V. It is best to regard 24V as being the upper limit however in order to provide an adequate safety margin and prevent possible damage during voltage surges. The minimum power supply voltage recommended by the manufacturers is 5V, but the power output is then less than 0-5W. The quiescent current taken by the TBA800 is typically 9mA from a 24V supply-no device of this type should draw more than 20mA. When an input signal is applied the current increases considerably- up to about 1.5A at full power. Two circuits for use with the TBA800 are shown in Figs. 2 and 3 and give comparable performance. The circuit shown in Fig. 2 is somewhat simpler but that
shown in Fig. 3 enables one side of the loudspeaker to be connected to chassis. The input resistance of the TBA800 is quite high (typically 5 MOhm) but a resistor must be connected between the input pin 8 and chassis otherwise the out- put stage will not operate with the correct bias. In the circuits shown the volume control VR1 provides this function: the bias current that flows through it is typically 1 microA (maximum 5 microA). The average voltage at the output pin 12 is half the supply potential. The loudspeaker must be capacitively coupled therefore and the low frequency response will be worse as this capacitor is decreased in value. The output coupling capacitor C4 in Fig. 2 also provides the bootstrap connection to pin 4. In Fig. 3 an additional capacitor (C9) is required for this purpose.
In both circuits the value of R1 controls the amount of feedback and thus the gain. The output signal is fed back to pin 6 via an internal 7 kOhm resistor. If R1 is reduced in value the gain will increase but the frequency response will be affected and the distortion will rise. With the component values shown the voltage gain of both circuits is typically 140 (43dB) which is quite adequate for most audio applications. R3 in Fig. 3 is necessary only if the power supply voltage is fairly low (less than about 14V).
C2 smooths the power supply input and C1 is connected between pin 1 and chassis to provide r.f. decoupling and help prevent instability. If mains hum is present on the supply line with the circuit shown in Fig. 3 capacitor C8 should be included between pin 7 and chassis. The circuits shown have a level frequency response (within ±3dB) between about 40Hz and 20kHz. If you wish to reduce the upper 3dB level to about 8kHz C5 can be increased to about 560pF. The total harmonic distortion provided by these circuits remains fairly constant at about 0.5% until the power output reaches 3W: it then rises rapidly with power level as shown in Fig. 4.
The TBA800 can be operated from a 13V supply to feed up to 2.5W into an 80 load or from a 17V supply to feed the same power into a 160 load without an additional heatsink. If more output power is required the cooling tabs must be connected to a heatsink. Two methods of mounting the TBA800 are shown in Figs. 5 and 6. In Fig. 5 the device is inserted into a circuit board and a heatsink is soldered to the same points as the tabs: this has the disadvantage that the heatsink extends above the board though on the other hand the whole board can be used for the construction of the circuit. In Fig. 6 the tabs are soldered directly to a suitable area of copper on the board: this method has the disadvantage that about two square inches of the board are not available for component mounting. It is generally best to make soldered connections to the pins of the device since this ensures good heat dissipation with minimum unwanted feedback. Observe the usual heat precautions when soldering. The pins can however be carefully bent so that they will fit into a 16 -pin dual -in -line socket.
The TBA810S has the same type of encapsulation as the TBA800 and the connections are also as shown in Fig. 1 except that there is no internal connection to pin 3. An alternative version, the TBA810AS, has two horizontal tabs with a hole in each (see Fig. 7) so that a heatsink can be bolted on. Some readers may find it easier to bolt a heatsink to a TBA810AS than to solder the TBA810S tabs. TBA810 devices can provide 7W of audio power to a 40 loudspeaker when operated from a I6V supply. Fig. 8 shows the change in maximum output power with different supply voltages. As a 4.5W output can be obtained with a 12V supply the TBA810 is much more suitable than the TBA800 for use with battery operated equipment. The TBA810 can provide output currents up to 2.5A.
Two circuits for use with TBA810 devices are shown in Figs. 9 and 10: they are very similar to the circuits shown in Figs. 2 and 3 though some of the capacitor values are larger because of the lower output impedance. The two circuits have comparable performance but that shown in Fig. 10 gives somewhat better results at low supply voltages (down to 4V). In either circuit R2 may be replaced with a 100k0 volume control. The bias current flowing in the pin 8 circuit is typically
0-4 microA and the input resistance 5M 0 (the value of R2 must be much less however to ensure correct bias.
 The gain decreases as the value of R1 is increased for the same reason as with the TBA800. The values of R1, C3 and C7 affect the high -frequency response. With the values shown the response is level within ±3dB from about 40Hz to nearly 20kHz. Fig. 11 shows values of C3 plotted against R1 where the frequency is 3dB down at 10kHz and 20kHz and C7 is five times C3. The output distortion with these circuits is about 0.3% for outputs up to 3W rising to about 1% at 4W, 3% at 5W and 9% at 6W with a 14.4V supply voltage. The voltage gain is typically 70 times (37dB). Although this value is half that obtained with the TBA800 the input voltage required to produce a given output power is about the same for both types. This is because a smaller output voltage is required to drive a 40 load at a certain power level than is required to drive a 160 load.

The TBA810S may be mounted in the same way as the TBA800. One way of mounting the TBA810AS is shown in Fig. 12. It is simpler however to bolt flat heatsinks to the tabs.
Devices of this type will be destroyed within a fraction of a second if the power supply is accidentally con- nected with reversed polarity. When experimenting therefore it is wise to include a diode in the positive power supply line to prevent any appreciable reverse current flowing in the event of incorrect power supply connection. The diode can be removed once the circuit has been finalised. The TBA800 is likely to be destroyed if the output is accidentally shorted to chassis. The TBA810S and TBA810AS however are protected from damage in the event of such a short-circuit even if this remains for a long time (but note that the earlier TBA8I0 and  TBA810A versions did not contain internal circuitry to provide this protection). The TBA800 is not protected against overheating but the TBA810S and TBA810AS incorporate a thermal shutdown circuit.
For this reason the heat- sinks used with the TBA810S and TBA810AS can have a smaller safety factor than those used with the TBA800. If the silicon chip in a TBA810S or TBA810AS becomes too hot the output power is temporarily reduced by the internal thermal shutdown circuit. As with all high -gain amplifiers great care should be taken to keep the input and output circuits well separated otherwise oscillation could occur. The de- coupling capacitors should be soldered close to the i.c. -especially the 0 1pF decoupling capacitor in the supply line (this should be close to pin I).
Field Output Circuit:

 Fig. 13 shows a suggested field output stage for monochrome receivers with 12-17in. 110° c.r.t.s using the TBA81OS. For safe working up to 50°C ambient temperature each tab of the device must be soldered to a square inch of copper on the board. The peak -to - peak scanning current is 1.5A, the power delivered to the scan coils 0.47W, power disspipation in the TBA810S 1 8W, scan signal amplitude 4.1V, flyback amplitude 5V and the maximum peak -to -peak current available in the coils 1.75A



TBA920 line oscillator combination
DESCRIPTION
The line oscillator combination TBA920 is a monolithic
integrated circuit intended for the horizontal deflection of the black and white
and colour TV sets
picture tube.

FEATURES:
SYNC-PULSE SEPARATION
OPTIONAL NOISE INVERSION
GENERATION OF A LINE FREQUENCY VOL-
TAGE BY MEANS OF AN OSCILLATOR
PHASE COMPARISON BETWEEN SYNC-
PULSE AND THE OSCILLATOR WAVEFORM
PHASE COMPARISON BETWEEN THE OS-
CILLATOR WAVEFORM AND THE MIDDLE OF
THE LINE FLY-BACK PULSE
AUTOMATIC SWITCHING OF THE VARIABLE
TRANSCONDUCTANCE AND THE VARIABLE
TIME CONSTANT TO ACHIEVE NOISE SUP-
PRESSION AND, BY SWITCHING OFF, POS-
SIBILITY OF TAPE-VIDEO-REGISTERED RE-
PRODUCTION
SHAPING AND AMPLIFICATION OF THE OS-
CILLATOR WAVEFORM TO OBTAIN PULSES
FOR THE CONTROL OF DRIVING STAGES IN
HORIZONTAL, DEFLECTION CIRCUITS
USING EITHER TRANSISTORS OR THYRISTORS.

TDA2521 synchronous demodulator for PAL

GENERAL DESCRIPTION
The TDA2521 is a monolithic integrated circuit designed as a synchronous demodulator for PAL color television receivers. It includes an 8.8 MHz oscillator and divider, to generate two 4.4 MHz reference signals, and provides color difference output.
The TDA2521 is intended to interface directly with the TDA251O with a minimum of external components and is constructed on a single silicon chip using the Fairchild Planar
epitaxial process.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage 14 V
Internal Power Dissipation 600 mW ORDER INFQRMATIQN
Operating Temperature Range —2O°C to +6O°C TYPE PART NO.
Storage Temperature Range —55°C to +125°C 2521 TDA2521
Pin Temperature iSo|dering 10 si 260°C

Planar is a patented Fairchild process













TDA2510 CHROMINANCE COMBINATION

GENERAL DESCRIPTION —
The TDA2510 is a monolithic integrated circuit designed for the function of a color television receiver. It Is designed to Interface directly with the TDA2521, using a minimum number of external components.
TDA251O is constructed on a single silicon chip using the Fairchild Planar‘ epitaxial process.

ABSOLUTE MAXIMUM RATINGS

supply Voltage 15 V
Collector voltage of chroma output transistor (pin 7) 20 V
(PD I 100 mW max)
Collector current of chroma output transistor (pin 7) 20 mA
Collector current of color killer output transistor (pin 11) 10 mA
Power dissipation 500 mW
Operating temperature range —25°C 10 +6O°
Storage temperature range *55°C to +12!-3°C
THE  Philips TBA SERIES

 The TBA series of i.c.s developed by Philips for use in TV receivers comprises the TBA500Q, TBA510Q, TBA520Q, TBA530Q, TBA540Q, TBA550Q, TBA560Q, TBA750Q and TBA990Q, the Q signifying that the lead out pins are in zig-zag form as illustrated in other posts here at  Obsolete Technology Tellye !
 The operations the various i.c.s in this series perform are as follows:
 TBA500Q: Luminance Combination. Luminance amplifier for colour receivers incorporating luminance delay line matching stages, gated black level clamp and a d.c. contrast control which maintains a constant black level over its range of operation. A c.r.t. beam limiter facility is incorporated, first reducing the picture contrast and then the brightness. Line and field flyback blanking can also be applied.
 TBA510Q: Chrominance Combination. Chrominance amplifier for colour receivers incorporating a gain  controlled stage, a d.c. control for saturation which can be ganged to the receiver's contrast control, burst gating and blanking, a colour killer, and burst output and PAL delay line driver stages.
 TBA520Q: Chrominance Demodulator. Incorporates U and V synchronous demodulators, G-Y matrix and PAL V switch. This type will be superseded by
 the TBA990Q (development of which was nearing completion in 1972) listed later.
 TBA530Q: RGB Matrix. Luminance and colour difference signal matrix incorporating preamplifiers.
 TBA540Q: Reference Combination. Decoder reference oscillator (with external crystal) and a.p.c. loop. Also provides a.c.c., colour killer and ident outputs. TBA550Q: Video signal processor for colour or monochrome receivers. This i.c. is the successor to the TAA700. It is very similar electrically to the TAA700. TBA560Q: Luminance and Chrominance Combination. Provides luminance and chrominance signal channels for a colour receiver. Although not equivalent to the TBA500Q and TBA510Q it performs similar functions to those i.c.s.
 TBA750Q: Intercarrier Sound Channel. Incorporates five stage intercarrier sound limiter/amplifier plus quadrature detector and audio preamplifier. External
 TBA990Q: Chrominance Demodulator. Incorporates U and V synchronous demodulators, G -Y matrix and PAL V switch. This is at the time  in the final stages of development and was been available from March 1972 onwards. As I have given information previously on the TBA550Q and TBA750Q we  may concentrate in this and the concluding post in the series on the colour receiver i.c.s. such as multistandard sets or bistandard color decoders here at  Obsolete Technology Tellye !

 Fig. 1 shows in block diagram form their application for luminance and chrominance signal processing. We will look first at the TBA520Q and TBA530Q which are in use for example in the Philips G8 single standard colour chassis.

TBA530Q RGB Matrix Preamplifier:
The internal circuitry of this i.c. is shown in Fig. 2 while Fig. 3 shows the immediate external connections as used in the Philips G8 chassis. The chip layout is designed to ensure tight thermal coupling between all transistors to minimise thermal drift between channels and each channel has an identical layout to the others to ensure equal frequency response characteristics. The colour -difference signals are fed in at pins 2, 3 and 4 and the luminance input is at pin 5. Trl and Tr2 form the matrix in each channel, driving the differential amplifiers Tr3, Tr4, Tr5. The operating conditions are set by Tr5 and Tr7, using an external current -determining resistor connected to pin 7. Pin 6 is the chassis connection and pin 8 the 12V supply line connection (maximum voltage permitted 13.2V, approximate current consumption 30mA). External load resistors are connected to pins 1, 14 and 11 from a 200V line and the outputs are taken from pins 16, 13 and 10. The output pins are internally connected to the load resistor pins via Tr6 which provides a zener-type junction giving a level shift appropriate for driving the bases of the external output transistors directly. External l0kpF capacitors are required between the output and load resistor pins to bypass these zener junctions at h.f. Feedback from the external output stages is fed in at pins 15, 12 and 9. A common supply line should be used for this and any other i.c.s in the series used in the decoder, to ensure that any changes in the black level caused by variations in the supply voltage occur in a predictable way : the stability of the supply should be not worse than ±3% due to operational variations to limit changes in picture black level during receiver operation. To reduce the possibility of patterning on the picture due to radiation of the harmonics of the demodulation process the leads carrying the drive signals to the tube should be kept as short as possible : resistors (typically 1.51J) connected in series with the leads and mounted close to the collectors of the out- put transistors provide useful additional filtering of these harmonics.






   
TBA520Q Chrominance Demodulator:
In addition to U and V balanced synchronous detectors this i.c. incorporates a PAL switch which inverts on alternate lines the V reference signal fed to the V synchronous detector. The PAL switch is controlled by an integrated flip-flop circuit which is driven by line frequency pulses and is under the control of an ident input to synchronise the V switching. Outputs from the U and V demodulators are matrixed within the i.c. to obtain the G-Y signal so that all three colour difference signals are available at pins 4, 5 and 7. The internal circuit of this i.c. is shown in Fig. 4 while Fig. 5 shows the immediate external circuitry as used in the Philips G8 chassis. The separated U and ±V chrominance signals from the PAL delay line/matrix circuit are fed in at pins 9 and 13 respectively. The U and V reference signals, in phase quadrature, are fed in at pins 8 and 2. Taking the U channel first we see that the U chrominance signal is fed to Tr18 base. This transistor with Tr19 forms a differential pair which drives the emitters of the transistors-Tr4, Try, Tr6 and Tr7-which comprise the U synchronous demodulator. The U reference signal is fed to Tr12 base, this transistor with Tr13 forming a further differential pair which drive the bases of the synchronous demodulator transistors. The B -Y signal is developed across R3 and appears at output pin 7. A similar arrangement is followed in the V channel except that here the V reference signal fed in at pin 2 to the base of Tr22 is routed to the V synchronous demodulator (Tr8-Tr11) via the PAL switch Tr14-Tr17. This switch is controlled by the integrated flip-flop (bistable) Tr24 and Tr25 (with diodes DI and D2). The bases of the transistors in the flip-flop circuit are driven by negative going line frequency pulses fed in at pins 14 and 15. As a result half line frequency antiphase squarewaves are developed across R13 and R14 and fed to the PAL switch via R57 and R58. The ident signal is fed into the base of Tr32 at pin 1. A positive -going input to pin 1 drives Tr32 on so that the base of Tr24 is shorted and the flip-flop rendered inactive until the positive input is removed. In the Philips circuit a 4V peak -to -peak 7.8kHz sinewave ident signal is fed in at pin 1 to synchronise the flip-flop. The squarewave signal is externally available at pin 3 from the emitter -follower Tr39 which requires an external load resistor. The R-Y signal developed across R9 is fed via R10 to output pin 4. The G-Y signal appears at the output of the matrix network R4, R5 and R6 and is fed via R7 to pin 5. The d.c. voltages applied to pins 11 and 12 establish the correct G -Y and R-Y signal levels relative to the B -Y signal. Pin 10 is internally connected and no external connection should be made to this pin. The U and V reference carrier inputs should be about IV p -p, via a d.c. blocking capacitor in each feed. These inputs must not be less than 0-5V. The flip-flop starts when the voltage at pin 1 is reduced The amplitudes of the pulses fed in at pins 14 and 15 below 0.4V : it should not be allowed to exceed -5V. to drive the flip-flop should be between 2.5 and 5V p-p.
For a colou bar signal a U input of approximately 360mV is required at pin 9 and a V input of approximately 500mV is required at pin 13. The supply is fed in at pin 6 and this also sets the d.c. level of the B-Y output signal. The maximum voltage allowed at this pin is 13.2V. In early versions of the Philips G8 chassis a TAA630 i.c. was used in place of the TBA520Q.

Philips TBA SERIES SINCE the last part in this series Philips have released details of a PAL -D decoder developed in their laboratories in which most of the circuitry has been integrated into four i.c.s a TBA560Q which undertakes the luminance and chrominance signal processing, a TBA540Q which provides the reference signal channel, a TBA990Q which provides synchronous demodulation of the colour -difference signals, G -Y signal matrixing and PAL V switching, and a TBA530Q which matrixes the colour -difference signals and the luminance signal to obtain the R, G and B signals which after amplification by single -transistor output stages drive the cathodes of the shadowmask tube.

The TBA540Q and TBA560Q and also the TBA500Q and TBA510Q which provide an alternative luminance and chrominance signal processing arrangement will be covered this time.
The internal circuits of the TBA530Q and TBA520Q (predecessor to the TBA990Q which shows how fast things are moving at present) were shown in Part 6 in order to give an idea of the type of circuitry used in these linear colour receiver i.c.s. The internal circuitry is not however of great importance to the user or service engineer: all we need to know about a particular i.c. are the functions it performs, the inputs and outputs it requires and provides and the external connections necessary. The i.c.s we shall deal with in this instalment are highly complex internally the TBA560Q for example contains some 67 integrated transistor elements alone. This time therefore we shall just show the immediate external circuitry in conjunction with a block diagram to indicate the functions performed within the i.c.

TBA540Q Reference Signal Channel:

A block diagram with external connections for this i.c. is shown in Fig. 1. In addition to providing the reference signal required for synchronous demodulation of the colour difference signals this i.c. incorporates automatic phase and amplitude control of the reference oscillator and a half line frequency synchronous demodulator which compares the phases and amplitudes of the burst ripple and the square waveform from the PAL V switch circuit in order to generate a.c.c., colour killer and ident outputs. The use of a synchronous demodulator for these functions provides a high standard of noise immunity in the decoder. The internal reference oscillator operates in conjunction with an external 4.43MHz crystal connected between pins 1 and 15. The nominal load capacitance of the crystal is 20pF. The reference oscillator output, in correct phase for feeding to the V signal synchronous demodulator, is taken from pin 4 at a nominal amplitude of 1.5V peak -to -peak. This is a low -impedance output and no d.c. load to earth is required here. The bifilar inductor Ll provides the antiphase signal necessary for push-pull reference signal drive to the burst detector circuit, the antiphase input being at pin 6. The U subcarrier is obtained from the junction of a 900 phase shift network (R1, C1) connected across Ll. The oscillator is controlled by the output at pin 2. This pin is fed internally with a sinewave derived from the reference signal and controlled in amplitude by the internal reactance control circuit. The phase of the feedback from pin 2 to the crystal via C2 is such that the value of C2 is effectively increased. Pin 2 is held internally at a very low impedance. Thus the tuning of the crystal is automatically controlled by the amplitude of the feedback waveform and its influence on the effective value of C2. The burst signal is fed in at pin 5. A burst waveform amplitude of 1V peak -to -peak is required (the minimum threshold is 0.7V) and this is a.c. coupled. The a.p.c. loop phase detector (burst detector) loads and filter (R2, C4, C5 and C6) are connected to pins 13 and 14. A synchronously -generated a.c.c. potential is produced at pin 9. The voltage at this pin is set by R3 to 4V with zero burst input. The synchronous demodu- lator producing this output is fed with the burst signal and the PAL half line frequency squarewave which is a.c. coupled at pin 8 at 2.5V peak -to -peak. If the phase of the squarewave is correct the potential at pin 9 will fall and normal a.c.c. action will commence. If the phase of the squarewave is incorrect the voltage at pin 9 will rise, providing the ident action as this rise will make the PAL switch miss a count thereby correcting its phase. A colour -killer output is provided at pin 7 from an internal switching transistor. If the ident conditions are incorrect this transistor is saturated and the output at pin 7 is about 250mV. When the ident conditions are correct (voltage at pin 9 below 2.5V) the transistor is cut off providing a positive -going turn -on bias at pin 7. The network between pins 10 and 12 provides filtering and a.c.c. level (R3) setting. The control connected to pin 11 is set so that in conjunction with the rest of the decoder circuitry the level of the burst signal at pin 5 under a.c.c. control is correct. The positive d.c. supply required is applied to pin 3 and the chassis connection is pin 16.

TBA560Q Chroma-Luminance IC:

A block diagram with external connections for this i.c. is shown in Fig. 2. The i.c. incorporates the circuits required to process the luminance and chrominance signals, providing a luminance output for the RGB matrix and a chrominance output for the PAL delay line circuit.
The luminance input is a.c. coupled from the luminance delay line terminating resistor at pin 3. This pin also requires a d.c. bias current which is obtained via the 22kI resistor shown. The brightness control is connected to pin 6: variation from OV to 1 2V at this pin gives a variation in the black level of the luminance output at pin 5 of from OV to 3V, which is a greater range than is needed in practice. The contrast control is connected to pin 2 and the potential applied here controls the gain of both the luminance and the chrominance channels so that the two signals track together correctly. Picture tube beam current limiting can be applied at either pin 6 or pin 2 (by taking the earthy side of one of the controls to a beam limiter network). To maintain correct picture black level it is preferable to apply the beam limiting facility to reduce the contrast. A positive going pulse timed to coincide with the back porch period is fed in at pin 10 to provide burst gating and to operate the black -level clamp in the luminance channel: the black -level clamp requires a charge storage capacitor which is connected to pin 4. The luminance output is obtained from an internal emitter follower at pin 5, an external load resistor of not less than 2kS2 being required here. The output has a nominal black level of 1.6V and 1V black -to -white amplitude. The chrominance signal is applied in push-pull to pins 1 and 15. A.c.c. is applied at pin 14, a negative going potential giving a 26dB control range starting at 1V and giving maximum gain reduction at 200mV. The saturation control is connected to pin 13 and the colour -killer potential is also applied to this pin : the chrominance channel is muted when the voltage at this pin falls below IV. The chrominance output, at an amplitude of about 2V peak -to -peak, is obtained at pin 9: an external network is required which provides d.c. negative feedback in the chrominance channel via pin 12. The burst output, at about 1V peak -to -peak, is obtained at pin 7. A network connected to this pin also provides d.c. feedback to the chrominance input transformer (connected between pins 1 and 15) to give good d.c. stability. Line and field blanking pulses are fed in at pin 8 to the luminance and chrominance channels : these negative -going pulses should not exceed -5V in amplitude. The d.c. supply is applied to pin 11 and pin 16 is the chassis connection.

TBA500Q Luminance IC:

A block diagram with external connections for this i.c. is shown in Fig. 3. This i.c. provides a colour receiver luminance channel incorporating luminance delay -line matching stages, a black -level clamp and a d.c. contrast control which maintains a constant black level over its range of operation. A beam current limiting facility which first reduces picture ,contrast and then picture brightness is provided and line and field flyback blanking can be applied. A video input signal of 2V peak -to -peak with negative -going sync pulses is required at pin 2, a.c. coupled. A clamp potential obtained from pin 13 via a smoothing circuit is fed to pin 2 to regulate the black level of the signal at pin 2 to about 10-4V. The smoothing network for the black -level control potential should have a time -constant which is less than the time constant of the video signal coupling network. The 3V peak -to -peak composite video output with positive -going sync pulses obtained at pin 3 from an emitter -follower can be used as a source of chroma signal: in Fig. 3 it is used as a source of sync pulses for the black -level clamp, fed in at pin 15. This pin requires positive -going sync pulses of 2V amplitude or greater for sync -cancelling the black -level clamp. The other input to the clamp consists of negative going back porch pulses fed in at pin 1 to operate the clamp. The timing of these pulses is not critical provided the pulse does not encroach on the sync pulse period and that it dwells for at least Zus on any part of the back porch-clamp pulse overlap into the picture line period is unimportant. A low-pass filter capacitor for the clamp is connected at pin 14 to prevent the operation of the clamp being affected by the bursts or h.f. noise. The contrast control is connected to pin 5 and is linked to the saturation control so that the two track together. A variation of from 2 to 4V at pin 5 gives a control range of at least 40dB, the relationship between the video at pin 4 and the potential at pin 5 being linear. An output to drive the luminance delay line is provided at pin 4. This is a low -impedance source and a luminance delay line with a characteristic impedance of 1-2.7161 can be used. The delayed luminance signal is fed back into the i.c. at pin 8. Line and field flyback banking pulses and the brightness control are also connected to this pin. The gain of the luminance channel is determined by the value of the resistor connected to pin 9. The luminance output is taken from an emitter -follower at pin 10, an external load resistor being required. The voltage output range available is from 0.7V to 5-5V. The potential of the black level of the output signal is normally set to 1.5V by appropriate setting of the potential at pin 8. A luminance signal output amplitude of 2.8V black to white at maximum contrast is produced : superimposed on this is the blanking waveform which remains of constant amplitude independently of the contrast and brightness control settings. A beam current limiting input is provided at pin 6. A rising positive potential at this pin will start to reduce the contrast at about 2V. Further increase in the voltage at this pin will continue to reduce the contrast until a threshold is reached, determined by the potential applied to pin 7, when the d.c. level of the video signal is reduced giving reduction in picture brightness. The d.c. supply is connected to pin 12 and pin 16 is the chassis connection.

TBA510Q Chrominance IC:

A block diagram with external connections for this i.c. is shown in Fig. 4. It provides a colour receiver chrominance signal processing channel with a variable gain a.c.c. chroma amplifier circuit, d.c. control of chroma saturation which can be ganged to the opera- tion of the contrast control, chroma blanking and burst gating, a burst output stage, colour -killer circuit and PAL delay line driver stage. The chroma signal is a.c. coupled to pin 4, the a.c.c. control potential being applied at pin 2. The non - signal side of the differential amplifier used for the a.c.c. system is taken to pin 3 where a decoupling capacitor should be connected. A resistor can be connected between pins 2 and 3 to reduce the control sensitivity of the a.c.c. system to any desired level. The saturation control is connected to pin 15, the d.c. control voltage range required here being 1.5-4-5V. For chrominance blanking a negative -going line flyback pulse of amplitude not greater than 5V is fed in at pin 14. A series network is connected to pin 6 to decouple the emitter of one of the amplifying stages in the i.c.: the value of the resistor in this network influences the gain of both the burst and the chroma channels in the i.c. The chrominance signal outputs are obtained at pin 8 (collector) to drive the chroma delay line and pin 9 (emitter) to feed the chrominance signal matrix (undelayed signal). A resistive path to earth is essen- tial at pin 9. The colour -killer turn -on bias is applied to pin 5 : colour is "on" at 2.3V, "off" at 1.9V. Chroma signal suppression when killed is greater than 50dB. The burst signal output is at pin 11 (collector) or 12 (emitter). If a low -impedance output is required pin 11 is connected direct to the 12V supply rail and the output is taken from pin 12. An external load of 2kn connected to chassis is required here. The burst gating pulse is fed in at pin 13, a negative -going pulse of not greater than 5V amplitude being required. Pins 7 and 10 are connected to an internal screen whose purpose is to prevent unwanted burst and chroma outputs : the pins must be linked together and taken via a direct path to earth. Pin 1 is the d.c.
supply pin and pin 16 the chassis connection.

A TBA510 as example  is used in the Grundig 1500/3010 series and also the YR 1972 Grundig colour chassis (5010 / 5050  series) introduced in the70's. Grundig continue in these models to favour colour -difference tube drive. The 5010 series uses a TBA510 together with a TAA630 colour demodulator i.c. in the chrominance section and a TBA970 luminance i.c. which drives a single BF458 luminance output transistor operated from a 280V rail. As this series has been appearing more and more i.c.s have come to be used in television receivers, both monochrome and colour, and more and more i.c.s designed for television set use have been announced. Some of these have been mentioned in recent argumentations here in this Web Museum. There seems little doubt that a major increase in the use of integrated circuits in television receivers is about to occur in the future. Fully integrated i.f. and vision detector sections are already in use (PHILIPS K9-K11) and this is the likely area, together with the decoder in colour sets, in which integration will most rapidly spread. Elsewhere integrated line and field oscillators using circuits without inductors have been developed and a field output stage in integrated form is now feasible. Line output stages consisting of hybrid i.c. and thick film circuits (PHILIPS K12) have been built and there is a programme of work directed to the integration of the r.f. tuner, using digital frequency synthesisers to provide local oscillator action controlled by signals from a remote point.

We seem to have reached the position where the only part of the set which does not attract the i.c. manufacturers is the picture tube itself !

TEXAS INSTRUMENTS Solid state television channel selection system:
GRUNDIG Tuning Memory / Suchlauf Abstimmung overview.HERE below the description of the technology of the Texas Instruments Incorporated Tuning system used in GRUNDIG Super Color television Tuning circuits (STATIONS SUCHLAUF / STATION MEMORY) , and discloses various embodiments of solid state television channel selection systems.

It's shown and explained the theory on which is based all the technology of the GRUNDIG SUPER COLOR 8800 CHASSIS 29301-114.41 SUCHLAUF BAUSTEIN / STATION MEMORY 29301-045.21 (SEARCH UNIT) BASED AROUND TEXAS INSTRUMENTS CHIPSET and fitted in GRUNDIG SUPER COLOR CHASSIS DESIGN IN THE 70's.


An automatic TV tuner circuit responsive to a tuning voltage for tuning over a desired frequency reception range. The tuning voltage is generated by a staircase voltage generator. A discriminator produces an output signal having a nominal value when the receiver is tuned to a transmitted broadcast frequency and at a discriminator output having a predetermined difference from the nominal value, a sequence control circuit halts the operation of the staircase generator and regulates the tuning voltage in a continuous manner under control of the discriminator output signal to complete the tuning process.
1. A circuit for generating a tuning voltage for tuning a signal receiver having an input stage tunable over a desired reception frequency range by means of the tuning voltage and which includes discriminator means for producing an output signal having a selected value when the receiver is tuned to a nominal frequency; said circuit including staircase voltage generator means for generating a stepwise increasing tuning voltage for application to said input stage; frequency control circuit means operably connectable to said staircase voltage generator means for adjusting the output voltage of said staircase voltage generator in dependence on said discriminator means output signal in a sense to tune said receiver to said nominal frequency; sequence control circuit means for stopping stepping operation of said staircase voltage generator means when the value of said discriminator output signal has a predetermined difference from said selected value and for effecting said operable connection of said frequency control circuit means when stepping operation of said staircase voltage generator means has been stopped by said sequence control circuit means; and wherein said frequency control circuit means has a control range at least sufficiently wide to include tuning frequencies attained in successive steps of said staircase voltage.

2. A circuit according to claim 1, wherein said staircase voltage generator means includes scanning counter means for continuously sweeping its counting cycle, information counter means fed with stepping pulses by said sequence control circuit means, and comparator means for comparing the counts of said scanning and information counter means to produce an output voltage as long as the count of said scanning counter means is lower than the count of said information counter means, said output pulses having a duration which increases with the count of the information counter means and which remains constant when stepping operation of said staircase voltage generator means has been stopped; and means connecting the output of said comparator means to the input of integrator means for integrating the output voltage of said comparator means to produce said stepwise increasing tuning voltage, said tuning voltage having a level which depends on the existing count of the information counter when stepping operation of said staircase voltage generator means has been stopped.

3. A circuit according to claim 2, further including storage means for storing the count of said information counter means when said staircase voltage generator has been stopped by said sequence control circuit means and for subsequent re-entry of said count into said information counter.

4. In a television broadcast receiver including means responsive to received video signals to produce sync pulses and line flyback pulses, an input stage tunable over a desired reception frequency range by a tuning voltage applied to a tuning input of said input stage; staircase voltage generator means for generating a stepwise increasing voltage for application to said tuning input; and discriminator means for producing an output signal, said output signal having a predetermined value when said receiver is tuned to a nominal broadcast frequency, the improvement characterized by:
frequency control means connected to receive said discriminator output signal and responsive to enablement for continuously adjusting the output voltage from said staircase voltage generator, said frequency control circuit means having a control range sufficiently wide to include at least the tuning frequencies attained in successive steps of said staircase voltage;
sequence control circuit means including control logic means for stopping stepping operation of said staircase voltage generator means in response to a selected difference of said discriminator output signal from said predetermined value and, when enabled, for enabling said frequency control circuit means until said discriminator output signal has said predetermined value;
coincidence circuit means having an output connected to said control logic means and responsive to coincidence between said sync pulses and said line flyback pulses to effect said enablement of said control logic means, and responsive to non-coincidence between said sync pulses and said line flyback pulses to cause said control logic means to restart operation of said staircase voltage generator means.


5. A circuit according to claim 4, wherein said coincidence circuit includes a capacitor chargeable to a predetermined value to indicate presence of said coincidence, and a transistor circuit responsive to coincidence of said sync and line flyback pulses to pass charging current to said capacitor.

6. A circuit according to claim 4, wherein said coincidence circuit includes a capacitor chargeable to a predetermined value to indicate presence of said coincidence, a first transistor for passing charging current to said capacitor, a second transistor shunting a control input of said first transistor and switchable to an off condition in the presence of a sync pulse, and a third transistor shunting said control input of said first transistor and switchable to an off condition in the presence of a line flyback pulse.

7. A circuit according to claim 6, including discharge transistor means connected in parallel with said charging capacitor for switching to a conductive state in response to presence of a sync pulse in the absence of a line flyback pulse.

8. In a television broadcast receiver including means responsive to received video signals to produce sync pulses and line flyback pulses, an input stage tunable over at least one desired reception frequency range by a tuning voltage applied to a tuning input of said input stage;
staircase voltage generator means for generating a stepwise increasing voltage for application to said tuning input for coarse tuning;
discriminator means responsive to received signals for producing an output signal, said output signal having a selected value when said receiver is tuned to a nominal broadcast frequency;
frequency control means responsive to enablement for adjusting the output voltage from said staircase voltage generator in a continuous manner for fine tuning until said discriminator output voltage has said predetermined value, said frequency control means having a control range sufficently wide to include at least the tuning frequencies attained in successive steps of said staircase voltage;
gating means having an output connected for enabling said frequency control means, said gating means including a switch input and an enabling input;
sequence control circuit means including control logic means having a first output connected to apply stepping pulses to said staircase voltage generator and a second output connected to the switch input of said gating means;
first trigger means responsive to a discriminator output voltage having a predetermined difference from said selected value to input said control logic means for disabling said first output;
second trigger means for inputting said control logic means to actuate said switching input of said gating means, and to confirm disablement of said first output;
coincidence circuit means responsive to coincidence of said sync pulses and said line flyback pulses to trigger said second trigger means and to actuate said enabling input of said gating means.


9. A circuit according to claim 8, wherein said staircase voltage generator means includes scanning counter means for continuously sweeping its counting cycle, information counter means, the first output of said control logic means connected for stepping said information counter, compartor means for comparing the counts of said scanning and information counter means to produce an output voltage as long as the count of said scanning counter means is lower than the count of said information counter means, said output pulses having a duration which increases with the count of the information counter means and which remains constant when stepping operation of said staircase voltage generator means has been stopped, and means connecting the output of said comparator means to the input of integrator means for integrating the output voltage of said comparator means to produce said stepwise increasing tuning voltage, said tuning voltage having a level which depends on the existing count of the information counter when stepping operation of said staircase voltage generator means has been stopped; and storage means for storing the count of said information counter means when said staircase voltage generator has been stopped by said sequence control circuit means and for subsequent re-entry of said count into said information counter.

10. A circuit according to claim 8, wherein said coincidence circuit includes a capacitor chargeable to a predetermined value to indicate presence of said coincidence, a first transistor for passing charging current to said capacitor, a second transistor shunting a control input of said first transistor and switchable to an off condition for the duration of a sync pulse, a third transistor shunting said control input of said first transistor and switchable to an off condition for the duration of a line flyback pulse, and discharge transistor means connected in parallel with said charging capacitor for switching to a conductive state in response to presence of a sync pulse in the absence of a line flyback pulse.

11. A circuit according to claim 8, wherein said frequency control means comprises an AFC circuit of said receiver.

Description:

The invention relates to a circuit arrangement including a staircase voltage generator, for generating a tuning voltage for tuning a broadcast receiver whose input stage can be tuned through by means of the tuning voltage over a desired reception frequency range and which contains a discriminator whose output signal has a given nominal value when the receiver is tuned to a nominal frequency.

In such a circuit arrangement, it has been suggested to reduce the rate of variation of the output voltage of the staircase voltage generator if the output voltage of the discriminator indicates that the setting of the input stage is approaching tuning to a transmitter radiating a nominal frequency. The rate of variation is finally reduced to zero when the input stage is tuned exactly to the transmitter frequency. As can be readily seen, the steps of the staircase voltage must be very low to ensure exact tuning to any given nominal frequency. Voltage steps that are too high could have the result that the receiver is tuned to a frequency which is still below the nominal frequency, while it becomes tuned to too high a frequency in the next following step. Generating the finely tuned staircase voltage requires relatively high circuit complexity, which is further increased by the fact that the speed at which the individual steps are traversed must be reduced when approaching the tuning to a transmitter radiating the nominal frequency.
The invention is concerned with a circuit arrangement of the indicated type such that the required circuit complexity, and thus the costs may be reduced.
In a preferred embodiment of the invention, a sequence control circuit stops the staircase voltage generator when the value of the output signal of the discriminator has a predetermined difference from the nominal value. A frequency control circuit triggered by the sequence control circuit when the staircase voltage generator is stopped, regulates the voltage produced by the stopped staircase generator in dependence on the discriminator output signal to a value tuning the receiver to the nominal frequency, the control range of the frequency control circuit being at least sufficiently wide that it includes the range between two tuning frequencies attained in successive steps of the staircase voltage.
In such a circuit arrangement embodying the invention, the operation of the staircase voltage generator is stopped when the discriminator output signal indicates the predetermined approach of the tuning to a transmitter radiating the nominal frequency. The tuning voltage generated in the stopped state of the staircase voltage generator can then be so varied by means of a frequency control circuit so that the receiver is finely tuned to the nominal frequency. The control range of the frequency control circuit is sufficiently wide that it includes the range between two tuning frequencies attained in successive steps of the staircase voltage.
The coarse tuning achieved by means of the circuit using the steps of the tuning voltage produced by the staircase voltage generator, and the subsequent fine tuning by means of the similarly acting frequency control circuit have the result that high circuit complexity is no longer required for tuning the receiver. Production costs of a circuit embodying the invention can therefore be reduced.
In an advantageous embodiment of the invention, the staircase voltage generator includes a scanning counter continuously passing through its counting cycle, and an information counter fed from the sequence control circuit with stepping pulses. A comparator compares the counts of the two counters and produces an output voltage as long as the count of the scanning counter is less than the reading of the scanning information counter. The output of the comparator is connected to the input of an integrator which integrates the output voltage of the comparator and and produces the tuning voltage at its output.
Furthermore the count of the information counter, attained when the staircase voltage generator is stopped by the sequence control circuit, can be stored and fed again into the information counter when needed. This has the result that the receiver, by feeding an information counter count stored during its search run into the information counter, can be tuned immediately to this transmitter, without requiring a further search run. This is of particular advantage if a receiver is tuned through in its first operation in a search run over a predetermined frequency range, so that the transmitters located in this range can be determined. The counts of the information counter attained in the reception of these transmitters can be stored, so that the receiver can be tuned subsequently to a desired transmitter by feeding the stored information into the information counter.
For tuning a television receiver, the sequence control circuit embodying the invention is preferably so designed that it enables the frequency control circuit, after the operation of the staircase voltage generator has been stopped, only when there is coincidence between the sync pulses of the received video signal and line flyback pulses of the and that it starts the operation staircase voltage generator again in the absence of coincidence. This ensures that the television receiver is fine-tuned only to true picture transmitters where there is coincidence between the sync pulses and the line flyback pulses.
In circuit arrangement embodying the invention, the coincidence circuit used to determine the coincidence between the sync pulses and the line flyback pulses advantageously may contain a charging transistor which is arranged in the charging circuit of a charging capacitor, and which is conductive only when a sync pulse and a line flyback pulse appear in the coincidence circuit, a predetermined voltage value on the charging capacitor indicating the presence of coincidence.
An embodiment of the invention will now be described by way of example and in greater detail to show how the invention may be put into effect, reference being made to the accompanying drawings, in which:
FIG. 1 shows a block circuit diagram of a circuit arrangement embodying the invention,
FIG. 2 shows a circuit diagram of the coincidence circuit shown in FIG. 1.
The circuit arrangement illustrated in FIG. 1 serves to tune a television receiver to a nominal transmission frequency. The input stage of this television receiver receives over antenna 2 the RF-signal. This input stage 1 includes a conventional discriminator 3 which produces a signal having a predetermined nominal value when the receiver is tuned to the nominal frequency.
The tuning voltage for input stage 1 is supplied by a staircase voltage generator 4. This staircase voltage generator 4 includes an oscillator 5 which generates continuous output-pulses and feeds them to the stepping input 6 of a scanning counter 7. The scanning counter 7 thus sweeps its counting cycle continuously.
Furthermore, the staircase voltage generator 4 contains an information counter 8 which is operated only when required, as will be described below, and which is supplied at its stepping input 9 with pulses whose recurrence frequency is lower than the output pulses of the oscillator 5.
The counts of the scanning counter 7 and of the information counter 8 can be compared with each other in a comparator 10. This comparator 10 is so designed that it produces an output voltage at its output 11 whenever the count of the scanning counter 7 is lower than that of the information counter 8. The output voltage of the comparator 10 is integrated by an integrator 12 and fed to the input 14 of input stage 1 for tuning purposes. The integrator 12 is so designed that the value of the voltage at its output 13 depends not only on the output voltage of the comparator 10, but also on a signal fed to an input 15.
The signal at input 15 influencing the output voltage of the integrator is supplied by a frequency control circuit 16, generally also called an AFC-circuit, which in known manner produces at its output 17 a control voltage which depends on the difference between the discriminator output voltage and a fixed reference voltage. The frequency control circuit 16 can be gated or made inoperative by a switching signal fed to a gate input 18.
The operating sequence of the circuit arrangement illustrated by FIG. 1 is controlled by a sequence control circuit 19. This sequence control circuit 19 receives at the input 20 line flyback pulses of the television receiver, and its input 21 receives sync pulses from the video amplifier. At the input 22 of the sequence control circuit 19 is applied the reference voltage which is also fed to the frequency control circuit 16. At the input 23 is applied the output voltage from the discriminator 3. The sequence control circuit 19 includes a coincidence circuit 24 which triggers a Schmitt-trigger 25 to produce a coincidence signal indicating coincidence between the sync pulses and the line flyback pulses. Another Schmitt trigger 26 produces an output signal when the discriminator output voltage has a predetermined difference from the reference voltage. The output signals of the two Schmitt triggers 25 and 26 are applied to the inputs 28 and 27 of a control logic 29. This control logic 29 is so designed that it feeds the pulses derived from the scanning counter 7, which are fed to its input 30 and whose recurrence frequency is lower than that of the pulses at the stepping input 6 of the scanning counter 7, over an output 31 to the stepping input 9 of the information counter 8 and interrupts the supply of pulses when a signal from Schmitt trigger 26 appears at input 27, and the coincidence signal of Schmitt trigger 25 indicates the presence of coincidence between the line flyback pulses and the sync pulses. The supply of pulses to the stepping input 9 of the counter 8 is resumed, however, if the presence of coincidence is not indicated within a period required for checking the coincidence, by producing the coincidence signal on Schmitt trigger 25 after the pulse supply has been interrupted. But if coincidence is indicated, the control logic 29 generates at output 32 a signal which has the effect that the switching signal is applied together with the coincidence signal over an AND-circuit 33 to the enable input 18 of the frequency control circuit 16.
The counter reading attained when the supply of stepping pulses is interrupted to the input 9 of the information counter 8 can be stored in a store 34. The storage position can be selected by means of addressing inputs A, B, C, and D. This store also permits feeding of a previously stored counter reading into the information counter 8. The transmission path for the exchange of information between the information counter 8 and the store 34 is indicated schematically by the line 35. The control signals for carrying out the exchange of information are supplied over the line 36 by the control logic 29.

The manner of operation of the circuit arrangement represented in FIG. 1 is as follows. The circuit arrangement is to be used to tune the television broadcast receiver to a frequency radiated from a television transmitter. Input stages of television receivers are initially set to a certain frequency range before actual tuning to the nominal frequency within the set range. To this end the circuit arrangement represented in FIG. 1 includes three trip switches 37, 38, and 39, which, when tripped, set the input stage to the VHF-I range, the VHF-III range and the UHF range respectively. Assuming that the desired nominal frequency to which the receiver is to be tuned is in the VHF-I range, trip switch 37 is actuated. This has the result that information characterizing this range is fed into the band store 40 which effects the switching of input stage 1 to the desired range. Together with the switching, a trigger signal is applied over line 42 from band store 40 to input 43 of control logic 29, so that the latter is put into operation.
As mentioned above, the control logic 29 receives at input 30 pulses which are derived from the continuously recirculating scanning counter 7 and whose repetition frequency is lower than the repetition frequency of the stepping pulses of this counter, which are supplied by oscillator 5. The pulses at input 30 of control logic 29 are fed to the stepping input 9 of information counter 8 from band store 40, after they have been triggered by means of the signal at input 43. The count of this information counter 8 is therefore increased in synchronism with the pulses at the stepping input 9.
The counts of the scanning counter 7 and of the information counter 8 are compared continuously with each other by the comparator 10. As long as the count of the scanning counter 7 is less than the count of the information counter 8, comparator 10 produces at its output 11 an output signal with a high voltage value. If the count of the scanning counter 7 is greater than that of the information counter 8, the output signal of comparator 10 assumes the voltage value zero.
In the comparison of the readings of the continuously recirculating scanning counter 7 with that of the information counter 8 running at a lower stepping frequency, pulses appear at output 11 of comparator 10 whose duration increases with an increase of the count of the information counter 8. If we assume, for example, that the count of the information counter 8 has a low value, then the time interval in which the count of the scanning counter 7 is less than that of the information counter 8 is short. For this short time, a signal with a high voltage value is given off at output 11 of comparator 10. If the information counter 8 has a higher count, it takes longer until identity between counts of the two counters is achieved and, thus, until the signal at the comparator output 11 assumes the voltage value 0. The longest time for the high voltage produced at output 11 of comparator 10 is when the information counter 8 has attained its highest reading. The pulses produced by comparator 10 thus increase in duration with increasing count of the information counter 8.
The output pulses of comparator 10 are integrated by integrator 12, so that the latter produces at output 13 a voltage rising in steps. This rising voltage arrives as tuning voltage at the input 14 of the input stage 1, which is tuned through in the range selected by means of trip switch 37.
When a transmitter is received in the course of the tuning, discriminator 3 produces in known manner an output voltage with an S-shaped characteristic whose deviation from a reference value serving as a nominal value indicates how accurately the input stage is tuned to the transmitter frequency being received. Exact tuning has been achieved when there is not deviation anymore.
The output voltage of discriminator 3 is fed to Schmitt trigger 26 in the sequence control circuit 19 to which a reference voltage is applied from input 22 and which produces a control pulse when the discriminator output voltage has a predetermined difference from the applied reference voltage, and thus from the nominal value. The control pulse from Schmitt trigger 26 is fed to input 27 of the control logic 29. The control logic 29 then interrupts the supply of stepping pulses to the stepping input 9 of the information counter 8.
In the coincidence circuit 24 of the sequence control circuit 19, the sync pulses and line flyback pulses are checked for coincidence. The coincidence of these pulses is a criterion that the transmitter received is a picture transmitter, as desired. If coincidence is found, Schmitt trigger 25 triggered by coincidence circuit 24 generates a coincidence signal which is fed to the input 28 of control logic 29 and to one input of the AND-circuit 33.
The control logic 29 has only temporarily interrupted the supply of stepping pulses to the information counter 8 during the reception of a control pulse at input 27, and interruption of this supply is confirmed only when the coincidence signal appears at the input 28 after a delay necessary to check the coincidence. The appearance of the control pulse at input 27 and the delayed appearance of the coincidence signal at input 28 have the effect that the information counter 8 is definitely stopped, and a switching signal is produced at output 32 of the control logic 29. The switching signal at outputs 32 and 36 then arrives at the second input of the AND-circuit 33, which is thus enabled, triggering the frequency control circuit 16 over the line 44 leading to the trigger input 18.
Stopping of the information counter 8 has the result that output pulses of equal pulse duration are produced at the output 11 of comparator 10 with each passage of the counting period of the information counter 8, so that the integrator 12 produces at the output 13 a tuning voltage level which depends on the existing count of the information counter 8. Following stoppage of the information counter 8, triggering of the frequency control circuit 16 permits the turning voltage at the output 13 of the integrator 12 to be varied.
The frequency control circuit 16 can be a conventional frequency control circuit which generates a frequency control voltage at output 17 based on the deviation of the output voltage of discriminator 3 from a reference voltage. This control voltage is fed to the integrator 12 at the input 15; it effects a variation of the tuning voltage produced, so that input stage 1 is finely tuned to the transmitter received.
The control range of the frequency control circuit 16 must be so dimensioned that it comprises the range between two tuning frequencies attained in successive steps of the staircase voltage at the output 13 of the integrator circuit 12. Any value of the tuning voltage between the individual steps of the staircase voltage can thus be attained by means of the frequency control circuit 16, so that exact tuning to any desired nominal frequency is possible.
It can be seen that the tuning of the input stage to the nominal frequency takes place substantially in two steps, namely in a coarse-tuning obtained substantially with digital means, and in subsequent silimar fine-tuning.
The count of the information counter 8, which is obtained by the control logic 29 in the interruption of its step-by-step action, can be stored in a store 34. The desired store position can be selected over the addressing inputs A to D. The storage process is controlled by the control logic 29.
By pressing again on trip switch 37, the above described transmitter search can be continued. When the next transmitter is found, the same processes take place as described above. The count of the information counter 8 attained at the location of the next transmitter can likewise be stored again in store 34.
Since, with the storage of the respective readings of the information counter 8, the information on the respective frequency band contained in band store 40 has also been stored away, not only the stored counter reading arrives in the information counter during the addressing of store 34 for the selection of the respective frequency, but also the band information stored in band store 40. This has the effect that the input stage is set to this frequency range. The reading input of the information counter 8 has the result that the tuning voltage associated with this reading is given off at the output 13 of integrator 12, so that the input stage is coarse-tuned to the desired transmitter. This coarse-tuning thus effects the triggering of the frequency control circuit 16, when it approaches a transmitter, just as in the search run, which then effects the fine tuning to the desired transmitter.
As known, the frequency ranges which can be covered with a certain tuning range, are not equal in the VHF-ranges and in the UHF-ranges. The same variation of the tuning voltage leads in the UHF-range, to a greater variation of the tuning frequency than in the VHF-range. In order to take this fact into account, a switching is effected in Schmitt trigger 26 when trip switch 30 selecting the UHF-range is actuated. This switching has the effect on the control pulse produced by Schmitt trigger 26 that the frequency interval between the nominal frequency and the frequency at which the information counter 8 is stopped, is greater in the UHF-range than in the VHF-range.
FIG. 2 shows an embodiment of the circuit 24 for determining the coincidence between the sync pulses and the line flyback pulses. The video signal is fed to the input 45 and the line flyback signals are applied to the input 46. The sync pulses proper appear at the collectors of the Darlington pair transistors T1 and T2 which together with the input circuit consisting of the resistances R1 and R2 and the capacitors C1 and C2 serve to clip the sync pulses from the video signal. A resistance R3 leads from the connecting points of the capacitors C1 and C2 and of the resistance R2 to the positive terminal of the supply voltage.
The collectors of the transistors T1 and T2 are connected over a resistance R4 with the positive terminal of the supply voltage, and over two base current setting resistances R5, R7 with the base terminals of the transistors T3 and T4. The resistances R6 and R8 serve to shunt charge carriers from the base terminals of the transistors T3 and T4 to ground. Resistances R9 and R10 respectively lead from the collectors of the transistors T3 and T4 to the positive terminal of the supply voltage. Connected to the collector of transistor T3 is the base of a transistor T5 whose collector is connected directly to the positive terminal of the supply voltage and whose emitter is connected by a resistance R11 to the output of the coincidence circuit.
The line flyback pulses are fed from input 46 jointly over a resistance R12 and a capacitor C3 to the base terminals of two transistors T6 and T7 over two base current setting resistances R13 and R14. For shunting charge carriers, resistances R15 and R16 are connected to the base terminals of these transistors. The collector of transistor T7 is connected by a resistance R17 to the positive terminal of the supply voltage. Furthermore this collector is connected by a resistance R18 to the base of a transistor T8 whose emitter is connected to ground and whose collector is connected to the base of transistor T5. The collector of transistor T6 is connected to the collector of transistor T4 and to the base of the transistor T9 whose emitter is connected to ground, and whose collector is connected by a resistance R19 to the output 47 of the coincidence circuit. Between the output 47 and ground is connected a capacitor C4.
When the television receiver is in operation, line flyback pulses are constantly fed to the input 46. These line flyback pulses make the transistors T6 and T7 conductive. Transistor T8 is cut off. In the time periods between the line flyback pulses, transistor T8 is always conductive and transistor T6 is cut off.
As a criterion that the receiver is tuned to a television transmitter, the fact is used that in such a tuning to a television transmitter, the sync pulses transmitted by the latter coincide in time with the line flyback pulses in the television receiver or appear within the line flyback pulses. The presence of coincidence between the line flyback pulses and the sync pulses thus means that the receiver is tuned to a television transmitter.
In the tuning to a television transmitter, the sync pulses clipped by the transistors T1 and T2 from the video signal at the input 45 have the effect that the transistors T3 and T4 are blocked. Since transistor T8 had already been blocked by the line flyback pulses at the input 46, transistor T5 can switch into the conductive state, so that a charging current can flow over transistor T4 to capacitor C4. When the charging voltage at capacitor C4 exceeds the threshold value of Schmitt trigger 25, the latter gives off a control voltage which indicates the coincidence between the sync pulses and the line flyback pulses.
Transistor T9, which in the conductive state provides a discharge circuit for capacitor C4, is always blocked when at least one of the transistors T4 and T6 is conductive. This is naturally the case when there is coincidence, that is, when transistor T5 is conductive and permits the charging of capacitor C4.
In order to prevent that a charging voltage is formed on capacitor C4 by some breakdown in the absence of coincidence, the coincidence circuit of FIG. 2 is so designed that capacitor C4 is discharged in the time periods between line flyback pulses. This is achieved in the following manner: When a noise signal appears in the time interval between two line flyback pulses, which is so great that it simulates a sync pulse, the transistors T3 and T4 are blocked. Transistor T5 becomes thus non-conductive, since it is still held in the cut-off state by the conductive transistor T8. Since transistor T6 is always cut off in the time intervals between line flyback pulses, the cut off state of transistor T4 caused by the noise signal effects switching of transistor T9 into the conductive state. A charging voltage on capacitor C4 can therefore be by-passed by resistor R19 and the collector-emitter junction of transistor T9. Tests have shown that such noise signals appear relatively frequently, so that transistor T9 is switched several times into the conductive state in the periods between line flyback pulses. This prevents a charging voltage from building up on capacitor C4, which could trigger a response of Schmitt trigger 25 connected to output 47.
The same effect, namely the discharge of capacitor C4, is also realized by true sync pulses not simulated by noise signals, which fall into the periods between line flyback pulses. Such sync pulses appear in the non-synchronized state when the video signal received has not yet synchronized the oscillator generating the line flyback pulses.
Summarizing it can thus be said that the sync pulses act as charging pulses in the synchronized state, that is, in the case of coincidence which leads to the charging of capacitor C4, while they act in the non-synchronized state as discharge pulses which enable a discharge circuit for capacitor C4.

The specification discloses various embodiments of solid state television channel selection systems. The systems provide sequential and/or parallel access of television channels by operation of simple pushbutton or sense touch switches on the control panel of the television set, as well as sequential or parallel access of the channels through operation of remote control units. The system enables selected television channels to be skipped during the sequential access mode. The system enables the operator to selectively choose which VHF and UHF channels may be selected by the system.
(The photo is referred to the GRUNDIG:Station-Memory / Tuning Search - Program Memory)




1. A broadcast receiver tuning system comprising:
a memory for storing digital tuning words,
means responsive to said digital tuning words for tuning said receiver to a desired position,
programming switches operable to change the stored digital tuning words in said memory, and
speed control means operable in response to said switches for providing fine tuning of said receiver by slow progressive change of said words in said memory for a preset time interval and thereafter providing course tuning of said receiver by faster progressive change of said words in said memory.


2. The tuning system of claim 1 wherein said broadcast receiver comprises a television set.

3. The tuning system of claim 2 wherein said speed control means provides different tuning speeds for VHF channel tuning than for UHF channel tuning.

4. A television tuning system comprising:
means on the exterior of a television set for selecting desired channels,
address generator means responsive to said means for selecting for generating digital address signals,
memory means storing digital tuning words and responsive to said address signals for outputting selected ones of said tuning words,
means for converting said digital tuning words into analog tuning control signals,
programming switches on the exterior of the television set for changing the stored digital tuning words in said memory means, and
speed control means operable in response to initial actuation of said programming switches to provide fine tuning by slowly changing said stored digital tuning words in said memory means during a preset time interval and for thereafter providing coarse tuning by rapidly changing said stored digital tuning words in said memory means until said programming switches are deactivated.


5. The tuning system of claim 4 wherein said programming switches comprise:
up and down switches, and
skip circuitry responsive to actuation of both said switches to cause a predetermined television channel to be skipped.

6. The tuning system of claim 5 wherein said skip circuitry is operable to store logic zeroes at a memory location in said memory means to cause skipping of a channel.

7. The tuning system of claim 4 wherein said speed control means provides slower fine and coarse tuning speeds for UHF channel selection than for VHF channel selection.

8. The tuning system of claim 4 wherein said speed control means again provides fine tuning when said programming switches are deactivated.

Description:

This invention relates to television channel selection, and more particularly relates to a solid state system for selecting television channels and for displaying the selected channel.
It is well known that problems commonly occur in conventional rotary mechanical switch tuning systems which are presently utilized to select channels in television sets. For example, such mechanical rotary switches are subject to mechanical failure and inferior performance due to the inherent unreliability of the switch contacts. In addition, such rotary mechanical switches have not been able to provide parallel channel access, or the direct selection of a desired channel without the requirement of sequentially moving through unwanted channels. Moreover, such rotary mechanical switches have been bulky and expensive.
It has been heretofore proposed to eliminate the problems associated with rotary mechanical switches by the utilization of electronic circuitry. However, such previously developed electronic channel selection systems have not been sufficiently flexible to enable widespread use for a variety of different types of television sets and applications. For example, certain previously developed systems have required extremely uniform varactor tuning diodes to enable channel tuning, therby allowing insufficient tolerances for conventional variances between varactor diodes. Other previously developed systems have not been sufficiently modular to enable a selection of various types of channel access or displays. Moreover, previously developed electronic channel selectors have not been sufficiently economical to fabricate and have required uneconomical printed circuit boards or other uneconomical fabrication techniques or construction. For example, certain prior systems have required expensive potentiometers for each channel desired to be tuned.
In addition, previously developed electronic television tuning systems have not satisfactorily satisfied recent regulatory requirements which call for a television tuner to provide a comparable capability and quality of tuning for both VHF and UHF stations. Specifically, such prior tuning systems have not enabled selection and display of a selected group of precise UHF channels, nor have the prior systems provided means for easily changing selected UHF channels.
Iin accordance with the present invention, a solid state system is provided for tuning a television set which includes an array of switches each corresponding to a predetermined television channel. An address generator is responsive to the operation of the switches for generating multibit digital address words each corresponding to one of the switches. A tuning memory includes a random access memory for storing digital tuning words and for outputting the tuning words in response to the address words. Circuitry converts the tuning words into analog signals and controls a varactor diode ttuner in order to select the desired television channel.
In accordance with another aspect of the invention, a television tuning system includes a matrix array of switches for selecting a desired television channel. An address generator generates a unique binary address corresponding to the selected channel. A tuning memory stores a plurality of digital tuning words and outputs one digital tuning word in response to each unique binary address. A digital-to-analog converter converts the binary tuning words into an analog signal for providing channel tuning. Circuitry is responsive to the unique binary address for generating one of three band selection signals. A diode tuner is responsive to the analog signal and the band selection signal for tuning the desired television channel automatically.
In accordance with yet another aspect of the invention, a sequential access television channel tuning system includes switches for generating up and down scan indications. An up/down couonter is responsive to the switches for counting clock signals and for generating binary address signals. A memory generates unique digital tuning words in response to the address signals. Circuitry is responsive to the tuning words for tuning to a desired television channel.
In accordance with another aspect of the invention, a television channel tuning system includes a matrix array of switches operable to select a desired television channel. An address generator generates a unique binary address corresponding to the selected channel. A memory stores a plurality of digital tuning words each representative of a different television channel. A converter converts the tuning words into analog tuning levels. Circuitry is operable to selectively change the digital tuning words stored in the memory. Circuitry is also operable to cause selected ones of the digital addresses to be skipped during sequential access tuning of the system.
In accordance with yet another aspect of the invention, a combined sequential and parallel access television channel tuning system includes a matrix array of channel selection switches each operable to provide parallel selection of a television channel. Up and down channel selection switches are operably to provide sequential selection of television channels, the up and down switches being connected to terminals of the matrix array. Circuitry is responsive to operation of the matrix array switches for generating unique binary address signals corresponding to the selected television channel. Circuitry connected to the matrix array is responsive to operation of the up and down switches for generating sequential binary address signals corresponding to sequential television channels. Tuning circuitry is responsive to the binary address signals for tuning a selected television channel.
For a more complete understanding of the present invention and for further objects and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a somewhat diagrammatic view of a first embodiment of a 16 channel parallel access television selection system with illuminated sense buttons and including a sequential access remote tuning device;
FIG. 2 illustrates a 20 channel sequential access television channel selection system with illuminated channel lamps;
FIG. 3 illustrates a 20 channel parallel access channel selection system with pushbutton switches and adjacent light sources;
FIG. 4 illustrates another embodiment of a 20 channel parallel access selection unit with illuminated tab displays;
FIG. 5 illustrates a sequential access channel selection system having a two digit seven segment numeric channel display;
FIG. 6 illustrates a 20 channel parallel access system with a two digit seven segment channel display;
FIG. 7 is a block diagram of s 16 channel parallel or sequential access system with a neon light illuminated tab display;
FIG. 8 is a block diagram of a 20 channel combined sequential and parallel access system with a two digit seven segment display;
FIG. 9 is a schematic diagram of an address generator for a 16 channel sequential channel selection circuit;
FIG. 10 is a state diagram of the operation of the AFC sequence counter and associated circuitry of the circuit shown in FIG. 9;
FIGS. 11a-h comprise waveforms of portions of the circuit as shown in FIG. 9 during operation;
FIG. 12 is a schematic diagram of a 16 channel parallel access address generator for use in conjunction with the sequential access circuit of FIG. 9;
FIG. 13 is a block diagram of a tuning memory for use with both the sequential access address generator of FIG. 9 and the parallel access address generator of FIG. 12;
FIG. 14 is a schematic diagram of a 20 channel combined sequential access and parallel access address generator as shown in FIG. 8;
FIG. 15 is a block diagram of a tuning memory for use with the 20 channel selection address generator of FIG. 14;
FIGS. 16a and 16b are schematic diagrams of the tuning memory of FIG. 15; and
FIGS. 17a-h are waveforms of a portion of the tuning memory as shown in FIG. 16;
Referring to the drawings, FIGS. 1-6 illustrate variations of tuning control features for a television set which are provided by the present invention. Referring to FIG. 1, a television set 10 includes a conventional television screen 12 and a control panel 14. A picture and sound control set 16 includes variable controls for controlling the volume, picture brightness, contrast, tint and color of the television picture. A microphone 18 receives ultrasonic commands from the remote control unit.
A set of 12 pushbutton or touch sense switches 20 is provided to enable selection of VHF television stations. A set of four pushbuttons or touch sense switches 22 is provided to enable selection of UHF television channels. The switches 20 may be selectively depressed to select any one of VHF channels 2-13. The numerals 2-13 may be permanently affixed to the pushbutton switches 20, or alternatively, tabs bearing indicia may be selectively affixed to or removed from the switches 20. Depression of the switches 20 causes the selected switch and the corresponding indicia to become illuminated, such that the operator will know the desired channel has been selected for display.
The switches 22 may also be provided with removable tabs bearing numerals, such that any selected group of VHF and UHF television channels may be selected in the manner to be subsequently described. In the illustrated embodiment, four UHF television stations may be selected by depression of the switches 22. Depression of one of the switches 22 causes the selected switch and the corresponding tab indicia to be illuminated. Although in the illustrated embodiment four UHF channels are provided for selection, in other embodiments of the invention to be subsequently described, the capacity for more or less UHF channel selections may be provided. As will be subsequently described, when the television set 10 is initially tuned, the desired VHF and UHF channels are set into the system and tabs bearing the desired channel indicia are inserted into the pushbutton switches 20 and 22. If desired, the selected VHF and UHF channels may be selectively changed at any time.
A remote control tuning device 24 is provided for use with the present tuning system and includes an off/on button 26. An up button 28 is provided to be depressed to enable sequential selection of the channel by moving the tuning system of the television set 10 from one channel to a higher number channel. A down button 30 is provided to be depressed to cause automatic sequential selection of television channels in the set 10 by causing the tuning of the set to move from one channel to a lower number channel.

As noted, any of the pushbutton switches 20 and 22 may be selectively depressed and the television set 10 will be automatically tuned to the desired channel. This type of selection is termed parallel access or selection. The type of series channel selection provided by the remote control unit 24 is termed sequential channel selection. It will be understood that an array of switch buttons could be provided on the remote control unit 24 to enable parallel selection of channels by the remote control unit 24. Remote control unit 24 operates according to any one of a variety of well known techniques, such as by generating acoustic signals which are detected by tuned circuits in the television set 10 to enable channel selection.
An up voltage programming pushbutton switch 32 and a down voltage programming pushbutton switch 34 are provided behind a removable panel, etc. on the television set 10 to enable initial tuning of the VHF and UHF channels which may be selected by actuation of the switches 20 and 22. In order to initially program the system to select a desired channel, the operator first disengages the channel skip circuit and AFC circuit (to be later described) and then pushes the first VHF switch 20 which corresponds to Channel 2. Both voltage programming switches 32 and 34 are then depressed for a brief period to clear the system. The switch 32 is then depressed until Channel 2 appears on screen 12. If either switch 32 or 34 is depressed longer than a preset period, as for example 8 seconds, the system switches to a fast tuning mode. When the picture appears on screen 12, the switch 32 is released and, on again pressing switch 32 or 34, the system switches back to the slow tuning mode. Switches 32 and 34 may then be "bumped" to fine tune the program on the screen 12.
When Channel 2 is tuned, the next switch 20 is depressed and the same sequence is performed to select VHF Channel 3. When all VHF channels have been programmed, the four selected UHF channels are programmed in the same way and tabs having indicia corresponding to the selected UHF channels are added to the switches 22. If desired, less VHF and more UHF channels may be programmed into the system. Once all switches 20 and 22 have been programmed, the skip circuit is again energized, and it is necessary only to depress or otherwise actuate one of the switches 20 or 22 and the set 10 will be automatically tuned to the desired channel and the actuated switch will be illuminated.
FIG. 2 illustrates a variation of the television tuning system shown in FIG. 1, and like numerals will be utilized for like and corresponding parts previously described. In this embodiment, parallel access of television channels is not provided on the front panel of the set 10, but only serial or sequential channel access is provided for 20 channels. Twelve lamps 36 are each provided with an indicia from 2-13 in order to indicate a desired VHF television channel when illuminated. A second set of lamps 38 is provided in order to indicate eight selected UHF channels. The indicia formed on lamps 36 are fixed, while the indicia for lamps 38 may be removed and changed as desired. The particular UHF channels which may be selected and illuminated by the lamps 38 are chosen by the operator by operation of an up voltage programming button 40 and down voltage programming button 42 in the manner previously described.
An up channel advance button 44 and a down channel advance button 46 may be selectively depressed by the operator in order to cause lamps 36 and 38 to be sequentially illuminated. When the lamp corresponding to the desired channel is illuminated, the button 44 or 46 is released and the set 10 will be tuned to the desired illuminated channel. It will be understood that sequential channel access may also be provided with the system shown in FIG. 2 by a remote control unit similar to that shown in FIG. 1. In addition, if desired, parallel access may be provided by remote control units having the required number of pushbutton selection switches.
As noted, initial programming of the channels associated with lamps 36 and 38 is accomplished in the manner previously described by operation of voltage programming buttons 40 and 42. In some cases, it may be desirable to skip certain channels during sequential access. To skip a channel, the skip disable switch is opened, and the channel is selected. Both buttons 40 and 42 are then simultaneously depressed for a brief period, and the skip disable switch is then closed. Subsequent operation of the tuning system will result in the skipping of that channel, and thus the lamps 36 and 38 corresponding to skipped channels will not be illuminated. In this manner, inactive or undesired channels need not be tuned through when searching for valid channels.
FIG. 3 illustrates a third embodiment of the television channel selection system according to the invention which enables selection of VHF channels by 12 pushbutton switches 50, each of which is provided with a suitable channel indicia. Twelve lamps or light emitting diodes (LEDs) 52 are disposed adjacent switches 50 and are illuminated upon depression of the associated switches 50. To enable UHF channel selection, eight pushbutton switches 54 are provided in association with eight LEDs 56 which are illuminated when the corresponding switch is depressed. Indicia tabs are operable to be inserted into the pushbutton switches 54 to designate the particular UHF channels desired to be selected. An up voltage programming switch 58 and down voltage programming switch 60 are operable during initial programming of the set 10 to tune the channels selected by pushbutton switches 50 and 54.
FIG. 4 illustrates another embodiment of a channel select and display system according to the invention. Twelve pushbutton switches 62 may be depressed to select VHF channels. Lamps 64 are associated with the pushbutton switches 62 and have indicia thereon which are illuminated when the lamp is energized by the depression of the corresponding pushbutton switch 62. Eight, or any other selected number less then eight, pushbutton switches 66 may be depressed for selection of UHF channels. Eight lamps 68 include selected indicia thereon corresponding to the desired UHF channels. The indicia may be selectively changed by removing tabs bearing the indicia and by selection of new tabs with different indicia thereon. An up voltage programming button 70 and a down voltage programming button 72 enable tuning of the desired channels to be selected by the pushbutton switches 62 and 66. It will be noted, if desired, a remote control unit similar to that shown in FIG. 1 may be utilized to control sequential selection of the channels of the system shown in FIGS. 3 and 4. Further, up and down channel selection switches may be also incorporated on the select system shown in FIGS. 3 and 4.
FIG. 5 illustrates a station select and display system wherein sequential channel selection is enabled by an up channel advance button 74 and by a down channel advance button 76. The number of the channel presently being displayed on the screen 12 is displayed in a seven segment two digit display 78. In this embodiment, the VHF channel numbers are contained in a read only memory (ROM), and are not programmable. The UHF channel numbers which may be displayed in the display 78 are chosen by operation of a display programming button 83, which is depressed until the correct number is displayed, then released. In operation, the operator pushes either the up button 74 or the down button 76 and when the desired television channel number is displayed on the display 78, the operator releases his finger and the set is tuned to the desired channel.
FIG. 6 illustrates a variation of the system shown in FIG. 5 wherein parallel channel access may be provided by the use of a switch array 84. The switch array 84 may comprise mechanical pushbutton switches or sense touch buttons with removable tabs to enable the channel number to be changed. In operation of the system shown in FIG. 6, the desired channel is selected by merely depressing or actuating a switch in the array 84 which corresponds to the desired channel. The desired channel number will appear in the display 78 and the set will be automatically tuned for display of the selected channel.
Sixteen Channel Tuner With Neon Display
FIG. 7 illustrates a 16 channel system with a neon light display. This system may be utilized to provide the functions of the systems shown in FIGS. 1-4. The terminals of a 4×4 pushbutton switch array matrix 90 are connected to a parallel address generator 92 which applies binary address signals on a multiline bus comprising four leads 94, 96, 98 and 100 to a tuning memory 102 and to a neon display 104. A second sequential address generator 93 also connects to leads 94, 96, 98 and 100. The multiline bus enables the present system to be modular, such that different displays and address generators may be easily substituted to provide a wide range of desired functions. An up pushbutton switch 106 and a down pushbutton switch 108 are connected to the address generator 93 to enable serial channel access when desired. The address generators 92 and 93 generate an AFC (Automatic Frequency Control) defeat signal via leads 110 which is utilized to eliminate AFC during tuning operation. A skip signal is applied from the tuning memory 102 to the generator 93 via lead 112 to enable predetermined tuning positions to be skipped during sequential channel selection. Switch 113 may be thrown to disengage the skip function during the set-up procedure. Switch 113 may be mechanically interlocked with the AFC switch to eliminate AFC during skip programming.
An up pushbutton switch 114 and a down pushbutton switch 116 are utilized to program the tuning memory to enable selection of desired channels. The selected binary words stored in the tuning memory 102 are applied to a digital to analog converter 103 which generates duty cycle modulated binary signals that are fed to the analog integrator, which in turn feeds the varactor diode tuner 120. Tuner 120 operates in the known manner to vary the local oscillator of the television set in order to select the desired television channels, and the RF tanks (not shown) to reject unwanted signals. Band selection signals are applied from the tuning memory 102 to the bases of transistors 122. The collectors of transistors 122 are coupled to the bases of transistors 124 to generate band selection signals UHF, HVHF and LVHF which are applied to the varactor diode tuner 120 in order to select the varactor diode set necessary to perform the desired tuning operation. The generation of the band selection signals is accomplished automatically and no action by the operator of the set is needed, except during initial programming.
The address signals generated by the address generators 92 and 93 are also applied from the multiline bus to a neon display driver 104 which enables transistors 130 and leads 132 in order to selectively energize neon light bulbs contained within a 4×4 display matrix 134. The neon display 104 is responsive to the address generated by the generators 92 and 93 such that one of the neon lamps within matrix 134 is energized to correspond with the pushbutton depressed in the matrix 90 to indicate which television channel is presently being tuned. The lamps may be incorporated into the switches 90 (FIG. 1) or placed adjacent the switches 90 (FIG. 3).
Briefly, in operation of the system shown in FIG. 7 in the parallel access mode, one of the switches in the matrix 90 is actuated. The address generator 92 detects which of the pushbutton switches was actuated and generates a four bit binary address via leads 94-100 to the tuning memory 102. In response to the digital address, the tuning memory 102 applies a binary tuning word stored in the memory to the digital-to-analog converter 103. Converter 103 converts the binary word into a duty cycle modulated binary signal, which drives integrator 118, generating an analog voltage and applies the voltage to the varactor diode set within tuner 120 which is selected by the band selection signals. Such varactor diode tuners are known in the art and generally operate as voltage variable capacitors which vary a local oscillator and RF tank frequency to provide channel tuning. The address signals generated by the generator 92 operate through the neon display driver 104 in order to energize one of the neon lamps in the array 134 in order to indicate which channel is presently being displayed.
In the operation of the system shown in FIG. 7 in the serial or sequential channel access mode, one of the up channel select buttons 106 or down channel select buttons 108 is depressed by the operator. The address generator 93 then generates a series of addresses to the tuning memory 102 such that a series of the stored binary words in the memory 102 is applied to the digital-to-analog convertor 103 and integrator 118. A series of analog voltages are then applied to the varactor diode tuner 102 such that one channel after another is selected for display. The address from the address generator 93 is also applied to the neon display driver 104 such that lamps in the array 134 are sequentially energized in order to indicate which of the channels is presently being displayed. When the operator sees that the desired channel is displayed by viewing the energized lamp in the array 134, he releases his finger from one of the buttons 106 or 108 and the set is properly tuned. As previously noted, desired channels may be programmed by operation of the up voltage programming button 114 and down voltage programming button 116 such that the channels are skipped during sequential tuning. In such a case, the tuning memory 102 operates to skip the unused position and the neon display 134 does not display the skipped channel indication.
Twenty Channel Tuner With Numeric Display
FIG. 8 illustrates a system somewhat similar to the system shown in FIG. 7, and thus like numerals are utilized for like and corresponding parts previously described. In this embodiment, a 5×4 pushbutton switch selection matrix 140 is provided such that twelve VHF and eight UHF channels may be selected. It will, of course, be understood that the display shown in FIG. 8 may be used with the system of FIG. 7, and vice versa, the illustrated systems being merely exemplary.
In the embodiment of FIG. 8, a multiline bus comprising five address lines 94, 96, 98, 100 and 101 extends between an address generator 141 and a tuning memory 143. An advantage of the system shown in FIG. 8 is that both the up channel select switch 106 and down channel select switch 108 are connected to terminals of the matrix 140, and thus do not require additional chip pin connections. Moreover, the skip signal applied via lead 112 is applied through matrix 140 to the address generator 141. The system shown in FIG. 8 may be used in a system such as shown in FIGS. 5 or 6, or alternatively may be utilized in a channel selection system utilizing both the up and down channel advance buttons 74 and 76 of FIG. 5 and the pushbutton array 84 shown in FIG. 6 on the same television set front panel.
The operation of the system shown in FIG. 8 is similar to that shown in FIG. 7, except that the five address lines from the address generator 141 are applied to a display memory 145 which generates control signals to a seven segment decoder 142. The two circuits 142 and 145 may be formed on separate chips, or may be combined in one circuit. Decoder 142 drives the two digit seven segment display 147 to provide a visual indication of the channel presently being tuned. If desired, the neon lamp display driver 104 of FIG. 7 may be used in place of the digital readout and display.
Address Generator For 16 Channel Sequential Access System
FIG. 9 illustrates in schematic detail a sequential access program generator 93 for use in the system of FIG. 7. As will be subsequently described, the circuit shown in FIG. 9 may be combined with circuitry shown in FIG. 12 to allow the selection by a manufacturer of serial and/or parallel channel access. An advantage of the circuitry shown in FIG. 9 is that the entire circuit may be formed on a single 16 pin semiconductor chip utilizing conventional integrated fabrication techniques.
Referring to FIG. 9, an up channel select pushbutton switch 150 is connected to a pin 152 of the semiconductor chip and is applied through inverting buffers 154 and 156 to a terminal of a NAND gate 158. Similarly, a down channel select pushbutton switch 160 is applied to a pin 162 of the semiconductor chip and is applied through inverting buffers 164 and 166 to a terminal of a NAND gate 168. Gates 158 and 168 are interconnected as a latch. The outputs of gates 158 and 168 are applied to the up and down inputs of a four bit up/down presettable multi-modulo counter 170. Counter 170 enables the circuit to select either six, eight, 12 or 16 television channels, as desired. In order to set the counter 170 to enable selection of a predetermined number of television channels, pins 172 and 174 are selectively grounded or opened according to a conventional code.
The outputs of the counter 170 are applied through NAND gates 176, 178, 180 and 182 to pins 184, 186, 188 and 190 to provide the four bit binary address which is applied to leads 94, 96, 98 and 100 previously shown in FIG. 7. The channel skip signal is generated from circuitry to be later described in FIG. 13 or other figures and is applied through inverting buffers 192 and 194 to an input of an OR gate 196. The output of gate 196 is applied through an invertor 198 to control the clocking of the counter 170 such that a memory address will be skipped for each input signal on the channel skip line.

An oscillator 200 generates clock signals to a three bit AFC sequence counter 202. The C output of counter 202 comprises a clock out signal which is applied to the second input of gate 196. The output of invertor 192 is applied as an extend signal to oscillator 200, and the output of invertor 194 is applied as a clear signal to counter 202. The three bit outputs from counter 202 are applied as inputs to a NAND gate 204, the output of which is applied as an enable signal to oscillator 200. The A and B outputs from counter 202 are applied to a NAND gate 206, the output of which is applied through a NAND gate 208 and invertor 210 to an input of an OR gate 212 to provide a stretched AFC defeat signal.
The outputs of invertors 156 and 166 are tied to the inputs of an OR gate 214, the output of which is applied to a NAND gate 216. The output of gate 216 is tied to inputs of NAND gates 176-182. The output of gate 216 is also applied to a pin 218 to a NAND gate 220 which is located on the chip to be described in FIG. 12. The output of gate 220 is applied through pin 222 to the input of gate 216. Gate 220 comprises a latch which enables the selection by a television manufacturer of either the serial access circuit shown in FIG. 9 or the parallel access circuit shown in FIG. 12, or both circuits. The output of gate 216 is also applied to the load input of counter 170.
FIGS. 10 and 11 assist in the explanation of the operation of the system shown in FIG. 9. FIG. 10 comprises a state diagram illustrating the various stages of operation of the AFC sequence counter system of FIG. 9 during sequential channel selection. FIG. 11 illustrates various waveforms of portions of the circuit of FIG. 9. If it is desired to operate the television set only in the sequential access mode, pin 222 is grounded such that the circuit of FIG. 9 is activated and the circuit to be described in FIG. 12 is not installed. This grounding connection will be made by the television manufacturer upon determination of the type of channel selection control desired. If the manufacturer so decides, both the circuits of FIGS. 9 and 12 will be used to provide both sequential and parallel access. Upon grounding of pin 222, gate 216 generates a logic one output which allows data to ripple through the gates 176, 178, 180 and 182.
Referring to FIG. 10, at the beginning of operation of circuitry shown in FIG. 9, the counter 202 is set at 111. When the operator depresses either the up or down channel selection buttons 150 or 160, the counter 202 cycles to state 000 generating a station change signal, and then to states 001 and 010. During the counter states 000, 001 and 010, the gates 206 and 208 decode the counter outputs and generate the AFC defeat signal through gate 212. During the remaining states 011, 100, 010 and 110, the operator decides whether or not the channel being accessed is the desired channel. If so, the operator releases the button 150 or 160 and terminates operation of the system. The oscillator 200 is enabled through the NAND gate 204 during this operator recognition time and the oscillator 200 cannot be stopped during the states of operation until the operator takes his finger off the up or down selection buttons 150 or 160. The counter 202 will only stop in state 111 in any case.
If the particular station being accessed is not the desired station, the operator maintains his finger on either buttons 150 or 160, and the counter 202 sequences to state 111 and to state 000, such that a station change is generated to counter 170 and the cycle is repeated. The counter 170 then generates a new binary address to pins 184-190. If, however, a skip signal is generated during any state, the skip signal is applied from gate 196 and invertor 198 to counter 170 such that the counter is advances one state for each skip signal. The memory address, or addresses, are then skipped and the cycle begins again for another cycle. The resulting outputs from the counter 170 for a valid station comprise a unique four bit binary word which is decoded by subsequent circuitry.
Specifically referring to sequence counter 202 and associated circuitry in FIG. 9, a logic low appearing at the output of gate 214 and which is applied to an input of NAND gate 204 forces the output of a NAND gate 204 high, thereby enabling the oscillator 200. The counter 202 will continue to count in complete cycles as long as a logic low forces a one on the enable output of gate 204. When the low applied to gate 204 is removed, the output of gate 204 will set up conditions for the counter 202 to stop the next time that logic state 111 appears at the output of counter 202, thereby terminating the cycle.
Referring to FIG. 11, waveform 11a illustrates the depression of the up channel select button 150 by the operator during the time interval t ₁ -t ₀ . The waveform shown in FIG. 11b illustrates the oscillator enable signal that is applied to oscillator 200 from gate 204. The waveform shown in FIG. 11c illustrates the capacitor charging voltage generated within the oscillator 200. The interval designated generally by arrow 230 indicates the generation of skip channel pulses while that shown as 231 illustrates one skip pulse. The waveform shown in FIG. 11d indicates the output of the oscillator 200 which is applied to clock the sequence counter 202. The waveform shown in FIG. 11e comprises the eight states of operation of the counter 202 previously described in FIG. 10. The first three states zero, one and two of each cycle provide the AFC defeat function.

The waveform shown in FIG. 11f comprises the clock output of the counter 202 which is applied to gate 196 and to the invertor 208. The clock output pulse 232 is elongated due to the generation of skip channel signals. The waveform shown in FIG. 11g comprises the channel skip inputs which are applied through inverters 192 and 194 to gate 196. As noted, the channel skip inputs are generaated by circuitry to be subsequently described such that invalid channels which do not have programs in a particular area will not be cycled through by the present circuit. During the interval designated generally by the arrow 234, five skip signals are generated such that five invalid channels are skipped. During the interval designated generally by the numeral 236, a single invalid channel is skipped. The waveform shown in FIG. 11h comprises the clock inputs which are generated by gate 196 and are inverted by inverter 198 to clock the counter 170.
During operation of the circuit of FIG. 9, the depression of up channel select button 150 causes the counter 170 to generate an upward changing sequence of four bit address words to pins 184, 186, 188 and 190. These address words are applied to the memory circuit shown in FIG. 13 in order to select memory words, which in turn cause the control of varactor diode tuners. Depression of the down channel select button 160 causes operation of the counter 170 in the down mode to cause a downward sequence of address words to be generated from the counter 170. As noted, the number of address words generated by the counter 170 is controlled by selective grounding of pins 172 and 174.
Address Generator For 16 Channel Parallel Access System
FIG. 12 illustrates a parallel access address generator 92 which may be fabricated on a single 18 pin semiconductor chip with integrated logic techniques and utilized in the system of FIG. 7. This circuit may be used in place of or in conjunction with the circuitry shown in FIG. 9. As previously noted, the circuits shown in FIG. 9 and FIG. 12 are interconnected by a common gate 220, the terminals of which may be selectively grounded to enable the television manufacturer to use either the circuitry shown in FIG. 9 or FIG. 12. If the gate terminals are cross connected, both circuits are enabled for use.
Referring to FIG. 12, a 4×4 array of sixteen touch sense switches, or any other suitable type of switches, is formed as a switch matrix 240. Four terminals of the matrix 240 are connected to a four line sense amplifying stage 242, while the remaining four terminals of the matrix 240 are connected to four line sense amplifiers 244. The outputs of amplifiers 242 are applied to a four to two line encode circuit 246. The outputs of the amplifiers 244 are applied to a four to two line encode circuit 248. The outputs of the amplifiers 242 are also applied to a NOR gate 250, the output of which is applied to a NAND gate 252. The outputs from the amplifiers 244 are applied to the inputs of a NOR gate 254, the output of which is also applied to an input of gate 252.
The two outputs from the encode circuits 246 are applied through time delays 256 and 258 to a four bit latch 260. The outputs from the encode circuit 248 are applied through time delays 262 and 264 to the latch 260. The output of gate 252 is applied to load the latch 260 and is applied to the AFC defeat circuit 266. The AFC defeat circuit 266 generates an AFC defeat signal which is applied through the gate 212 previously shown in FIG. 9. Pin 268 connects the gate 212 to the chip shown in FIG. 12, while pin 270 connects the gate to the circuit of FIG. 9. The outputs of the latch 260 are applied through NAND gates 274, 276, 278 and 280 to provide a four bit binary address at pins A, B, C and D.
In operation of the circuit shown in FIG. 12, the manufacturer may choose either or both of the address generator circuits shown in FIG. 9 and FIG. 12 by selective grounding or interconnecting of terminals of the gates 220. In some instances, the circuit shown in FIG. 9 will be utilized as the remote control channel selection circuitry, while the circuitry shown in FIG. 12 will be used as the channel selection circuitry for the set control panel. When one of the sense switches in the matrix 240 is depressed, a logic zero appears at the output of one of the amplifiers 242 and one of the amplifiers 244. Gates 250 and 254 then generate logic one outputs which operate through the gate 252 in order to initiate an AFC defeat signal from circuit 266. This eliminates the AFC of the system during the tuning operation, and also provides an extended AFC defeat signal after the customer releases the button.
The encode circuits 246 and 248 detect the output from the amplifiers 242 and 244 and transmit encoded signals through the time delays 256-264 which provide sufficient time delays to enable the latch 260 to be loaded in response to the signals generated by the gate 252. A four bit binary code is generated from the encode circuits 246 and 248 for storage in the latch 260. The latch 260 then generates a four bit digital code output through the NAND gates 274-280. The outputs from the gates 274-280 may not be transmitted to pins A-D unless the gate 220 generates a logic one which is applied to the inputs of the NAND gates 274-280. Gate 220 also operates to override the output from the circuit shown in FIG. 9.
When the circuits shown in FIGS. 9 and 12 are used concurrently, provision must be made to store the state of the circuit shown in FIG. 12 in the parallel circuit of FIG. 9. Consequently, assume that the circuit shown in FIG. 9 has been placed in the up mode and then the circuit shown in FIG. 12 is energized and a channel selected thereby. When the operator next tries to go back to the circuit shown in FIG. 9, it is desirable to start at the last channel selected by the circuitry shown in FIG. 12. Thus, the data word generated from the four bit latch 260 is also applied to the output of the circuit shown in FIG. 9. Thus, when the circuit of FIG. 9 is not active, a load signal is generated from the gate 220 and is applied through the invertor 286 to load the counter 170 with the output of the circuit shown in FIG. 12.
Tuning Memory For Sixteen Channel System
FIG. 13 is a schematic diagram of the tuning memory 102 previously shown in FIG. 7. This circuit may be utilized with either or both of the circuits shown in FIGS. 9 and 12, as well as other circuits using similar techniques. The binary address outputs from the circuits previously described in FIGS. 9 and 12 are applied to the A, B, C and D inputs of the circuit of FIG. 13 and are applied to a four to 16 line decode circuit 290. The resulting word enable signals are applied to a two bit 16 word band switch and skip random access memory (RAM) 292 and a 12 bit 16 word tuning voltage RAM 294. RAMs 292 and 294 have stored therein binary coded words which flag the television channel to be skipped, LVHF, HVHF and UHF band switch information, and which define an analog voltage level utilized to control a desired varactor diode in the tuning system. Data multiplex gates 296 control the input and output of the data stored in RAM 292. Data multiplexing gates 298 control the input and output of data stored in RAM 294. A D.C. voltage, typically from a battery, is applied to pin 300 in order to protect the storage of the RAMs 292 and 294 during the interval from set-up by the manufacturer and ultimate use by the consumer. Voltage is applied from a storage battery to pins 300 in order to provide as much as six months protection to the stored contents of the RAMs.
The output from RAM 294 is applied to a 12 bit presettable ripple up/down counter 302 which generates output data to a 12 bit data comparator 304. A 12 bit synchronous binary counter 306 also applies binary patterns to the comparator 304 which in turn generates an output through buffer 308 representative of the digital data from the RAM 294 in a predetermined output sequence. The predetermined output sequence is provided with a high ripple frequency such that the integrating capacitor in the integrating filter of the D-A convertor may be as small as possible. The output applied through invertor 308 to pin 310 is thus applied to a D-flipflop and to an integrating filter in order to provide the desired analog voltage for control of the varactor diode for tuning of the television set.
A 1 MHz clock input is applied through pin 312 and through an invertor 314 to clock the synchronous binary counter 306. Clock signals are also applied from the counter 306 to a count down and frequency select circuit 318 which generates clock signals for a tuning program generator 320. Generator 320 is loaded by operation of the voltage programming up button 322 and down button 324. The operation of the programming buttons has been previously described with respect to FIGS. 1-6. The buttons 322 and 324 are utilized to program the tuning voltage for the VHF and UHF channels which are selected by the system. Up/down clock and load signals are applied from the generator 320 to the counter 302 and are utilized to program the binary words stored in the RAM 294. Read/write signals are also generated from the generator 320 to the data multiplexing gates 298 for the RAM 294.
Program band and skip signals are applied to pin 325 to a band/skip program generator 326 which generates read/write signals to the data multiplexing gates 296 and which also generates clock signals to a two bit ripple counter 330. Band select signals and channel skip information is generated by a generator 334 and applied to pins 336, 338, 340 and 342 for application to the varactor diode tuner in the manner shown in FIG. 7. Data is transmitted to the data multiplexing gates 296 from the ripple counter 330 and is applied from the gates 296 to the generator 334.
In operation of the tuning memory circuit shown in FIG. 13, it will be assumed that the system is to be initially programmed by the manufacturer. A storage battery is connected to the pin 300 in order to protect the memory of the RAMs 292 and 294. In order to tune the first valid VHF Channel 2, both of the up and down buttons 322 and 324 are simultaneously pressed for a brief period. A signal is generated by the generator 320 such that all logic zeroes are applied to the up/down counter 302, and subsequently loaded into the RAM. Since all logic zeroes are now present in the RAM, giving a known initial condition, the up button 322 is depressed. After a set time interval such as 8 seconds, the system changes from a slow mode to a fast mode until the button is released. Inasmuch as the system started out at the logic zero level, the first channel will be Channel 2 and the operator then removes his finger. The system goes into an 8 second slow mode of operation on release of the button and the operator may alternatively operate the tuning buttons 322 and 324 in order to fine tune Channel 2. This procedure is repeated by the manufacturer until all VHF signals have been selected. The selected UHF channels may also be selected in the same manner, usually by the consumer. It should be noted for channels whose binary data word in closer to all ones than all zeroes (above the middle of a band), it would be preferable to press the down button after setting memory to zero, thereby counting down, and approaching the channel from above its frequency rather than from below as described previously.
After the consumer buys a set, it may be desired to skip certain program channels which are not available in the consumer's viewing area. In order to skip a channel, the set is addressed to the memory address of the channel to be skipped. Both the up button 322 and down button 324 are simultaneously depressed and two zeroes are entered into the RAM 292 for that channel. When the channel skip generator 334 detects two zeroes transmitted from the RAM 292, the channel skip signal is generated from generator 334 such that the channel will be skipped when operating in the sequential access mode.
In operation of the circuit, the band switch RAM 292 receives the two bit data input word from the counter 330 through the multiplexing gates 296. The word is stored in RAM 292, and later transmitted through the multiplexing gates 296 to the generator 334 in order to generate the band switch signals to the varactor tuner through pins 336-340.
The 1 MHz clock applied to pin 312 clocks the counter 306, which provides twelve outputs to the comparator 304 which changes in a synchronous fashion. The comparator 304 converts the binary word generated from the RAM 294 through the up/down counter 302 into an output signal which is applied through buffer 308. The output signal has a duty cycle equivalent to the desired D.C. level. Thus, the output of comparator 304 comprises data words having duty cycles such that when the data words are integrated, a desired analog voltage is provided. The least significant (fastest changing) bit from the synchronous binary counter 306 is matched with the most significant bit from the RAM 294 in order to provide the maximum cross coupling to provide maximum ripple frequency of the output signal applied to pin 310.
It will be understood that other types of digital scanning systems for providing inputs to the integration circuit may be utilized with the invention in place of the synchronous counter 306 and comparator 304. For example, a digital scanning system such as described in U.S. Pat. Application Ser. No. 457,664, filed Apr. 3, 1974 by Tegze Haraszti and Preston Snuggs may be utilized in the system shown in FIG. 13. Alternatively, the SN7497 Binary Rate Multiplier manufactured and sold by Texas Instruments of Dallas, Tex. may be used for the counter 306 and comparator 304.
In the U.S.A. market, the low VHF band (enabled by pin 340) comprises five VHF channels 2 through 6, while the high VHF band (enabled by pin 338) comprises seven VHF channels 7 through 13. However, the UHF band (enabled by pin 336) will be comprised of a possible seventy channels. Hence, when fine tuning during channel selection, more bits will be required to fine tune across each VHF channel than across each UHF channel. The count down and frequency select circuit 318 provides a fast or a slow tuning voltage in dependence upon which band is being enabled. When the UHF signal band signal is generated on pin 336, a signal is applied via lead 350 to the select circuit 318 such that a slower clock signal is applied to the tuning program generator 320.
Combined Serial and Parallel Access Channel Selection Circuit for Twenty
Channel Tuning System
FIG. 14 is a schematic diagram of the address generator 141 for use in the twenty channel tuning system shown in FIG. 8. An advantage of the circuitry shown in FIG. 14 is that both serial access and parallel access channel selection functions are accomplished by circuitry on a single semiconductor 18 pin integrated logic semiconductor chip.
Referring to the circuit shown in FIG. 14, a 4×5 twenty pushbutton switch array 360 is provided which may correspond to the parallel access systems shown in FIGS. 1, 4 and 6. An up sequential access button 362 and a down sequential access button 264 are connected through the matrix 360 to enable sequential channel selection. Such up and down channel selection may alternatively be accomplished with use of a remote control unit. The channel skip signal from the memory chip also enters chip 141 through the switch matrix 360.
The terminals of the array 360 are connected to a set of output buffers 366 and input buffers 368. The outputs from the input buffers 368 are applied to a five to three line encoder 370. The inputs of the output buffers 366 are connected to a two to four line decoder 372. The outputs of encoder 370 are applied to the Data C, D and E terminals of a five bit presettable up/down counter 374. The decoder 372 inputs are connected to D _A and D _B input terminals of the counter 374. The output of the counter 374 is applied to pins A-E and comprises the five bit output applied from the address generator 141 to the tuning memory 143 as shown in FIG. 8.
The outputs from the input buffers 368 are also applied to the inputs of an OR gate 376, the output of which is applied to load counter 374 and is applied through an invertor 378 to an input of a NAND gate 380. Gate 380 is connected in a latch configuration with a NAND gate 382. The output of NAND gate 382 is applied as an input to an OR gate 384, the output of which is applied through an invertor 386 to clock the counter 374. The output of gate 382 is also applied as an input to a NAND gate 388, the output of which is applied to an OR gate 390 which applies a clear signal to a three bit AFC sequence counter 392.
The A, B and C outputs of counter 392 are applied to a NAND gate 394, the output of which is applied as a clock through NAND gate 396 to counter 392. The C output of counter 392 is applied as a serial clock to the OR gate 384. The A and B outputs of counter 392 are applied through a NAND gate 398 and a NAND gate 400 and through an inverting buffer 402 to cause the generation of and AFC defeat signal.
An oscillator 404 generates clock signals which are applied to the clock input of a two bit scan counter 406. The NAND gate 388 generates a clear signal which is applied through gate 390 to the counter 392, and to the scan counter 406. The A and B outputs of counter 406 are applied to the decoder 372. The B output of counter 406 is applied as an input to gate 396, serving as the clock for counter 392.
Inputs and outputs of the output buffers 366 are applied through inverters as inputs to AND gates 408 and 410, the outputs of which are applied through inverters to an OR gate 412. The output of OR gate 412 is applied through an inverter to an input of gate 394. The output of oscillator 404 is applied through an inverter 414 to the inputs of NAND gates 416 and 418. The output of gate 416 is applied to an input of an OR gate 420 and to the input of a NAND gate 422. The output of gate 418 is applied to the second input of gate 420 and is applied to an input of a NAND gate 424. Gates 422 and 424 are interconnected in a latch configuration in order to provide up and down control signals to the counter 374.
In operation of the circuitry shown in FIG. 14, both sequential and parallel access channel selection may be accomplished. The local oscillator 404 drives the two bit scan counter 406 which is conventionally running. The two binary outputs from the counter 406 are applied to D _A and D _B terminals of the up/down counter 374 which are the parallel load data inputs of the counter 374. The outputs of the counter 406 are also applied to the two to four line decoder 372 which converts from the binary code to a single one out of four code. The outputs from the decoder 372 are applied to the output buffers 366.
The outputs of buffers 366 are high 25 percent of the time and are low 75 percent of the time. Thus, the four vertical lines of the pushbutton matrix array 360 are sequentially high when the system is in the parallel access mode. If the operator pushes one of the twenty buttons in the array 360, and one of the vertical lines is high, the corresponding horizontal line also goes high, which condition is applied through the input buffer 368 and through the five to three line encoder 370. The encoder 370 converts the signal into a binary code which corresponds to the three most significant bits of the address code and which is applied to the parallel load data inputs of the up/down counter 374. The gate 376 performs a NOR function on the zeroes on the inputs of the encoder 370 such that any input to the encoder 370 which goes low results in the corresponding three bit binary code being loaded into the counter 374. Additionally, at the same time, the two bit code applied at D _A and D _B is loaded into counter 374.
As long as the operator's finger remains on one of the pushbuttons in the array 360, a signal is generated through gates 376, 378 and 390 to clear the counter 392. Counter 392 and its associated circuitry thus operates in a similar manner as counter 202 in the circuit shown in FIG. 9. When the system is in the parallel mode, a logic one appears on line 430, and a zero thus appears at the output of gate 382. No clock signals are applied through gate 384 and inverter 386 to the up/down counter 374. The operation of the circuitry shown in FIG. 14 is thus similar to the operation of the circuitry shown in FIG. 9.
If it is desired to operate the system of FIG. 14 in the serial access mode, one of the buttons 362 or 364 is depressed in order to ground the respective vertical line through the array 360. Gate 408 or 410 detects the up/down mode by detecting the situation wherein the output buffer 366 commands the line B to go high, but when the down button 364 is depressed it cannot comply, thereby creating the down command. Similarly, gate 408 detects the up mode which occurs when the output buffer 366 commands the A line to go high, but the up button 362 is depressed, thereby grounding the line. The outputs of gates 408 and 410 are applied to gates 416 and 418 and Nanding with the narrow output pulse from the invertor 414 and the oscillator 404. The outputs of the gates 416 and 418 are applied to gate 420 which detects a logic zero on either of the gates in order to set the serial side of the latch comprising gates 380 and 382. Setting of the serial side of the latch enables clock signals to be applied through the gate 384 to the up/down counter 374 for operation of the circuit.
Other outputs of gates 408 are inverted and applied to gate 412 which detects a logic zero on either input. Detection of the logic zero by gate 412 causes the generation of the logic one which is inverted and utilized to momentarily depress, through gate 394, the application of clock signals to the counter 392. Unless counter 392 is cleared, the counter will attempt to start the AFC sequence. This operation just described is provided by the first pulse generated through the array 360 by operation of the up or down buttons 362 and 364.
In the serial mode, a latch comprising gates 380 and 382 applies a logic zero to line 430 in order to indicate to the decoder 372 that it is desired that all logic ones appear on the outputs A-D from the output buffers 366.
The latch comprising gates 380 and 382 enables application of clock pulses to counter 374 in the manner previously described. In addition, the latch opens gate 388, thereby enabling counter 392 and counter 406 to be cleared when receiving skip data. When no skip clock is available, gate 384 is opened in order to advance the counter 374 one count. Counter 374 thus operates to generate the five bit binary code on pins A-E.
If the channel selected by the operator is not a valid channel and it is desired to be skipped, a skip signal is applied through switch 434. The skip signal is large enough to overpower the circuitry shown in FIG. 14 in the same manner as the switches 362 and 364, such that the skip data flows back through line D of matrix 360 and line 436 to the OR gate 384. Gate 388 detects the skip signal and generates a logic zero, thereby reconstituting the skip signal in the serial mode. The logic zero from gate 388 clears the counter 392 and maintains the counter 406 in zero-zero state, preventing normal counting action. The latch comprising gates 380 and 382 has previously opened the gate 384 for operation in the serial channel selection or to receive the skip signals via lines 436.
When either the up button 362 or down button 364 is depressed, the counter 374 must be directed as to which direction to count. The output from either gate 416 or 418 sets one side of the latch comprising gates 422 and 424 in order to set the counter 374 in the desired count mode.
If the mode of operation of the circuit shown in FIG. 14 is changed from the serial access to the parallel access on a valid channel, no data is provided to reset counter 392. Counter 406 is scanning at this time, but is blocked by the decoder 372, and the action of line 430 from gate 380. When the operator presses one of the buttons in the array 360, the line is already high and is applied through the input buffers 368 to gate 376 in order to set the latch comprising gates 380 and 382 back to the parallel mode.
As noted, the selected vertical line in the array 360 is high 25 percent of the time and is low 75 percent of the time. The decoder 372 is noe open to decode the input data from the scan counter and to cause loading of the counter 374 with the correct data.
When the system shown in FIG. 14 is in the parallel access mode and the operator attempts to pick up an unprogrammed channel, the skip signal is applied to gate 384, which is not open and which prevents serial advance away from that channel. However, the system still performs the loading of data and gate 376 is energized such that the counter is loaded by a generated spike from gate 376. Thus, if the operator so desires, a channel that is not programmed may nevertheless be addressed.
Tuning Memory For Twenty Channel System
FIG. 15 is a schematic diagram of the tuning memory 143 (FIG. 8) for use with the circuitry shown in FIG. 14. The five binary address inputs generated from the circuitry shown in FIG. 14 or other means are applied to a five to 20 line decode 450 which applies the resulting word enable signals to a 12 bit 20 word tuning voltage RAM 452. The output of the RAM 452 is applied through multiplexing gates 453 to a 12 bit data shunt 454. The output of shunt 454 is applied to a 12 bit presettable ripple up/down counter 456. The output of counter 456 is applied to a 12 bit data comparator 458 which also receives the output from a 12 bit synchronous binary counter 460. The resulting output from the comparator 458 is applied through an invertor 461 to a D-flipflop 462 and an integrating filter 463 which generates the analog signal for control of the varactor diodes of the tuner 464.
A 1 MHz clock is applied to pin 465 to drive the synchronous binary counter 460. A signal of approximately 256 Hz is applied from the counter 460 to a count down frequency select circuit 466. The outputs from the circuit 466 apply a clock frequency to a tuning program generator 468 which applied clock and load signals to the counter 456 and which applies enable signals to the shunt 454. Operation of an up voltage programming button 470 and a down voltage programming button 472 operates a tuning mode timer 474 which generates fast or slow signals to the select circuit 466.
Output signals from the counter 456 are applied to the data multiplexing gates 453 for input to the RAM 452. Read or write signals are applied from the tuning program generator 468 to control the operation of the reading or writing of the RAM 452. The output from the counter 456 is also applied to a channel skip decode 478 which generates the channel skip output previously noted.
The decoder output from the address decode 450 is also applied to a band switch circuit 480 which generates three band switch control signals LVHF, HVHF and UHF which are applied to the varactor diodes in the manner previously described. In addition, when the output of the band switch 480 appears on a UHF output, a signal is applied via lead 482 to the frequency select circuit 466 in order to operate the slow clock mode of the select circuit 466.
Operation of the tuning memory of FIG. 15 is similar to the circuitry shown in FIG. 13, except that additional RAM storage is not required for band switching bits or skip bits. Thus, when it is desired to address signals to be stored in the RAM 452, a battery is connected to pin 486 to protect the memory of the RAM 452 and both buttons 470 annd 472 are depressed. Depression of both the buttons 470 and 472 for a brief period causes a shunt signal to be generated from the generator 468 to the 12 bit data shunt 454. This causes all logic zeroes to be applied to the output of the shunt 454. This action sets the RAM to the known all zero state. Subsequently, only the up button is depressed, and after a time interval such as 8 seconds, tuning mode timer 474 kicks into the fast mode and operates the count down frequency select 466 in the fast mode to apply a high clock frequency to the tuning program generator 468. When the first channel is detected by the operator, the operator removes the finger and the circuit moves into the slow mode such that the channel may be fine tuned by selective action of the tuning buttons. The tuning program generator then causes the desired address to be read and stored in the RAM 452.
When the operator desires to skip unused channels, both buttons 470 and 472 are depressed for a brief period at those channel locations and a zero appears on the output from the tuning program generator 468 and is detected by the 12 bit data shunt 454, causing twelve zeroes to appear as data. Therefore, all zeroes are entered into the RAM 452 at that location. The all zero data word generates a skip signal from the decoder 478 when that channel address is selected in subsequent operation.
As previously noted, the output words from the RAM 452 are applied through the shunt 454 to operate the counter 456. The outputs from counter 456 are applied to the comparator 458 along with the output from the counter 460. The comparator 458 converts the binary word stored in the RAM 452 into a duty cycle of a specific D.C. level. This duty cycle is detected by the flipflop 462 and is applied to the integrating filter 463 in order to generate the desired analog signal for control of the varactor diode tuner 464.
In order to more specifically illustrate the operation of the tuning memory shown in FIG. 15, FIGS. 16a and 16b illustrate a schematic logic diagram of the circuit shown in FIG. 15. An important aspect of the present invention is that the circuitry shown in FIG. 16 may be formed on a single semiconductor chip by the use of integrated injection logic techniques. A description of integrated injection logic may be found in the article "Integrated Injection Logic -- A New Approach to LSI", I.E.E.E. Journal of Solid-State Circuits, K. Hart and A. Slob, Vol. SC-7, No. 5, October, 1972. Thus, the five binary address inputs are applied to pins 500 and are applied through invertors to a five to twenty line decoder comprising NAND gates 502. The decoded outputs from the gates 502 are applied to a twenty word twelve bit RAM 504. For simplicity of illustration, the construction of RAM 504 is not completely shown, but one bit 506 of the RAM is illustrated in detail. The bit 506 is constructed from a plurality of interconnected transistors which generate WORD ENABLE, DATA IN, DATA OUT and DATA IN signals in the manner illustrated.
The output of the decode gates 502 are detected by NAND gates 508 and 510 in order to generate through buffers and through a NAND gate 512 the three band selection signals for the varactor diode tuner. These band selection signals control the selection of the low VHF, the high VHF and UHF bands.
The input and output from the RAM 504 is controlled by the data multiplexing gate 514 which comprises 12 stages of interconnected NAND gates 516 and 518. The read and write control signals are applied to the data multiplexing gates via lead 520, the read word being logic zero and the write word being logic one at the output of the invertor 522. The output from the data multiplexing gates is applied to the NAND gates 528 which comprise interconnections to counter 456. Counter 456 includes twelve stages each comprising a counter 526, NAND gates 528 and 530, AND gates 532 and 534 and OR gates 536. Up and down control signals are applied via lines 540 and 542. The up and down signals are generated by operation of the up and down voltage programming buttons 470 and 472 which are applied through NAND gates 544 and 546 connected in a latch configuration.
The twelve outputs from the counter 456 are applied to the twelve bit data comparator 458 (see FIG. 16a) which comprises twelve NAND gates 550. Inputs of NAND gates 550 also receive clock signals from the twelve bit synchronous counter 460 which comprises ten NAND gates 552 interconnected with twelve flipflops 554. Flip-flops 554 are driven by a 1 MHz clock signal applied to line 556.
The output from the gates 550 in the comparator 458 are applied to a NAND gate 558 which generates a data output on pin 560 which is applied to the D-flipflop and the integrator 463 which generates the analog signals of the invention.
The tuning program generator 468 comprises NAND gates 564 and 566 which receive up/down signals generated by voltage programming switches 470 and 472. The output of gate 564 is applied via lead 568 to the data shunt 454 (which is an input on NAND gates 528). The output of gate 566 is applied to D-flipflop 570, the outputs of which are connected to four interconnected flipflops 571. The Q and Q outputs of flipflops 571 are applied to NAND gates 5772, 573 and 574. The outputs of gates 572-574 generate clock, write/read and load signals. Outputs from the up and down switches 470 and 472 are also applied through a NAND gate 577 to a latch comprising NAND gates 578 and 580.
The count down frequency select circuit 466 comprises seven counter stages 590 which receive a signal of approximately 256 Hz from the counter 460 via lead 592. An output of approximately 2 Hz is applied via lead 594 to the input of a NAND gate 596. Other outputs from counter stages 590 are applied to the input of NAND gates 600, 602, 604 and 606. The outputs of gates 600-606 are applied to a NAND gate 608, the output of which applies a clock frequency via lead 609 to the D-flipflop 570.
A logic signal indicating that the UHF band has been selected by the output of gate 512 is applied via lead 610 to the inputs of gates 600 and 606. Indication of the presence of the UFH band causes the count down frequency select 466 to generate a slow clock frequency to the tuning program generator 468. The tuning program generator 468 is responsive to an up or down input from the output of gate 566 which allows a logic one on the clear line to start the count. After sixteen counts, or an 8 second delay, a logic one output is applied to lead 616 by the tuning mode timer, which comprises five stages 612, to shift the count down frequency select 466 to the fast mode for the coarse tuning feature.
Clock signals are applied from the count down frequency select 466 via leads 618 to the channel skip decode ciircuit 478. The clocks are applied to a NAND gate 620, the output of which is applied to a NAND gate 622. Outputs from the counter 456 are applied to the inputs of a NAND gate 624, the output of which is applied to a D-flipflop 626. The Q output of the D-flipflop 626 is applied to the NAND gate 622. The output from the gate 622 is buffered and is applied to pin 630 to generate the channel skip signal.
In operation of the tuning program generator 468 in FIG. 16b, if it is desired to skip a tuning position, the up and down buttons 470 and 472 are simultaneously depressed. The inverted outputs from the switches are logic ones and are applied to gate 564. Gate 577 also detects the logic ones and feeds, through an inverter, the latch comprising gates 578 and 580. The input of gate 578 is connected to the five-bit time delay counter comprising stages 612.
Due to the depression of the switches 470 and 472, a logic zero would be applied to the shunt line if not for the output of the latch gate 578. The tuning mode control counter 468 does not enter all zeroes until switches 470 and 472 have been depressed for a brief period, due to the clearing applied to the Q lines connected to the input of gate 578. After a predetermined time interval, the input of gate 578 goes to logic zero, thereby causing the output of gate 578 to become the logic one. Now the input conditions of gate 574 are satisfied and the shunt becomes enabled.
The latch comprising gates 578 and 580 debounces the signal from the switches 470 and 472. The outputs from switches 470 and 472 are sensed by gate 577. When either or both of the switches returns to ground, a logic one appears at the output of gate 577. The output is inverted to reset gate 580 of the latch, thereby removing a logic one from gate 564. This cycle is then required to start again during the next cycle of operation.
The counter stages 612 extend the fine tuning mode before going into the coarse mode. Gate 596 requires the counter to maintain counting in the fast mode after the 8 second time interval because of the feedback applied thereby. Gates 600-604 creat the generation of different fast and slow tuning speeds for UHF and VHF modes.
The operation of the circuits shown in FIGS. 15 and 16a-b may be further understood by reference to the waveforms shown in FIG. 17. FIG. 17a illustrates the depression of one of the switches 470 or 472. The waveform shown in FIG. 17b is the free clock signal generated from the NAND gate 566 and applied to the D-flipflop 570. The waveform shown in FIG. 17c is the Q output of the D-flipflop 570. The state diagram shown in FIG. 17d illustrates the states of the program counter comprising the four counter stages 571 in the tuning program generator 468. The waveform shown in FIG. 17e comprises the Q output of D-flipflop 571 which is applied to clear D-flipflop 570. The waveform of FIG. 17f is the load up/down signal generated by the output of NAND gate 572 and utilized to control the loading of the up/down counter 456. The waveform shown in FIG. 17g comprises the output of the NAND gate 573 which is applied via the clock line to the counter 456. The waveform shown in FIG. 17h comprises the RAM write signal which is applied from gate 574 to the data multiplexer gates 516 and 518 in order to command the RAM to write.
In normal operation, the shunt 454 is open and the counter 456 is continuously loaded and the RAM 504 is continuously read. When the write signal is generated as shown in FIG. 17h, the shunt is controlled and the load is disabled. The count up or down is generated as required and the write RAM, enable read, and enable load signals are generated by the tuning program generator 468.
When the waveform of FIG. 17a goes high due to depression of one of the buttons 470 or 472, and the free clock signals shown in FIG. 17b are high, the leading edge of the waveform of 17b transfers the data of FIG. 17a to the Q output of the flipflop 570. After a transition time of τ ₁ as shown in FIG. 17c, the time occurs for shifting of data.
Referring to the state diagram of FIG. 17d, during preset, the first three flipflops 571 are held high as shown in state 7. After the time interval τ ₂ , to enable operation of the flipflops, the next 500 KHz clock that is applied causes state transition to state zero as shown in FIG. 17d. Referring to FIG. 17f, the state seven is decoded by gate 572 which goes high to isolate the RAM from the up/down counter. The preset counter is then no longer parallel loading and is ready to accept the clock signals. State one is now decoded by gate 573 and the up/down counter is clocked with the data. States two, three and four shown in FIG. 17d are skipped to provide ripple time for the counter and state five is decoded by gate 574 (FIG. 17h) to execute the write instruction for the RAM. State six is not decoded to provide debounce protection. As soon as the circuitry enters state seven, gate 572 goes low and the inverted output of gate 572 goes high.
Referring to FIG. 17e, the output of the last flipflop 571 was high. After a τ ₃ delay, the output of the last flipflop 571 now goes low because of the inverted output from gate 572. This causes flipflop 570, after a time delay of τ ₄ , to provide a low output which is utilized to preset the remaining flipflops. Now the last flipflop 571, whose output just went low, after a time interval of τ ₅ goes high. This removes the clear from flip-flop 570 and the state of the circuitry recycles to the beginning.
If the operator still has his finger on one of the buttons 470 or 472, the next time that the clock shown in FIG. 17b goes high, the entire cycle is repeated. If the operator removes his finger from the buttons 470 or 472, the set is now fine tuned and the counter comprising the four stages 571 remains at state 7.
During a channel skip operation, whenever a logic one is applied on the Q output of the flipflop 626 in response to a zero from gate 624, the D-flipflop is clocked from the line 618 by the 32 Hz clock at the leading edge thereof. The Q output of the D-flipflop 626 follows the leading edge of the clock signals and follows the data from gate 624. The output of D-flipglop 626 is Nanded at gate 622 with the output of gate 620 and inverted to provide the desired output waveform. The resulting output comprises a negative going narrow pulse which is delayed to allow the RAM to settle, thereby enabling time for the circuitry to change the program counter. The remainder of the operation of the schematic circuitry shown in FIG. 16 is apparent from the previous description of FIGS. 15 and 13.
Neon Display for 16 Channel Tuning System
for driving the various channel-number displays in response to the signal generated by the address generators is disclosed in the U.S. patent application Ser. No. 508,968 filed Sept. 25, 1974 and assigned to the same assignee as the present application.
It will thus be seen that the present invention provided an improved solid state television tuning system. The present system is modular, thus enabling easy interchange of displays or channel selection switches without modification of the remainder of the circuitry. The present system does not require expensive potentiometers or bulky printed circuit board fabrication. Although the present invention has been described with respect to the tuning of the television set, it will be understood that the present circuitry is also useful for tuning of other broadcast receivers such as radio, cable television and the like. The circuitry shown in FIG. 13 required RAM storage of two bit words to provide band switch information. As noted, this band switch information is programmed by actuation of switches by the operator during initial programming of the circuitry. Another aspect of the present invention is a system wherein such programming by the operator is not required.
In such a system, a band switch logic circuit such as a band switch circuit 480 shown in FIG. 15, is connected to the circuitry of FIG. 19 to detect the contents of the ROM 704 and the RAM 706. The band switch logic circuitry would thus decode portions of the discrete address generated from the ROM 704 and RAM 706 to generate the band switching signals which are applied to the varactor diode tuner in the manner previously described. The logic circuitry could consist of simple comparison logic of two BCD decades of the display memory word, and could comprise as few as two OR gates and a connected NOR gate.

Whereas the present invention has been described with respect to specific embodiments thereof, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.