Left side vertical Unit 2: Teletext processing board TNP17170.
Left side vertical Unit 3: Video Processing + Tuning + Tuner board TNP17169.
Left side vertical Unit 1 : Sound and stereo decoder board TNP17263.
MAB8461P
8-Bit Microcontroller-Microcomputer - Use w/8080/85 periph,8-bit LED driver
Various
8-Bit Microcontrollers,LEDs,LED Drivers
Clock Frequency - Max. (Hz)=6.0M
Clock Frequency - Min. (Hz)=1.0M
Min Instruction Length (bits)=8
Max Instruction Length (bits)=16
Memory Addressing Range=8k
Number of Addressing Modes=5
On-Chip RAM (Bytes)=128
On-Chip ROM (bytes)=6k
Number of Interrupt Lines=2
No. of Non-Maskable Interrupts=0
Number of Maskable Interrupts=0
Number of I/O Lines=20
No. of I/O Ports=4
Vsup Nom.(V) Supply Voltage=5.0
Status=Discontinued
Package=DIP
Pins=28
Military=N
Technology=NMOS
TDA3562A (Philips)PAL/NTSC ONE-CHIP DECODER
DESCRIPTION
The TDA3562A is a monolithic IC designed as
decode PAL and/or NTSC colour television standards
and it combines all functions required for the
identification and demodulation of PAL and NTSC
signals.
.CHROMINANCE SIGNAL PROCESSOR
.LUMINANCE SIGNAL PROCESSING WITH
CLAMPING
.HORIZONTAL AND VERTICAL BLANKING
.LINEAR TRANSMISSION OF INSERTED
RGB SIGNALS
.LINEAR CONTRAST AND BRIGHTNESS
CONTROL ACTING ON INSERTED AND MATRIXED
SIGNALS
.AUTOMATIC CUT-OFF CONTROL
.NTSC HUE CONTROL
FEATURES
· A black-current stabilizer which
controls the black-currents of the
three electron-guns to a level low
enough to omit the black-level
adjustment
· Contrast control of inserted RGB
signals
· No black-level disturbance when
non-synchronized external RGB
signals are available on the inputs
· NTSC capability with hue control.
APPLICATIONS
· Teletext/broadcast antiope
· Channel number display.
GENERAL DESCRIPTION
It follows that the
external switches and filters which
are required for the TDA3562A are
not required for the TDA3566A.
There is no difference between the
amplitudes of the colour output
signals in the PAL or NTSC mode.
· The clamp capacitor at pins 10, 20
and 21 in the black-level
stabilization loop can be reduced to
100 nF provided the stability of the
loop is maintained. Loop stability
depends on complete application.
The clamp capacitors receive a
pre-bias voltage to avoid coloured
background during switch-on.
· The crystal oscillator circuit has
been changed to prevent parasitic
oscillations on the third overtone of
the crystal. Consequently the
optimum tuning capacitance must
be reduced to 10 pF.
· The hue control has been improved
(linear)
SAB3035 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)
GENERAL DESCRIPTION
The SAB3035 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver
FUNCTIONAL DESCRIPTION
The SAB3035 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).
The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50 l
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