The chassis MG3.1E is particularly complex with various ASIC's interconnected via I2C bus and a sophisticated Microprocessor CCU.
There is even a sub Woofer integrated in the chassis.
It was not easy to service and to understand even because of the complexity toghether with the very high features level.
MOTOROLA MC34067 HIGH PERFORMANCE ZERO VOLTAGE SWITCH RESONANT MODE CONTROLLER
The MC34067/MC33067 are high performance zero voltage switch
resonant mode controllers designed for off–line and dc–to–dc converter
applications that utilize frequency modulated constant off–time or constant
deadtime control. These integrated circuits feature a variable frequency
oscillator, a precise retriggerable one–shot timer, temperature compensated
reference, high gain wide bandwidth error amplifier, steering flip–flop, and
dual high current totem pole outputs ideally suited for driving power
Also included are protective features consisting of a high speed fault
comparator and latch, programmable soft–start circuitry, input undervoltage
lockout with selectable thresholds, and reference undervoltage lockout.
These devices are available in dual–in–line and surface mount packages.
• Zero Voltage Switch Resonant Mode Operation
• Variable Frequency Oscillator with a Control Range Exceeding 1000:1
• Precision One–Shot Timer for Controlled Off–Time
• Internally Trimmed Bandgap Reference
• 4.0 MHz Error Amplifier
• Dual High Current Totem Pole Outputs
• Selectable Undervoltage Lockout Thresholds with Hysteresis
• Enable Input
• Programmable Soft–Start Circuitry
• Low Startup Current for Off–Line Operation
As power supply designers have strived to increase power
conversion efficiency and reduce passive component size,
high frequency resonant mode power converters have
emerged as attractive alternatives to conventional
pulse–width modulated control. When compared to
pulse–width modulated converters, resonant mode control
offers several benefits including lower switching losses,
higher efficiency, lower EMI emission, and smaller size. A
new integrated circuit has been developed to support this
trend in power supply design. The MC34067 Resonant Mode
Controller is a high performance bipolar IC dedicated to
variable frequency power control at frequencies exceeding
1.0 MHz. This integrated circuit provides the features and
performance specifically for zero voltage switching resonant
mode power supply applications.
The primary purpose of the control chip is to provide a
fixed off–time to the gates of external power MOSFETs at a
repetition rate regulated by a feedback control loop.
Additional features of the IC ensure that system startup and
fault conditions are administered in a safe, controlled manner.
A simplified block diagram of the IC is shown on the front
page, which identifies the main functional blocks and the
block–to–block interconnects. Figure 13 is a detailed
functional diagram which accurately represents the internal
circuitry. The various functions can be divided into two
sections. The first section includes the primary control path
which produces precise output pulses at the desired
frequency. Included in this section are a variable frequency
Oscillator, a One–Shot, a pulse Steering Flip–Flop, a pair of
power MOSFET Drivers, and a wide bandwidth Error
Amplifier. The second section provides several peripheral
support functions including a voltage reference, undervoltage
lockout, Soft–Start circuit, and a fault detector.
Primary Control Path
The output pulse width and repetition rate are regulated
through the interaction of the variable frequency Oscillator,
One–Shot timer and Error Amplifier. The Oscillator triggers
the One–Shot which generates a pulse that is alternately
steered to a pair of totem pole output drivers by a toggle
Flip–Flop. The Error Amplifier monitors the output of the
regulator and modulates the frequency of the Oscillator. High
speed Schottky logic is used throughout the primary
control channel to minimize delays and enhance high
The characteristics of the variable frequency Oscillator are
crucial for precise controller performance at high operating
frequencies. In addition to triggering the One–Shot timer and
initiating the output deadtime, the oscillator also determines
the initial voltage for the one–shot capacitor. The Oscillator is
designed to operate at frequencies exceeding 1.0 MHz. The
Error Amplifier can control the oscillator frequency over a
1000:1 frequency range, and both the minimum and
maximum frequencies are easily and accurately
programmed by the proper selection of external components.
The pulse(tOS), generated by the Oscillator and One–Shot
timer is gated to dual totem–pole output drives by the
Steering Flip–Flop shown in Figure 16. Positive transitions of
tOS toggle the Flip–Flop, which causes the pulses to alternate
between Output A and Output B. The flip–flop is reset by the
undervoltage lockout circuit during startup to guarantee that
the first pulse appears at Output A.
The totem–pole output drivers are ideally suited for driving
power MOSFETs and are capable of sourcing and sinking
1.5 A. Rise and fall times are typically 20 ns when driving a
1.0 nF load. High source/sink capability in a totem–pole
driver normally increases the risk of high cross conduction
current during output transitions. The MC34067 utilizes a
unique design that virtually eliminates cross conduction, thus
controlling the chip power dissipation at high frequencies. A
separate power ground pin is provided to isolate the sensitive
analog circuitry from large transient currents.
PERIPHERAL SUPPORT FUNCTIONS
The MC34067 Resonant Controller provides a number of
support and protection functions including a precision voltage
reference, undervoltage lockout comparators, soft–start
circuitry, and a fault detector. These peripheral circuits
ensure that the power supply can be turned on and off in a
controlled manner and that the system will be quickly
disabled when a fault condition occurs.
Undervoltage Lockout and Voltage Reference
Separate undervoltage lockout comparators sense the
input VCC voltage and the regulated reference voltage as
illustrated in Figure 17. When VCC increases to the upper
threshold voltage, the VCC UVLO comparator enables the
Reference Regulator. After the Vref output of the Reference
Regulator rises to 4.2 V, the Vref UVLO comparator switches
the UVLO signal to a logic zero state enabling the primary
control path. Reducing VCC to the lower threshold voltage
causes the VCC UVLO comparator to disable the Reference
Regulator. The Vref UVLO comparator then switches the
UVLO output to a logic one state disabling the controller.
The Enable/UVLO Adjust pin allows the power supply
designer to select the VCC UVLO threshold voltages. When
this pin is open, the comparator switches the controller on at
16 V and off at 9.0 V. If this pin is connected to the VCC
terminal, the upper and lower thresholds are reduced to
9.0 V and 8.6 V, respectively. Forcing the Enable/UVLO
Adjust pin low will pull the VCC UVLO comparator input low
(through an internal diode) turning off the controller.
The Reference Regulator provides a precise 5.1 V
reference to internal circuitry and can deliver up to 10 mA to
external loads. The reference is trimmed to better than 2%
initial accuracy and includes active short circuit protection.
The high speed Fault Comparator and Latch illustrated in
Figure 18 can protect a power supply from destruction under
fault conditions. The Fault Input pin connects to the input of
the Fault Comparator. If this input exceeds the 1.0 V
threshold of the comparator, the Fault Latch is set and two
logic signals simultaneously disable the primary control path.
The signal labeled “Fault” at the output of the Fault
Comparator is connected directly to the output drivers. This
direct path reduces the propagation delay from the Fault
Input to the A and B outputs to typically 70 ns. The Fault
Latch output is OR’d with the UVLO output from the Vref
UVLO comparator to produce the logic output labeled
“UVLO+Fault”. This signal disables the Oscillator and
One–Shot by forcing both the COSC and CT capacitors to be
The Fault Latch is reset during startup by a logic “1” at the
UVLO output of the Vref UVLO comparator. The latch can
also be reset after startup by pulling the Enable/UVLO Adjust
pin momentarily low to disable the Reference Regulator.
The Soft–Start circuit shown in Figure 18 forces the
variable frequency Oscillator to start at the maximum
frequency and ramp downward until regulated by the
feedback control loop. The external capacitor at the
CSoft–Start terminal is initially discharged by the UVLO+Fault
signal. The low voltage on the capacitor passes through the
Soft–Start Buffer to hold the Error Amplifier output low. After
UVLO+Fault switches to a logic zero, the soft–start
capacitor is charged by a 9.0 mA current source. The buffer
allows the Error Amplifier output to follow the soft–start
capacitor until it is regulated by the Error Amplifier inputs. The
soft–start function is generally applicable to controllers
operating below resonance and can be disabled by simply
opening the CSoft–Start terminal.
The MC34067 is specifically designed for zero voltage
switching (ZVS) quasi–resonant converter (QRC)
applications. The IC is optimized for double–ended push–pull
or bridge type converters operating in continuous conduction
mode. Operation of this type of ZVS with resonant properties
is similar to standard push–pull or bridge circuits in that the
energy is transferred during the transistor on–time. The
difference is that a series resonant tank is usually introduced
to shape the voltage across the power transistor prior to
turn–on. The resonant tank in this topology is not used to
deliver energy to the output as is the case with zero current
switch topologies. When the power transistor is enabled the
voltage across it should already be zero, yielding minimal
switching loss. Figure 19 shows a timing diagram for a
half–bridge ZVS QRC. An application circuit is shown in
Figure 20. The circuit built is a dc to dc half–bridge converter
delivering 75 W to the output from a 48 V source.
When building a zero voltage switch (ZVS) circuit, the
objective is to waveshape the power transistor’s voltage
waveform so that the voltage across the transistor is zero
when the device is turned on. The purpose of the control IC is
to allow a resonant tank to waveshape the voltage across the
power transistor while still maintaining regulation. This is
accomplished by maintaining a fixed deadtime and by
varying the frequency; thus the effective duty cycle is
Primary side resonance can be used with ZVS circuits. In
the application circuit, the elements that make the resonant
tank are the primary leakage inductance of the transformer
(LL) and the average output capacitance (COSS) of a power
MOSFET (CR). The desired resonant frequency for the
application circuit is calculated by Equation 6:
L L 2CR
In the application circuit, the operating voltage is low and
the value of COSS versus Drain Voltage is known. Because
the COSS of a MOSFET changes with drain voltage, the value
of the CR is approximated as the average COSS of the
MOSFET. For the application circuit the average COSS can be
calculated by Equation 7:
measured at (7) CR
2 * COSS = in V
The MOSFET chosen fixes CR and that LL is adjusted to
achieve the desired resonant frequency.
However, the desired resonant frequency is less critical
than the leakage inductance. Figure 19 shows the primary
current ramping toward its peak value during the resonant
transition. During this time, there is circulating current
flowing through the secondary inductance, which effectively
makes the primary inductance appear shorted. Therefore,
the current through the primary will ramp to its peak value at
a rate controlled by the leakage inductance and the applied
voltage. Energy is not transferred to the secondary during
this stage, because the primary current has not overcome the
circulating current in the secondary. The larger the leakage
inductance, the longer it takes for the primary current to slew.
The practical effect of this is to lower the duty cycle, thus
reducing the operating range.
The maximum duty cycle is controlled by the leakage
inductance, not by the MC34067. The One–Shot in the
MC34067 only assures that the power switch is turned on
under a zero voltage condition. Adjust the one–shot period so
that the output switch is activated while the primary current is
slewing but before the current changes polarity. The resonant
stage should then be designed to be as long as the time for
the primary current to go to zero amps.
TDA9321H I2C-bus controlled TV input processor
The TDA9321H is an input processor for
‘High-end’ television receivers. It contains the following
· Multistandard IF amplifier with PLL demodulator
· QSS-IF amplifier and AM sound demodulator
· CVBS and Y/C switch with various inputs and outputs
· Multistandard colour decoder which can also decode the
PALplus helper signal
· Integrated baseband delay line (64 ms)
· Sync processor which generates the horizontal and
vertical drive pulses for the feature box
(100 Hz applications) or display processor
(50 Hz applications).
The supply voltage for the TDA9321H is 8 V.
· Multistandard Vision IF (VIF) circuit with Phase-Locked
Loop (PLL) demodulator
· Sound IF (SIF) amplifier with separate input for single
reference Quasi Split Sound (QSS) mode and separate
Automatic Gain Control (AGC) circuit
· AM demodulator without extra reference circuit
· Switchable group delay correction circuit which can be
used to compensate the group delay pre-correction of
the B/G TV standard in multistandard TV receivers
· Several (I2C-bus controlled) switch outputs which can
be used to switch external circuits such as sound traps,
· Flexible source selection circuit with 2 external
CVBS inputs, 2 Luminance (Y) and Chrominance (C)
(or additional CVBS) inputs and 2 independently
· Comb filter interface with CVBS output and Y/C input
· Integrated chrominance trap circuit
· Integrated luminance delay line with adjustable delay
· Integrated chrominance band-pass filter with switchable
· Multistandard colour decoder with 4 separate pins for
crystal connection and automatic search system
· PALplus helper demodulator
· Possible blanking of the helper signals for PALplus and
· Internal baseband delay line
· Two linear RGB inputs with fast blanking; the
RGB signals are converted to YUV signals before they
are supplied to the outputs; one of the RGB inputs can
also be used as YUV input
· Horizontal synchronization circuit with switchable time
constant for the PLL and Macrovision/subtitle gating
· Horizontal synchronization pulse output or clamping
· Vertical count-down circuit
· Vertical synchronization pulse output
· Two-level sandcastle pulse output
· I2C-bus control of various functions
· Low dissipation.
Vision IF amplifier
The VIF amplifier contains 3 AC-coupled control stages
with a total gain control range which is higher than 66 dB.
The sensitivity of the circuit is comparable with that of
The video signal is demodulated by a PLL carrier
regenerator. This circuit contains a frequency detector and
a phase detector. During acquisition the frequency
detector will tune the VCO to the correct frequency.
The initial adjustment of the oscillator is realized via the
I2C-bus. The switching between SECAM L and L’ can also
be realized via the I2C-bus. After lock-in the phase
detector controls the VCO so that a stable phase
relationship between the VCO and the input signal is
achieved. The VCO operates at twice the IF frequency.
The reference signal for the demodulator is obtained by
means of a frequency divider circuit. To get a good
performance for phase modulated carrier signals the
control speed of the PLL can be increased by bit FFI.
The AFC output is obtained by using the VCO control
voltage of the PLL and can be read via the I2C-bus.
For fast search tuning systems the window of the AFC can
be increased with a factor 3. The setting is realized with
The AGC detector operates on top-sync and
top-white-level. The demodulation polarity is switched via
the I2C-bus. The AGC detector time constant capacitor is
connected externally; this is mainly because of the
flexibility of the application. The time constant of the AGC
system during positive modulation is rather long, this is to
avoid visible variations of the signal amplitude. To improve
the speed of the AGC system a circuit has been included
which detects whether the AGC detector is activated every
frame period. When, during 3 field periods, no action is
detected the speed of the system is increased. For signals
without peak white information the system switches
automatically to a gated black level AGC. Because a black
level clamp pulse is required for this mode of operation the
circuit will only switch to black level AGC in the internal
The circuits contain a video identification (ident) circuit
which is independent of the synchronization circuit.
Therefore search tuning is possible when the display
section of the receiver is used as a monitor. However, this
ident circuit cannot be made as sensitive as the slower
sync ident circuit (bit SL). It is recommended to use both
ident outputs to obtain a reliable search system. The ident
output is supplied to the tuning system via the I2C-bus.
The input of the ident circuit is connected to pin 14
(see Fig.3). This has the advantage that the ident circuit
can also be made operative when a scrambled signal is
received (descrambler connected between pins 10
and 14). A second advantage is that the ident circuit can
be used when the VIF amplifier is not used (e.g. with
built-in satellite tuners). The video ident circuit can also be
used to identify the selected CBVS or Y/C signal.
The switching between the 2 modes can be realized with
The TDA9321H contains a group delay correction circuit
which can be switched between the BG and a flat group
delay response characteristic. This has the advantage that
in multistandard receivers no compromise has to be made
for the choice of the SAW filter. Both the input and output
of the group delay correction circuit are externally
available so that the sound trap can be connected
between the VIF output and the group delay correction
input. The output signal of the correction circuit can be
supplied to the internal video processing circuit and to the
external SCART plug.
The IC has several (I2C-bus controlled) output ports which
can be used to switch sound traps or other external
When the VIF amplifier is not used the complete VIF
amplifier can be switched off with bit IFO.
The SIF amplifier is similar to the VIF amplifier and has a
gain control range of approximately 66 dB. The AGC
circuit is related to the SIF carrier levels (average level of
AM or FM carriers) and ensures a constant signal
amplitude to the AM demodulator and the QSS mixer.
The single reference QSS mixer is realized by a multiplier.
In this multiplier the SIF signal is converted to the
intercarrier frequency by mixing it with the regenerated
picture carrier from the VCO. The mixer output signal is
supplied to the output via a high-pass filter for attenuation
of the residual video signals. With this system a high
performance hi-fi stereo sound processing can be
The AM sound demodulator is realized by a multiplier.
The modulated SIF signal is multiplied in phase with the
limited SIF signal. The demodulator output signal is
supplied to the output via a low-pass filter for attenuation
of the carrier harmonics.
The circuit has 3 CVBS inputs (1 internal and 2 externals)
and 2 Y/C inputs. The Y/C inputs can also be used as
additional CVBS inputs. The switch configuration is given
in Fig.3. The various sources can be selected via the
The circuit can be set in a mode in which it automatically
detects whether a CVBS or a Y/C signal is supplied to the
Y/C inputs. In this mode the TV-standard identification first
takes place on the added Y/CVBS and the C input signal.
Then both chrominance input signal amplitudes are
checked once and the input signal with the highest burst
signal amplitude is selected. The result of the detection
can be read via the I2C-bus.
The IC has 2 inputs (AV1 and AV2) which can be used to
read the status levels of pin 8 of the SCART plug.
The information is available in the output status byte 02 in
bits D0 to D3.
The 3 outputs of the video switches (CVBSCF, CVBSTXT
and CVBSPIP) can be independently switched to the
various input signals. The names are just arbitrary and it is,
for instance, possible to use the CVBSCF signal to drive
the comb filter and the teletext decoder in parallel and to
supply the CVBSTXT signal to the SCART plug (via an
For comb filter interfacing the circuit has the CVBSCF
output, a 3rd Y/C input, a reference signal output REFO
and 2 control pins (SYS1 and SYS2) which switch the
comb filter to the standard of the incoming signal (as
detected by the ident circuit of the colour decoder). When
a signal is recognized which can be combed and the comb
filter is enabled by bit ECMB the Y/C signals coming from
the comb filter are automatically selected. This is indicated
via bit CMB in output status byte 02 (D5). For signals
which cannot be combed (such as SECAM or
black-to-white signals) the Y/C signals coming from the
comb filter are not selected.
Chrominance and luminance processing
The circuits contain a chrominance band-pass, a SECAM
cloche filter and a chrominance trap circuit. The filters are
realized by means of gyrator circuits and they are
automatically calibrated by comparing the tuning
frequency with the crystal frequency of the decoder.
The luminance delay line is also realized by means of
gyrator circuits. The centre frequency of the chrominance
band-pass filter is switchable via the I2C-bus so that the
performance can be optimized for ‘front-end’ signals and
external CVBS signals.
The luminance output signal which is derived from the
incoming CVBS or Y/C signal can be varied in amplitude
by means of a separate gain setting control via the I2C-bus
control bits GAI1 and GAI0. The gain variation which can
be realized with these bits is -1 to +2 dB.
The colour decoder can decode PAL, NTSC and SECAM
signals. The PAL/NTSC decoder contains an
alignment-free crystal oscillator with 4 separate pins for
crystal connection, a killer circuit and two colour difference
demodulators. The 90° phase shift for the reference signal
is produced internally.
Because it is possible to connect 4 different crystals to the
colour decoder, all colour standards can be decoded
without external switching circuits. Which crystals are
connected to the decoder must be indicated via the
I2C-bus. The crystal connection pins which are not used
must be left open-circuit.
The horizontal oscillator is calibrated by means of the
crystal frequency of the colour PLL. For a reliable
calibration it is very important that the crystal indication
bits XA to XD are not corrupted. For this reason
bits XA to XD can be read in the output bytes so that the
software can check the I2C-bus transmission.
The IC contains an Automatic Colour Limiting (ACL) circuit
which is switchable via the I2C-bus and prevents
oversaturation occuring when signals with a high
chrominance-to-burst ratio are received. The ACL circuit is
designed such that it only reduces the chrominance signal
and not the burst signal. This has the advantage that the
colour sensitivity is not affected by this function. The ACL
function is mainly intended for NTSC signals but it can also
be used for PAL signals. For SECAM signals the ACL
function should be switched off.
The SECAM decoder contains an auto-calibrating PLL
demodulator which has two references: the 4.43 MHz
subcarrier frequency which is obtained from the crystal
oscillator which is used to tune the PLL to the desired
free-running frequency and the band gap reference to
obtain the correct absolute value of the output signal.
The VCO of the PLL is calibrated during each vertical
blanking period, when the IC is in search or SECAM mode.
The circuit can also decode the PALplus helper signal and
can insert the various reference signals: set-ups and
timing signals which are required for the PALplus decoder
The baseband delay line (TDA4665 function) is integrated.
RGB switch and matrix
The IC has 2 RGB inputs with fast switching. The switching
of the various sourcing is controlled via the I2C-bus and the
condition of the switch inputs can be read from the I2C-bus
status bytes. If the RGB signals are not synchronous with
the selected decoder input signal, an external clamp pulse
has to be supplied to the HA/CLP input. The IC must be set
in this mode via the I2C-bus. In that case the vertical pulse
is suppressed by switching the VA output in a
When an external RGB signal is mixed with the internal
YUV signal it is necessary to switch-off the PALplus
demodulation. To detect the presence of a fast blanking a
circuit is added which forces bits MACP and HD to zero if
a blanking pulse is detected in 2 consecutive lines. This
system is chosen to prevent switching-off at every spike
which is detected on the fast blanking input.
The IC has the possibility to use the RGB1 input as YUV
input. This function can be enabled by means of bit YUV in
subaddress 0A (D3). When switched to the YUV input the
input signals must have the same amplitude and polarity
as the YUV output signals. The Y signal has to be supplied
to the GI1 input, the U signal to the BI1 input and the
V signal to the RI1 input.
The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage which operates at
50% of the amplitude. The separated sync pulses are fed
to the phase detector and to the coincidence detector. This
coincidence detector is used to detect whether the line
oscillator is synchronized and can also be used for
transmitter identification. This circuit can be made less
sensitive with bit STM. This mode can be used during
search tuning to avoid the tuning system stopping at very
weak input signals. The PLL has a very high statical
steepness so that the phase of the picture is independent
of the line frequency.
For the horizontal output pulse 2 conditions are possible:
· An HA pulse which has a phase and width which is
identical to the incoming horizontal sync pulse
· A clamp pulse (CLP) which has a phase and width which
is identical to the clamp pulse in the sandcastle pulse.
The HA/CLP signal is generated by means of an oscillator
which is running at a frequency of 440 ´ fhor. Its frequency
is divided by 440 to lock the first loop to the incoming
signal. The time constant of the loop can be forced by the
I2C-bus (fast or slow).
If required the IC can select the time constant depending
on the noise content of the incoming video signal.
The free-running frequency of the oscillator is determined
by a digital control circuit which is locked to the reference
signal of the colour decoder. When the IC is switched on
the HA/CLP is suppressed and the oscillator is calibrated
as soon as all subaddress bytes have been sent. When the
frequency of the oscillator is correct the HA/CLP signal is
switched on again. When the coincidence detector
indicates an out-of-lock situation the calibration procedure
The VA pulse is obtained via a vertical count-down circuit.
The count-down circuit has various windows depending on
the incoming signal (50 or 60 Hz standard or
non-standard). The count-down circuit can be forced in
various modes via the I2C-bus. To obtain short switching
times of the count-down circuit during a channel change
the divider can be forced in the search window by means
of bit NCIN.
SAA4961 Integrated multistandard comb filter
The SAA4961 is an adaptive alignment-free one chip
comb filter compatible with both PAL and NTSC systems
and provides high performance in Y/C separation.
· One chip adaptive multistandard comb filter
· Time discrete but continuous amplitude signal
processing with analog interfaces
· Internal delay lines, filters, clock processing and signal
· No hanging dots or residual cross colour on vertical
· Few external components.
The multistandard comb filter processes the video
standards PAL B, G, H, M, N and NTSC M. PAL D and I
signals can also be processed but with the drawback of a
slightly reduced bandwidth.
For SECAM and SVHS signals the input signals can be
bypassed to the output without processing by selecting the
A sync separation circuit is incorporated to generate
control signals for the internal clock processing. With a
sync compression of up to 12 dB the sync separator works
properly (see Fig.4).
The IC is controlled via six pins:
1. BYP forces the IC into the BYPASS-mode (comb filter
2. SSYN defines whether the COMB-mode is entered
synchronously or not and defines the polarity of the
3. SYS1 selects the video standard
4. SYS2 selects the video standard
5. FSCSW selects the reference frequency fsc or 2 ´ fsc
6. LPFION enables the internal pre-filter.
It is possible to select the following modes of operation:
COMB-mode: luminance and chrominance comb filter
function active if BYPASS-mode not active.
BYPASS-mode: signal processing not active, all clocks
inactive, Cext (pin 10) is bypassed to CO (pin 12) and
Yext/CVBS (pin 17) is bypassed to YO (pin 14) and
CVBSO (pin 15). This mode is forced via BYP (pin 3).
If the stimulus of the mode is changed, the IC is following
the new mode after the stabilization time given in Table 1.
Table 1 Stabilization time after mode change
The mode change from BYPASS to COMB depends on
SSYN (pin 6) and can be asynchronous or synchronous
related to the vertical pulse. The mode change from
COMB to BYPASS is always performed asynchronously.
COMB-mode to BYPASS-mode 1 line
BYPASS-mode to COMB-mode 1 field
FSC (PIN 1)
Input for the reference frequency fsc (see note 2 of Chapter
“Characteristics”) or 2 ´ fsc. For SECAM standard signals
the best signal performance in BYPASS-mode is achieved
by switching the FSC input signal off externally.
BYP (PIN 3)
Input signal that controls the operation mode. A low-pass
filter is added to the input for suppression of subcarrier
frequencies. Thus applications are supported where the
operation mode (COMB or BYPASS) is controlled by the
DC-level of the FSC input signal at pin 1. For those
applications the BYP input can be externally connected to
FSC (pin 1).
Depending on SSYN (pin 6) the function of BYP can be
adapted to a certain application with respect to the polarity
of the logic level and with respect to the behaviour when
entering the COMB-mode.
Depending on SSYN the BYP input can be either inverted
The PLL and the clock processing are always stopped if
the selected level for BYPASS is applied to BYP
(independent of the vertical pulse).
REFBP (PIN 5)
Decoupling capacitor for the band-pass filter reference
SSYN (PIN 6)
Input signal that controls the function of BYP (pin 3).
VCCA, VCCO, VDDD AND VCCPLL (PINS 7, 8, 22 AND 27)
AGND, OGND, DGND AND PLLGND (PINS 9, 11,
21 AND 26)
Ground connection. AGND is used as signal reference for
all analog input and output signals.
Cext (PIN 10)
Input for an external chrominance signal which is
correlated to the external VBS signal.
CO (PIN 12)
Chrominance output signal. This output can be switched
between the comb filtered chrominance from the CVBS
signal and the external chrominance signal from the input
Cext if the IC is forced into BYPASS-mode.
FSCSW (PIN 13)
Input signal to select between fsc or 2 ´ fsc as reference at
the FSC input pin.
YO (PIN 14)
VBS output signal. This output can be switched between
the comb filtered luminance signal (including
synchronization) and the external (C)VBS signal from the
input Yext/CVBS. In COMB-mode the output signal is
delayed by 2 lines (1 line at NTSC) and by an additional
CVBSO (PIN 15)
CVBS output signal directly from the input in
BYPASS-mode or delayed by the signal processing time
of 2 lines (1 line at NTSC) and an additional processing
Yext/CVBS (PIN 17)
Input for the CVBS signal or for an external VBS signal.
LPFION (PIN 18)
Input signal to disable the internal pre-filter LPFI.
CSY (PIN 19)
Sync top capacitor for the sync separator.
SYS1 AND SYS2 (PINS 20 AND 23)
System switch input signals to adapt the signal processing
to the different CVBS standards.
Internal functional description
SWITCHED CAPACITOR DELAY LINE
Delays the CVBS input signal by 2 lines and 4 lines
(all PAL standards) or by 1 line and 2 lines (NTSC
standard). Input signals for the delay lines are the CVBS
signal, the clock CL3 (3 ´ fsc), the control signal HSEL and
the standard selection signal SYSPAL.
Output signals are the non-delayed, the 2-line delayed and
the 4-line delayed CVBS signal (PAL) or the 1-line delayed
and the 2-line delayed CVBS signal (NTSC).
SWITCHED CAPACITOR BAND-PASS FILTERS (BPFS)
The comb filter input BPFs attenuate the low frequencies
to guarantee a correct signal processing within the logical
The comb filter output BPF reduces the alias components
that are the result of the non-linear signal processing within
the logical comb filter.
LOGICAL COMB FILTER
Separates the chrominance from the band-pass filtered
Compensates the internal processing time of the
band-pass filters and the logical comb filter section.
The comb filtered luminance output signal is obtained by
adding the delayed CVBS signal and the inverted comb
filtered chrominance signal.
LOW-PASS FILTER INPUT (LPFI)
Analog input low-pass filter to reduce the outband
frequencies of EMC. The input low-pass filter is included in
the signal path but it can be switched off via the input
LOW-PASS FILTER OUTPUTS (LPFO1 AND LPFO2)
Two different types of output low-pass filters (LPFO1 and
LPFO2) are necessary to get equal signal delays within the
luminance path and the chrominance path (important for
good transient behaviour). The low-pass output filter type
LPFO1 is used for the luminance output while LPFO2 is
used for the chrominance output. The filters are analog 3rd
order elliptic low-pass filters that convert the output signals
from the time discrete to the time continuous domain
Automatic tuning of the low-pass filters is achieved by
adjusting the filter delays. The control information for all
filters (CONT1 and CONT2) is derived from a built-in
reference filter (LPFO1-type) that is part of a control loop.
The control loop tunes the reference filter delay and thus
all other filter delays to a time constant derived from the
system clock CL3.
CONTROL AND CLOCK PROCESSING (CLOCK CONTROL)
The control and clock processing block (see Fig.9)
consists of the sub-blocks PLL, the clock processing and
the mode control. The PLL and the clock processing are
released for operation if the input level at BYP selects the
Main tasks of the control and clock processing are:
· Clock generation of system clock CL3
· Delay line start control
· Mode control.
The signal processing is based on a 3 ´ fsc system clock
(CL3), that is generated by the clock processing from the
fsc signal at FSC (pin 1) via a PLL. Because the subcarrier
frequency divided by the line frequency results not in an
integer value a clock phase correction of 180° is necessary
every second line for PAL standards or every line for
NTSC standard. The clock phase correction is controlled
by the input signals horizontal sync. Additionally the delay
line start is synchronized once a field to the input signals
horizontal sync. The 25 Hz PAL offset is corrected in this
The PLL provides a master clock MCK of 6 ´ fsc, which is
locked to the subcarrier frequency at FSC (pin 1).
The system clock CL3 (3 ´ fsc) is obtained from MCK by a
divide-by-two circuit. The 180° phase shift is generated by
stopping the divide-by-two circuit for one MCK clock cycle.
The generated clock is a pseudo-line-locked clock that is
referenced to fsc. The sync separator generates the
necessary signals HDET and VDET indicating the line (H)
and the field (V) sync periods.
The current mode of operation (BYPASS or COMB) is
external readable via COMBENA (pin 25).
The input signals of the control and clock processing
(CLOCK CONTROL) are:
HDET: analog horizontal pulse from sync separator
VDET: analog vertical pulse from sync separator
FSC: subcarrier frequency (fsc or 2 ´ fsc)
FSCSW: reference frequency selection
BYP: BYPASS control signal
SSYN: vertical synchronous mode selection for BYP
and polarity selection of BYP.
The output signals are:
CL3: system clock (3 ´ fsc)
HSEL: line start signals for the delay lines
STOPS: forces the comb filter via the switches S2A,
S2B and S2C into the BYPASS-mode (always
asynchronous) or COMB-mode (synchronous or
asynchronous with VINT; depending on SSYN)
COMBENA: HIGH during COMB-mode; otherwise
HORIZONTAL AND VERTICAL SYNC SEPARATOR
A built-in sync separator circuit generates the HDET and
VDET signals from the Yext/CVBS input signal. This circuit
is still operating properly at input signals with a 12 dB
attenuated sync in a normal 700 mV black-to-white video
The black level clamping of the video input signal is
performed by the sync separator stage. The clamping level
is nearly adequate to the voltage at REFDL (pin 24).
SIGNAL SWITCH S1
The switch is included to bypass the low-pass input filter.
For the CVBS input of the delay line block two signals can
be selected via the slow signal switch S1.
SOUND PROCESSING WITH MSP3400C
Multistandard Sound Processor
Release Notes: The hardware description in this
document is valid for the MSP 3400C – C8 and newer
codes. Revision bars indicate significant changes
to the previous version.
The MSP 3400C is designed as single-chip Multistandard
Sound Processor for applications in analog and
digital TV sets, satellite receivers and video recorders.
The MSP-family, which is based on the MSP 2400, demonstrates
the progressive development towards highly
integrated multi-functional ICs.
The MSP 3400C, again, improves function integration:
The full TV sound processing, starting with analog
sound IF signal-in, down to processed analog AF-out, is
performed in a single chip. The IC is produced in 0.8 mm
CMOS technology, combined with high performance
digital signal processing.
The MSP 3400C 0.8 m CMOS version is fully pin and
software compatible to the 1.0 m MSP 3400 and MSP
3410. The main difference between the MSP 3400C and
the MSP 3410, consists of the MSP 3410 being able to
decode NICAM signals.
2. Features of the MSP 3400C:
2.1. Features of the Demodulator and Decoder
The MSP 3400C is designed to perform demodulation
of FM-mono TV sound and two carrier FM systems according
to the German or Korean terrestrial specs. With
certain constraints, it is also possible to do AM-demodulation
according to the SECAM system. Alternatively, the
satellite specs can be processed with the MSP 3400C.
For FM carrier detection in satellite operation, the AMdemodulation
offers a powerful feature to calculate the
carrier field strength, which can be used for automatic
search algorithms. So, the IC facilitates a first step towards
multistandard capability with its very flexible
application and may be used in TV-sets, satellite tuners,
and video recorders.
The MSP 3400C facilitates profitable multistandard capability,
offering the following advantages:
– two selectable analog inputs (TV and SAT-IF sources)
– Automatic Gain Control (AGC) for analog input: input
range: 0.14 – 3 Vpp
– integrated A/D converter for sound-IF inputs
– all demodulation and filtering is performed on chip and
is individually programmable
– no external filter hardware is required
– only one crystal clock (18.432 MHz) is necessary
– FM carrier level calculation for automatic search algorithms
and carrier mute function
– high deviation FM-mono mode (max. deviation:
approx. 360 kHz)
2.2. Features of the DSP-Section
– flexible selection of audio sources to be processed
– digital input and output interfaces via I2S-Bus for external
DSP-processors, surround sound, ADR etc.
– digital interface to process ADR (Astra Digital Radio)
together with DRP 3510 A
– performance of all deemphasis systems including
adaptive Wegener Panda 1 without external components
– digitally performed FM-identification decoding and dematrixing
– digital baseband processing: volume, bass, treble,
5-band equalizer, loudness, pseudostereo, and basewidth
– simple controlling of volume, bass, treble, equalizer
– increased audio bandwidth for FM-Audio-signals
(20 Hz – 15 kHz, 1 dB)
2.3. Features of the Analog Section
– three selectable analog pairs of audio baseband inputs
(= three SCART inputs)
input level: 32 V RMS,
input impedance: .25 kW
– one selectable analog mono input (i.e. AM sound),
input level: 32 V RMS,
input impedance: .10 kW
– two high quality A/D converters, S/N-Ratio: .85 dB
– 20 Hz to 20 kHz Bandwidth for SCART-to-SCARTCopy
– MAIN (loudspeaker) and AUX (headphones): two
pairs of 4-fold oversampled D/A-converters
output level per channel: max. 1.4 V RMS
output resistance: max. 5 kW
S/N-Ratio: .85 dB at maximum volume
max. noise voltage in mute mode: 310 mV (BW: 20 Hz
– one pair of four-fold oversampled D/A-converters supplying
two selectable pairs of SCART-Outputs. Output
level per channel: max. 2 V RMS, output resistance:
max. 0.5 kW, S/N-Ratio: .85 dB
(20 Hz...16 kHz).
SAA7712H Sound effects DSP
1.1 Hardware features
· Digital Signal Processor (DSP) core:
– 18 bits data width, 12 bits coefficient width
– Separate X, Y and P memories (both 384 bytes word
XRAM and YRAM, 3 kbytes word PROM)
– 1 kbytes delay line memory suited for Dolby Pro
– 2 slave 18-bit digital stereo inputs: I2S-bus and
LSB-justified serial formats
– 2 master 18-bit digital stereo inputs: I2S-bus and
LSB-justified serial formats.
– 4 DACs with 4-times oversampling and noise
shaping, fed to 4 output pins and configurable from
the DSP program, as left, right, front and surround
channels of a Dolby Pro Logic Surround system
– 2 master 18-bit digital stereo outputs: I2S-bus and
LSB-justified serial formats.
· 4-channel 5-band or 2-channel 10-band
I2C-bus controlled parametric equalizer
· I2C-bus microcontroller interface for:
– Access to full X and Y memory space
– Control of hardware settings: selectors,
programmable clock generations, etc.
· Controllable Phase-Locked Loop (PLL) to generate the
high frequency DSP clock from common fundamental
· 3.3 V process with 3.3 or 5 V digital periphery:
– 3.3 or 5 V I2S-bus and I2C-bus microcontroller
· Operating temperature range from 0 to 70 °C.
1.2 Software features
· Dolby Pro Logic Surround/Dolby 3 stereo:
Trademark of Dolby Laboratories Licensing Corporation
· Noise generation: A pink noise generator is included
for installation of the Dolby Pro Logic/Dolby 3 stereo
· Hall/Matrix Surround: When no Dolby Pro Logic
Surround source material is available then this mode
can be used to produce a signal in the surround channel
· Incredible Surround (222-IS): This algorithm expands
the stereo width (stereo expander). This is intended to
be used when the 2 speakers are placed close together
(TV set and Midi set).
· Robust Incredible Surround (222-RIS): Same as
incredible surround only an alternative algorithm
· 3D Surround (422) or Incredible Virtual Surround:
Dolby Pro Logic Surround reproduced by 2 speakers
(L and R)
· IS-3D Surround (422-IS): Same as 3D Surround (422)
only with extra stereo width expander on left and right
· RIS-3D Surround (422-RIS): Same as IS-3D Surround
(422) with alternative algorithm
· 3D Surround (423) or Incredible Virtual Surround:
Dolby Pro Logic Surround reproduced by 3 speakers
(L, C and R)
· IS-3D Surround (423-IS): Same as 3D Surround (423)
only with extra stereo width expander on left and right
· RIS-3D Surround (423-RIS): Same as IS-3D Surround
(423-IS) with alternative algorithm.
· Voice cancelling (karaoke): Rejects voice out of
source material, mainly intended to be used with
karaoke. Several karaoke modes available in stereo
mode and in Dolby Pro Logic mode, such as (auto) voice
cancel, (auto) centre voice cancel, (auto) multi left and
(auto) multi right.
· Microphone mix modes (karaoke): Mono microphone
mixed to left, right and centre channel
· Spectrum analysis: 3-band spectrum analyser is
· Dolby B: Both a Dolby B encoder as well as a Dolby B
decoder is implemented
· 2 Room solution: In all modes not requiring more than
2 output channels (stereo and karaoke incredible
surround) it is also possible to feed the source signal to
the other 2 output channels (with same processed or
not processed signal)
· Dynamic Bass Enhancement (DBE): Dynamic bass
enhancement generates a sub-woofer channel, which is
either a separate output or is added to the front channels
· Volume processing: Independent volume processing
of all 4 output channels
· AC-3/MPEG-2: Inputs available intended to be used
with an AC-3/MPEG-2 co-processor. In this mode the
SAA7712H can be used as post-processor.
· Output redirection: Several output configurations are
possible (normal 4 channel, special 4 + 2 channel,
record 2 + 2 channel, 6 or 6 + 2 channel).
Depending on the sample frequency several combinations
of the above mentioned features are possible.
The SAA7712H can be used in TV sets with:
· Dolby Pro Logic Surround, incredible surround,
3D Surround and advanced acoustics processing
· Multi-channel sound decoding (AC-3 and MPEG-2) on a
co-processor. The SAA7712H can be used for
3 GENERAL DESCRIPTION
The SAA7712H provides for digital signal processing
power in TV systems and home theatre systems.
A DSP core is equipped with digital inputs and outputs, a
5-band parametric equalizer accelerator, a digital
co-processor interface and a delay line memory. This
architecture accommodates on-chip standard sound
processing, incredible surround, Dolby Pro Logic Surround
and other surround sound processing algorithms.
The architecture also supports co-processing, e.g. to add
to the processing power of the internal DSP core or for
multi-channel surround decoding.
All settings and parameters are controlled by an I2C-bus
interface. The available interfaces support a high
The DSP core communicates over 32 dedicated registers.
The selected digital input is master for the data rate of the
DSP core. This input can be selected among 2 slave
I2S-bus inputs. The 4 outputs from the core are passed
through 4 DACs and then routed to 4 output pins.
Two master I2S-bus outputs and two master I2S-bus
inputs can serve as an I2S-bus co-processor interface.
Eight of the remaining registers are used for
communication with the hardware equalizer, and eight for
communication with the delay line memory.
All I2S-bus inputs and outputs support the Philips I2S-bus
format as well as 16, 18 and 20-bit LSB-justified formats.
8.1 Analog outputs
8.1.1 ANALOG OUTPUT CIRCUIT
Depending on the configuration of the equalizer sections,
the SAA7712H has 2 or 4 analog outputs which are
supplied by the same power supply. Each of these outputs
has a voltage and a current pin (see Fig.3). The signals are
available on 2 outputs (OUT0 and OUT1), or 4 outputs
(OUT0, OUT1, OUT2 and OUT3).
The sample rate (fs) of the selected source is the frame
rate of the DSP. The word clock for the upsample filter and
the clock for the DACs, at 4fs, are derived internally from
the word select of the selected audio source.
Each of the four low noise high dynamic range DACs
consists of a signed-magnitude DAC with current output,
followed by a buffer operational amplifier.
8.1.4 UPSAMPLE FILTER
To reduce spectral components above the audio band, a
fixed 4 times oversampling and interpolating digital filter is
used. The filters give an out-of-audio-band attenuation of
at least 29 dB. The filter is followed by a first-order noise
shaper to expand the dynamic range to more than 105 dB.
The band around multiples of the sample frequency of the
DAC (4fs) is not affected by the digital filter. A capacitor
must be added in parallel with the DAC output amplifier to
attenuate this out-of-band noise further to an acceptable
In Fig.4 the overall frequency spectrum at the DAC audio
output without external capacitor or low-pass filter for the
audio sampling frequencies of 38 kHz is shown. In Fig.5
the detailed spectrum around fs is shown for an fs of
38, 44.1 and 48 kHz. The pass band bandwidth (-3 dB) is
The signed-magnitude noise-shaped DAC has a dynamic
range in excess of 100 dB. The signal-to-noise ratio of the
audio output at full-scale is determined by the word length
of the converter. The noise at low outputs is fully
determined by the noise performance of the DAC. Since it
is a signed-magnitude type, the noise at digital silence is
also low. As a disadvantage, the total THD is higher than
POWER-ON MUTE (POM)
To avoid any uncontrolled noise at the audio outputs after
power-on of the IC, the reference current source of the
DAC is switched off. The capacitor on pin POM
determines the time after which this current has a soft
switch-on. So at power-on the current audio signal outputs
are always muted. The loading of the external capacitor is
done in two stages via two different current sources.
The loading starts at a current level that is 9 times lower
than the current loading after the voltage on pin POM has
passed the 1 V level. This results in an almost dB linear
8.1.7 POWER-OFF PLOP SUPPRESSION
Power should still be provided to the analog part of the
DAC, while the digital part is switching off. As a result, the
output voltage will decrease gradually allowing the power
amplifier some extra time to switch-off without audible
plops. If a 5 V power supply is present, the supply voltage
of the analog part of the DAC can be fed from the 5 V
power supply via a 1.8 V zener diode. A capacitor,
connected to the 3.3 V power supply, provides power to
the analog part when the 5 V power supply is switching off
8.1.8 PIN VREFDA
With two internal resistors half the supply voltage (VDDA2)
is obtained and coupled to an internal buffer. This
reference voltage is used as DC voltage for the output
operational amplifiers and as reference for the DAC.
In order to obtain the lowest noise and to have the best
ripple rejection, a filter capacitor has to be added between
this pin and ground.
8.1.9 INTERNAL DAC CURRENT REFERENCE
As a reference for the internal DAC current and for the
DAC current source output, a current is drawn from the
level on pin VREFDA to pin VSSA2 (ground) via an internal
resistor. The absolute value of this resistor also
determines the absolute current of the DAC. This means
that the absolute value of the current is not that fixed due
to the spread of the current reference resistor value. This,
however, does not influence the absolute output voltages
because these voltages are also derived from a
conversion of the DAC current to the actual output voltage
via internal resistors.
8.1.10 SUPPLY OF THE ANALOG OUTPUTS
All the analog circuitry of the DACs and the operational
amplifiers are fed by 2 supply pins, VDDA2 and VSSA2.
Pin VDDA2 must have sufficient decoupling to prevent THD
degradation and to ensure a good power supply rejection
The digital part of the DAC is fully supplied from the chip
TDA9176 Luminance Transient Improvement (LTI) IC
The TDA9176 is a Luminance Transient Improvement
(LTI) IC which is suitable for operation in both
50 and 100 Hz environments. The device can be used in
conjunction with both LCD and CRT displays.
The TDA9176 also contains chrominance delay lines to
compensate for the luminance delay. The device can be
used as a low-power, cost effective alternative to (but also
in combination with) Scan Velocity Modulation (SVM).
The device operates at a supply voltage of 8 V. The device
is contained in a 16 pin dual in-line package.
· Luminance transient improvement
· Line width control
· Can be used in 50 and 100 Hz environments
(1FH and 2FH)
· Compensating chrominance delay
· YUV interface
· Black insertion or clamping are selectable
· Amplitude selection for optimum operation with
450 mV (p-p) and 1 Vbl-wh luminance signals.
The TDA9176 is a Luminance Transient Improvement
(LTI) IC which is suitable for operation in both
50 and 100 Hz environments. The IC also contains
chrominance delay lines to compensate for the luminance
delay. A diagram of the LTI processor is illustrated in Fig.3.
The LTI processor contains a delay line which drives a
minimum/maximum (MINMAX) detector and a control
circuit. When the control circuit discovers a transient, the
LTI shaper switches from the minimum to the maximum
signal (or vice-versa, depending on the sign of the
transient). By mixing the original signal with the switched
signal, a variable transient improvement is obtained.
The 50% crossing point of the transient is not affected by
the LTI circuit.
If the rise time improvement is active, the duty cycle of the
output signal can be varied with the line width control input.
This function delays the rising edge and advances the
falling edge (or vice-versa). This can be used for example
aperture correction. Figures 4 and 5 illustrate some
waveforms of the LTI processor.
For correct operation the LTI circuit requires a number of
fast clamps. To overcome problems where noise is
superimposed on the input signal the device contains an
input clamp that can either clamp to the black level of the
input signal, or, insert a black level. When a black level is
inserted, the internal clamps do not respond to the noise
on the input signal (see Fig.1). When the input signal
already has an inserted black level (e.g. when it is driven
from the TDA9170 picture booster) it is recommended to
set the device to the clamping mode. If no inserted black
level is available on the input signal it is recommended to
select the black insert mode of the input clamp.
The chrominance delay lines compensate for the delay of
the luminance signal in the LTI circuit. This is to safeguard
a correct colour fit.
Two and three level sandcastles can be used as a timing
signal, only the clamp pulse of the sandcastle input is used
in the device.
There are three selection inputs to select the modes of
operation. These selections are as follows:
1. 1FH or 2FH, for the 50 or 100 Hz applications.
2. Amplitude selection, for optimum operation of the
circuit with 450 mV (p-p) or 1 Vbl-wh luminance signals.
3. Black insertion or clamping of the luminance signal.
The selection inputs must be directly connected to either
ground or the supply rail. The modes are selected as
Frequency selection: GND = 1FH mode,
VCC = 2FH mode
Amplitude selection: GND = 450 mV (p-p),
VCC = 1 Vbl-wh mode
Black insertion/clamp: GND = clamp mode,
VCC = black insert mode.
If the selection pins are left floating, internal 1 MW resistors
connected to the pins set the device to, 1FH mode, black
insert mode and 1 Vbl-wh mode.
TDA933xH series I2C-bus controlled TV display processors:
The TDA933xH series are display processors for
‘High-end’ television receivers which contain the following
· RGB control processor with Y, U and V inputs, a linear
RGB input for SCART or VGA signals with fast blanking,
a linear RGB input for OSD and text signals with a fast
blanking or blending option and an RGB output stage
with black current stabilization, which is realized with the
CCC (2-point black current measurement) system.
· Programmable deflection processor with internal clock
generation, which generates the drive signals for the
horizontal, East-West (E-W) and vertical deflection.
The circuit has various features that are attractive for the
application of 16 : 9 picture tubes.
· The circuit can be used in both single scan (50 or 60 Hz)
and double scan (100 or 120 Hz) applications.
In addition to these functions, the TDA9331H and
TDA9332H have a multi-sync function for the horizontal
PLL, with a frequency range from 30 to 50 kHz (2fH mode)
or 15 to 25 kHz (1fH mode), so that the ICs can also be
used to display SVGA signals.
The supply voltage of the ICs is 8 V. They are each
contained in a 44-pin QFP package.
Available in all ICs:
· Can be used in both single scan (50 or 60 Hz) and
double scan (100 or 120 Hz) applications
· YUV input and linear RGB input with fast blanking
· Separate OSD/text input with fast blanking or blending
· Black stretching of non-standard luminance signals
· Switchable matrix for the colour difference signals
· RGB control circuit with Continuous Cathode Calibration
(CCC), plus white point and black level offset
· Blue stretch circuit which offsets colours near white
· Internal clock generation for the deflection processing,
which is synchronized by a 12 MHz ceramic resonator
· Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
· Slow start and slow stop of the horizontal drive pulses
· Low-power start-up option for the horizontal drive circuit
· Vertical count-down circuit
· Vertical driver optimized for DC-coupled vertical output
· Vertical and horizontal geometry processing
· Horizontal and vertical zoom possibility and vertical
scroll function for application with 16 : 9 picture tubes
· Horizontal parallelogram and bow correction
· I2C-bus control of various functions
· Low dissipation.
RGB control circuit
The RGB control circuit of the TDA933xH contains three
sets of input signals:
· YUV input signals, which are supplied by the input
processor or the feature box. Bit GAI can be used to
switch the luminance input signal sensitivity between
0.45 V (p-p) and 1.0 V (b-w). The nominal input signals
for U and V are 1.33 V (p-p) and 1.05 V (p-p),
respectively. These input signals are controlled on
contrast, saturation and brightness.
· The first RGB input is intended for external signals
(SCART in 1fH and VGA in 2fH applications), which have
an amplitude of 0.7 V (p-p) typical. This input is also
controlled on contrast, saturation and brightness.
· The second RGB input is intended for OSD and teletext
signals. The required input signals have an amplitude of
0.7 V (p-p). The switching between the internal signal
and the OSD signal can be realized via a blending
function or via fast blanking. This input is only controlled
Switching between the various sources can be realized via
the I2C-bus and by fast insertion switches. The fast
insertion switches can be enabled via the I2C-bus.
The circuit contains switchable matrix circuits for the
colour difference signals so that the colour reproduction
can be adapted for PAL/SECAM and NTSC. For NTSC,
two different matrices can be chosen. In addition, a matrix
for high-definition ATSC signals is available.
The output signal has an amplitude of approximately
2 V (b-w) at nominal input signals and nominal settings of
the controls. The required ‘white point setting’ of the
picture tube can be realized by means of three separate
gain settings for the RGB channels.
To obtain an accurate biasing of the picture tube, a CCC
circuit has been developed. This function is realized by a
2-point black level stabilization circuit.
By inserting two test levels for each gun and comparing the
resulting cathode currents with two different reference
currents, the influence of the picture tube parameters such
as the spread in cut-off voltage can be eliminated.
This 2-point stabilization is based on the principle that the
ratio between the cathode currents is coupled to the ratio
between the drive voltages according to:
The feedback loop makes the ratio between cathode
currents Ik1 and Ik2 equal to the ratio between the
reference currents (which are internally fixed) by changing
the (black) level and the amplitude of the RGB output
signals via two converging loops. The system operates in
such a way that the black level of the drive signal is
controlled to the cut-off point of the gun. In this way, a very
good grey scale tracking is obtained. The accuracy of the
adjustment of the black level is only dependent on the ratio
of internal currents and these can be made very accurately
in integrated circuits. An additional advantage of the
2-point measurement is that the control system makes the
absolute value of Ik1 and Ik2 identical to the internal
reference currents. Because this adjustment is obtained
by adapting the gain of the RGB control stage, this control
stabilizes the gain of the complete channel (RGB output
stage and cathode characteristic). As a result, this 2-point
loop compensates for variations in the gain figures during
An important property of the 2-point stabilization is that the
offset and the gain of the RGB path are adjusted by the
feedback loop. Hence, the maximum drive voltage for the
cathode is fixed by the relationship between the test
pulses, the reference current and the relative gain setting
of the three channels. Consequently, the drive level of the
CRT cannot be adjusted by adapting the gain of the RGB
output stage. Because different picture tubes may require
different drive levels, the typical ‘cathode drive level’
amplitude can be adjusted by means of an I2C-bus setting.
Depending on the selected cathode drive level, the typical
gain of the RGB output stages can be fixed, taking into
account the drive capability of the RGB outputs
(pins 40 to 42). More details about the design are given in
the application report (see also Chapter “Characteristics”;
The measurement of the high and the low currents of the
2-point stabilization circuit is performed in two consecutive
fields. The leakage current is measured in each field. The
maximum allowable leakage current is 100 mA.
For extra flexibility, it also possible to switch the CCC
circuit to 1-point stabilization with the OPC bit. In this
mode, only the black level at the RGB outputs is controlled
by the loop. The cathode drive level setting has no
influence on the gain in this mode. This level should be set
to the nominal value to get the correct amplitude of the
Via the I2C-bus, an adjustable offset can be made on the
black level of red and green channels with respect to the
level that is generated by the black current control loop.
These controls can be used to adjust the colour
temperature of the dark part of the picture, independent of
the white point adjustment.
When the TV receiver is switched on, the black current
stabilization circuit is directly activated and the RGB
outputs are blanked. The blanking is switched off as soon
as the loop has stabilized (e.g. the first time that bit BCF
changes from 1 to 0, see also Chapter “Characteristics”;
note 15). This ensures that the switch-on time is reduced
to a minimum and is only dependent on the warm-up time
of the picture tube.
The black current stabilization system checks the output
level of the three channels and indicates whether the black
level of the lowest RGB output of the IC is in a certain
window (WBC bit), below or above this window (HBC bit).
This indication can be read from the I2C-bus and can be
used for automatic adjustment of voltage Vg2 during the
production of the TV receiver.
When a failure occurs in the black current loop (e.g. due to
an open circuit), status bit BCF is set. This information can
be used to blank the picture tube to avoid damage to the
The control circuit contains an average beam current
limiting circuit and a peak white level (PWL) circuit. The
PWL detects small white areas in the picture that are not
detected by the average beam current limiter. The PWL
can be adjusted via the I2C-bus. A low-pass filter is placed
in front of the peak detector to prevent it from reacting to
short transients in the video signal. The capacitor of the
low-pass filter is connected externally so that the set
maker can adapt the time constant as required. The IC
also contains a soft clipper that limits the amplitude of the
short transients in the RGB output signals. In this way, spot
blooming on, for instance, subtitles is prevented. The
difference between the PWL and the soft clipping level can
be adjusted via the I2C-bus in a few steps.
The vertical blanking is adapted to the vertical frequency
of the incoming signal (50 or 100 Hz or, 60 or 120 Hz).
When the flyback time of the vertical output stage is
greater than the 60 Hz blanking time, the blanking can be
increased to the same value as that of the 50 Hz blanking.
This can be set by means of bit LBM.
When no video is available, it is possible to insert a blue
background. This feature can be activated via bit EBB.
Synchronization and deflection processing
HORIZONTAL SYNCHRONIZATION AND DRIVE CIRCUIT
The horizontal drive signal is obtained from an internal
VCO which runs at a frequency of 440 times (2fH mode) or
880 times (1fH mode) the frequency of the incoming HD
signal. The free-running frequency of this VCO is
calibrated by a crystal oscillator which needs an external
12 MHz crystal or ceramic resonator as a reference. It is
also possible to supply an external reference signal to the
IC (in this case, the external resonator should be
The VCO is synchronized to the incoming horizontal HD
pulse (applied from the feature box or the input processor)
by a PLL with an internal time constant. The frequency of
the horizontal drive signal (1fH or 2fH) is selected by means
of a switching pin, which must be connected to ground or
left open circuit.
For HDTV applications, it is possible to change the
free-running frequency of the horizontal drive output from
31.2 kHz to 33.7 kHz by means of bit HDTV.
For safety reasons, switching between 1fH and 2fH
modes is only possible when the IC is in the standby
For the TDA9331H and TDA9332H, it is also possible to
set the horizontal PLL to a ‘multi-sync’ mode by means of
bit VGA. In this mode, the circuit detects the frequency of
the incoming sync pulses and adjusts the centre frequency
of the VCO accordingly by means of an internal
Digital-to-Analog-Converter (DAC). The frequency range
in this mode is 30 to 50 kHz at the output.
The polarities of the incoming HD and VD pulses are
detected internally. The detected polarity can be read out
via status bits HPOL and VPOL.
The horizontal drive signal is generated by a second
control loop which compares the phase of the reference
signal (applied from the internal VCO) with the flyback
pulse. The time constant of this loop is set internally. The
IC has a dynamic horizontal phase correction input, which
can be used to compensate phase shifts that are caused
by beam current variations. Additional settings of the
horizontal deflection (which are realized via the second
loop) are the horizontal shift and horizontal parallelogram
and bow corrections (see Chapter “Characteristics”;
Fig.16). The adjustments are realized via the I2C-bus.
When no horizontal flyback pulse is detected during three
consecutive line periods, status bit NHF is set.
The horizontal drive signal is switched on and off via the
so-called slow-start/slow-stop procedure. This function is
realized by varying the ton of the horizontal drive pulse. For
EHT generators without a bleeder, the IC can be set to a
‘fixed beam current mode’ via bit FBC. In this case, the
picture tube capacitance is discharged with a current of
approximately 1 mA. The magnitude of the discharge
current is controlled via the black current feedback loop.
If necessary, the discharge current can be enlarged with
the aid of an external current division circuit. With the fixed
beam current option activated, it is still possible to have a
black screen during switch-off. This can be realized by
placing the vertical deflection in an overscan position. This
mode is activated via bit OSO.
An additional mode of the IC is the ‘low-power start-up’
mode. This mode is activated when a supply voltage of 5 V
is supplied to the start-up pin.
The required current for this mode is 3 mA (typ.). In this
condition, the horizontal drive signal has the nominal toff
and the ton grows gradually from zero to approximately
30% of the nominal value. This results in a line frequency
of approximately 50 kHz (2fH) or 25 kHz (1fH). The output
signal remains unchanged until the main supply voltage is
switched on and the I2C-bus data has been received. The
horizontal drive then gradually changes to the nominal
frequency and duty cycle via the slow-start procedure.
The IC can only be switched on and to standby mode when
both standby bits (STB0 and STB1) are changed. The
circuit will not react when only one bit changes polarity.
The IC has a general purpose bus controlled DAC output
with a 6-bit resolution and with an output voltage range
between 0.2 to 4 V. In the TDA9331H, the DC voltage on
this output is proportional to the horizontal line frequency
(only in VGA mode). This voltage can be used to control
the supply voltage of the horizontal deflection stage, to
maintain constant picture width for higher line frequencies.
VERTICAL DEFLECTION AND GEOMETRY CONTROL
The drive signals for the vertical and E-W deflection
circuits are generated by a vertical divider, which derives
its clock signal from the line oscillator. The divider is
synchronized by the incoming VD pulse, generated by the
input processor or the feature box. The vertical ramp
generator requires an external resistor and capacitor; the
tolerances for these components must be small. In the
normal mode, the vertical deflection operates in constant
slope and adapts its amplitude, depending on the
frequency of the incoming signal (50 or 60 Hz, or
100 or 120 Hz). When the TDA933xH is switched to the
VGA mode, the amplitude of the vertical scan is stabilized
and independent of the incoming vertical frequency. In this
mode, the E-W drive amplitude is proportional to the
horizontal frequency so that the correction on the screen is
The vertical drive is realized by a differential output
current. The outputs must be DC-coupled to the vertical
output stage (e.g. TDA8354).
The vertical geometry can be adjusted via the I2C-bus.
Controls are possible for the following parameters:
· Vertical amplitude
· Vertical slope
· Vertical shift (only for compensation of offsets in output
stage or picture tube)
· Vertical zoom
· Vertical scroll (shifting the picture in the vertical direction
when the vertical scan is expanded)
· Vertical wait, an adjustable delay for the start of the
With regard to the vertical wait, the following conditions are
· In the 1fH TV mode, the start of the vertical scan is fixed
and cannot be adjusted with the vertical wait
· In the 2fH TV mode, the start of the vertical scan
depends on the value of the Vertical Scan Reference
(VSR) bus bit. If VSR = 0, the start of the vertical scan is
related to the end of the incoming VD pulse. If VSR = 1,
it is related to the start. In both cases, the start of the
scan can be adjusted with the vertical wait setting
· In the multi-sync mode (TDA9331H and TDA9332H
both in 1fH mode and 2fH mode), the start of the vertical
scan is related to the start of the incoming VD pulse and
can be adjusted with the vertical wait setting.
The minimum value for the vertical wait setting is 8 line
periods. If the setting is lower than 8, the wait period will
remain at 8 line periods.
The E-W drive circuit has a single-ended output. The E-W
geometry can be adjusted on the following parameters:
· Horizontal width with increased range because of the
· E-W parabola/width ratio
· E-W upper corner/parabola ratio
· E-W lower corner/parabola ratio
· E-W trapezium.
The IC has an EHT compensation input which controls
both the vertical and the E-W output signals. The relative
control effect on both outputs can be adjusted via the
I2C-bus (sensitivity of vertical correction is fixed; E-W
To avoid damage to the picture tube in the event of missing
or malfunctioning vertical deflection, a vertical guard
function is available at the sandcastle pin (pin SCO). The
vertical guard pulse from the vertical output stage
(TDA835x) should be connected to the sandcastle pin,
which acts as a current sense input. If the guard pulse is
missing or lasts too long, bit NDF is set in the status
register and the RGB outputs are blanked. If the guard
function is disabled via bit EVG, only NDF status bit NHF
The IC also has inputs for flash and overvoltage protection.
CHASSIS MG3.1E FEATURE BOX UNIT (FBX):
SAA4978H Picture Improved Combined Network (PICNIC)
· Analog AGC
· Triple YUV 9-bit Analog-to-Digital Converter (ADC)
· Triple bypassable analog anti-alias filter
· 4 MHz notch filter
· Non-linear phase filter after ADC
· 4 : 1 : 1 or 4 : 2 : 2 digital processing
· 4 : 1 : 1 or 4 : 2 : 2 selectable I/O interface
· Asynchronous digital input
· Time base correction
· Histogram analysis
· Histogram modification
· Subtitle detection
· Black bar detection
· Line memory based noise reduction (spatial)
· Noise level measurement
· Clamp noise reduction
· Dynamic peaking
· Energy measurement
· Multi Picture-In-Picture (multi PIP) decimation
· Differential Pulse Code Modulation (DPCM) data
decompression for colour
· 2D-peaking and coring
· Non-linear phase filter before DAC
· Coaxial Transceiver Interface (CTI)
· Triple 10-bit Digital-to-Analog Converter (DAC)
· Triple bypassable analog reconstruction filter
· Embedded microcontroller (80C51 core)
· Programmable signal positioner
· SNERT interface
· I2C-bus user control interface
· Boundary Scan Test (BST).
2 GENERAL DESCRIPTION
The SAA4978H is a monolithic integrated circuit suitable
either for 1fH or 2fH applications that contain a large variety
of picture improvement functions. It combines
analog-to-digital and digital-to-analog conversion for YUV
signals, digital processing, line-locked clock regeneration
and an 80C51 microcontroller core in one IC.
7 FUNCTIONAL DESCRIPTION
The SAA4978H consists of the following main functional
· Analog preprocessing and analog-to-digital conversion
· Digital processing at 1fH level
· Digital processing at 2fH level
· Digital-to-analog conversion
· Line-locked clock generation
· Crystal oscillator
· Control interfacing I2C-bus and SNERT
· Register I/O
· Programmable Signal Positioner (PSP)
· 80C51 microcontroller core
· Board level testability provisions.
7.1 Analog input blocks
7.1.1 GAIN ELEMENTS FOR AUTOMATIC GAIN CONTROL
(9 dB RANGE)
A variable amplifier is used to map the possible YUV input
range to the analog-to-digital converter range e.g. as
defined for SCART signals.
According to this specification, a lift of 6 dB up to a drop of
3 dB may be necessary with respect to the nominal values.
The gain setting within the required minimum 9 dB range
is performed digitally via the internal microcontroller.
For this purpose a gain setting digital-to-analog converter
is incorporated. The smallest step in the gain setting
should be hardly visible on the picture, this can be met with
smaller steps of 0.4%/step.
Luminance and chrominance gain settings can be
separately controlled. The reason for this split is that
U and V may have already been gain adjusted by an
Automatic Chrominance Control (ACC), whereas
luminance is to be adjusted by the SAA4978H AGC.
However, for RGB originated sources, Y, U and V should
be adjusted with the same AGC gain.
7.1.2 CLAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 32
AND UV TO 0 (TWOS COMPLEMENT)
A clamp circuit is applied to each input channel, to map the
colourless black level in each video line (on the sync back
porch) to level 32 at 9 bits for Y and to the centre level of
the converters for U and V. During the clamp period, an
internally generated clamp pulse is used to switch-on the
A voltage controlled current source construction, which
references to voltage reference points in the ladders of the
analog-to-digital converters, provides a current on the
input of the YUV signals in order to bring the signals to the
correct DC value. This current is proportional to the DC
error, but is limited to ±150 mA. It is essential that the clamp
current becomes zero with a zero error and that the
asymmetry between positive and negative clamp currents
is limited to within 10%. When the clamping action is off,
the residual clamp current should be very low, so that the
clamp level will not drift away within a video line.
The clamp level in the Y channel has a minimum value of
600 mV to ensure undisturbed clamping for maximum
Y input signals with top sync levels up to 600 mV. In order
to improve common mode rejection it is recommended to
connect the same source impedance as used in the YIN
input at the DIFFIN input to ground.
7.1.3 ANALOG ANTI-ALIASING PREFILTER
A 3rd-order linear phase filter is applied to each of the
Y, U and V channels. It provides a notch on fclk (16 MHz
at Y, U and V) to strongly prevent aliasing to low
frequencies, which would be the most disturbing.
The bandwidth of the filters is designed for -3 dB at
5.6 MHz. The filters can be bypassed if external filtering
with other characteristics is desired. In the bypass mode
the gain accuracy of the front-end part is 4% instead of 8%
for the filter-on mode.
7.1.4 9-BIT ANALOG-TO-DIGITAL CONVERSION
Three identical multi-step type analog-to-digital converters
are used to convert the Y, U and V inputs with a 16 MHz
data rate. The ADCs have a 2-bit overflow detection, and
an underflow detection for U and V, to be used for AGC
control. The 2 bits are coded for one in-range level and
three overflow levels; 1 dB, 1 to 2 dB and 2 to 3 dB.
7.2 Digital processing blocks
7.2.1 OVERFLOW DETECTION
A histogram of the three overflow levels is made every field
and can be read in a 2-byte accuracy. An input selector
defines which ADC is monitored.
In the event of U or V selection the underflow information
is also added to the first histogram level, in this way the
data can be handled as out-of-range information.
The histogram content provides information for the AGC to
make an accurate estimate of the decrease in gain, in the
event of overflow for luminance or out-of-range detection
for U and V.
7.2.2 Y DELAY
The Y samples can be shifted onto 4 positions with
respect to the UV samples. This shift is meant to account
for a possible difference in delay prior to the SAA4978H,
e.g. from a prefilter in front of an analog-to-digital
converter. The zero delay setting is suitable for the
nominal case of aligned input data according to the
interface format standard. One setting provides one
sampleless delay in Y, the other two settings provide more
delay in the Y path.
7.2.3 TRANSIENT NOISE SUPPRESSION
A circuit is added in the luminance channel to suppress the
typical multi-step trip level noise. This majority follower
filter compares the neighbouring pixels to a +1 or -1 LSB
difference. If the majority of these differences is +1 then 1
is added to the actual pixel. If the majority of these
differences is -1 then 1 is subtracted from the actual pixel.
The number of pixels included in the filter is selectable;
1 (bypass), 3, 5, 7 or 9.
7.2.4 NON-LINEAR PHASE FILTER AFTER ADC
The non-linear phase filter adjusts for possible group delay
differences in the luminance channel. The filter coefficients
are [-L ´ (1 - u); 1 + L; -L ´ u]; where L determines the
strength of the filter and u determines the asymmetry.
The effect of the asymmetry is that for higher frequencies
the delay is decreased for u £ 0.5. Settings are provided
for L = 0, 1¤16, 2¤16 and 3¤16 and u = 0, 1¤4 and 1¤2.
7.2.5 4 MHZ NOTCH
The 4 MHz notch provides a zero on 1¤4 of the sample
frequency. With fs = 16 MHz the notch is thus at 4 MHz.
The 3 dB notch width is 2 MHz. The filter coefficients are
1¤8 ´ [-1; 0; 5; 0; 5; 0; -1]. This filter gives a relative gain of
0.75 dB at 1.7 and 6.3 MHz.
The notch can be bypassed without changing the group
7.2.6 DIGITAL CLAMP CORRECTION FOR UV
During 32 samples within the active clamping the clamp
error is measured and accumulated to determine a
low-pass filtered value of the clamp error. A vertical
recursive filter is then used to further reduce this error
value. This value can be read by the microcontroller or be
used directly to correct the clamp error. It is also possible
for the microcontroller to give a fixed correction value.
7.2.7 4 : 4 : 4 DOWNSAMPLED TO 4 : 2 : 2 OR 4 : 1 : 1
4 : 4 : 4 data is downsampled to 4 : 2 : 2, by first filtering
with a [1; 0; -7; 0; 38; 64; 38; 0; -7; 0; 1] filter, before being
subsampled by a factor of 2. The U and V samples from
the 4 : 2 : 2 data are filtered again by a [-1; 0; 9; 16; 9; 0;
-1] filter, before being subsampled a second time by a
factor of 2. Bypassing this function keeps the data in the
4 : 2 : 2 format.
7.2.8 BUS A FORMAT: INTERFACE FORMATTING, TIMED
WITH ENABLING SIGNAL (see Table 1 and Fig.9)
The chosen 4 : 1 : 1 or 4 : 2 : 2 formatted output data is
presented to bus A (YUV_A bus), consistent with the WEA
data enable signal. After the rising edge of WEA the first,
respectively second, data word contains the first phase of
the 4 : 1 : 1 or 4 : 2 : 2 format, depending on the qualifier
respectively prequalifier mode of WEA. If the data has to
be formatted to 8 bits, a choice can be made between
rounding and dithered rounding. Dithered rounding may be
applied in the sense that every odd output sample has had
an addition of 0.25 LSB (relative to 8 bits) before
truncation and every even output sample has had an
addition of 0.75 LSB before truncation. In this way, on
average, correct rounding is realized (no DC shift).
Especially for low frequency signals, the resolution is
increased by a factor of 2 by the high frequency
modulation. The phase of dithering can be switched 180°
from line-to-line, field-to-field or frame-to-frame, in order to
decrease the visibility of the dithering pattern.
The not connected output pins of bus A, including WEA
(depending on the application), can be set to 3-state to
allow short-circuiting of these pins at board production.
Short-circuiting at not connected outputs can not be tested
by Boundary Scan Test (BST). For outputs in 3-state mode
it is not allowed to apply voltages higher than
VDDO + 0.3 V.
7.2.9 BUS B FORMAT (see Table 1 and Fig.9)
Bus B can accommodate the following formats; 4 : 1 : 1
serial, 4 : 2 : 2 parallel, 4 : 2 : 2 double clock UYVY, all
synchronous and asynchronous. All external formats are
selectable with prequalifier or qualifier WEB. All of the
various input formats are converted to the internal 9 bits
4 : 2 : 2. For the 8-bit inputs, the LSB of the input bus
should be connected externally to a fixed logic level. In the
event of a 4 : 1 : 1 input, the U and V channels are
reformatted and upsampled by generating the extra
samples with a 1¤16 ´ [-1; 9; 9; -1] filter. The other U and V
samples remain equal to the original 4 : 1 : 1 sample
It is possible, in bus B reformatter, to invert the UV data so
that the SAA4978H can handle any polarity convention of
the UV data.
In the event of an asynchronous input the clock has to be
provided externally to pin CLKAS.
When applying an external PALplus decoder with 30 ms
processing delay, the vertical field start can be set via
software in a PSP register. For “CCIR 656” standard data
format input, inversion of the MSB of the (synchronized)
bus B UV input can be selected. Synchronization signals
included in this format will be ignored.
7.2.10 TIME BASE CORRECTION AND SAMPLE RATE
The Time Base Correction (TBC) and Sample Rate
Conversion (SRC) block provides a dynamically controlled
delay with an accuracy of up to 1¤64 of a pixel and a range
of -0.5 to +0.5 lines (plus processing delay).
The time base correction block has an input for skew data.
This skew data can be the phase error measured by a
HPLL, which is located in the PLL block of the SAA4978H.
The skew is used as a shift of the complete active video
part of a line. Added with a static (user controlled) shift, up
to 1¤2 video line (32 ms) can be shifted in both directions,
related to a nominal 1¤2 line delay.
For sample rate conversion, the delay is also varied along
the line with the subpixel accuracy. With a zero-order
variation of the delay, a linear compress or expand
function can be obtained. The range for the compression
factor is 0 to 2, meaning infinite zoom up to a compression
with a factor of 2. With a 2nd-order variation of the delay
added to the control, the compression factor can be
modulated with a parabolic shape, thus giving a panoramic
view option to display e.g. 4 : 3 video on a 16 : 9 screen or
The static shift may also be used to make the delay of the
SAA4978H plus periphery equal to an integer number of
lines. This is useful for 1fH applications, in which the
horizontal sync signal is not delayed with the video data.
This will then make the function of time base correction
obsolete for 1fH applications.
Another main task for the sample rate converter is to
resynchronize external data at a non-system clock sample
rate, for instance, MPEG decoder signals at 13.5 MHz.
A requirement for these signals is that they are line and
frame locked to the SAA4978H.
7.2.11 NOISE REDUCTION
The noise reduction part consists of clamp noise reduction
and spatial noise reduction for low frequency noise. Within
this ensemble a two dimensional band split is used,
enabling also the functions of 2D low passing, adding the
multi Picture-In-Picture (multi PIP) function and 2D
The clamp noise reduction is realized with an adaptive
temporal recursive filter. This filter will correct the DC level
of each line when it is varying from field-to-field in the
segments with the least likely movement. This clamp noise
filtering is intended to correct for clamp errors in a
complete chain, which cannot be removed with traditional
clamping on the back porch of the video. Clamp noise is
only reduced for luminance.
The spatial noise reduction is targeted for reduction of the
mid frequency noise spectrum, where adaptive filtering
combines pixels around the centre pixel and pixels from
the lines above in a recursive way. This spatial noise
reduction is only realized for luminance.
The 2D low-pass filter is a [1; 2; 1] filter in both the
horizontal and vertical direction. 2D high-pass is realized
by taking the centre tap and subtracting the 2D low-pass
output from it. Also added in the 2D high-pass is the
vertical low-passed data, which is subtracted from the
centre tap and multiplied by a user selectable gain
(0 to 7¤8). The 2D high-pass data is multiplied by a user
selectable gain of 0 and 2¤4 to 8¤4 and cored before adding
it to the 2D low-pass branch for the 2D peaking function.
The HF signal bypasses both the LF temporal and the
spatial noise reduction, therefore sharpness in the high
frequencies is not reduced by the noise reduction parts.
The factor 0 on the HF signal yields a pure 2D low-passed
signal at the output. Multi PIP with pure subsampling of this
signal yields a much better result than without the low-pass
Histogram modification consists of acquiring the histogram
of the luminance levels and correcting the luminance
transfer curve in order to provide more perceptual contrast
in the picture.
For economy, a subsampling is realized on the video with
a factor of 4 before the histogram is produced. From
line-to-line, a two pixel offset is used on the subsample
The histogram acquisition uses 32 baskets on the grey
scale from (ultra) black to (ultra) white. Pixels that are
found around the centre of a basket increase a counter for
that basket with the value 8, pixels that come around the
edge between two baskets increase the counters in both
baskets, such as 3 in the left one and 5 in the right one.
By this method, the quantization distortion is overcome
from having a discrete set of baskets.
Between acquisition of the histogram and correction of the
transfer curves, the microcontroller included in the
SAA4978H processes the counter values from the
32 baskets. The outcome of the microcontrollers algorithm
defines a differential transfer curve for the luminance. This
means that only differences from a 1 : 1 transfer curve are
coded. This is done in 32 LUT points, with a linear
interpolation for all input values in between the LUT points.
When changes are made to the luminance level of pixels,
the saturation has to be restored by using the same
relative gain for the U and V channels.
The histogram data also provides the information of the
minimum and maximum levels of Y, U and V, by which the
microcontroller can affect an AGC gain before the video
Another main part of the histogram is the display-bars
block. This block can insert up to 32 horizontal bars in the
YUV data path. Size, spacing, luminance, colour and
length are fully programmable. This can be used to
construct a visual display of the histogram or transfer
7.2.13 SUBTITLE DETECTION
Subtitle detection searches in a large area of the video
field for patterns that are characteristic for subtitles.
The expectation is to encounter in a video line a
considerable number of crossings through both a dark
grey and a light grey threshold and in its vicinity also
crossings in the other direction. This part is realized with
valid crossing (event) counting on each line in the target
area. This event value is stored for 128 lines in the subtitle
RAM, which is located at the top of the auxiliary RAM.
The subtitle logic has higher priority to access the subtitle
RAM than the microcontroller.
The internal microcontroller can filter out this data. In a
number of adjacent lines, there must be a similar high
count value for the number of events. If this condition holds
then the detection of subtitles on that vertical position is
This information can be used in combination with other
information on how to display the video source on the
screen. Such decisions are made entirely by the internal
7.2.14 BLACK BAR DETECTION
Black bar detection searches in the upper and in the lower
part of the screen to respectively the last black line and the
first black line. To avoid disturbances of Logos in the video,
measurements can be performed in only the horizontal
centre part of the lines.
7.2.15 BUS C FORMAT (see Table 1)
The U and V samples from the 4 : 2 : 2 data are filtered
again by a [-1; 0; 9; 16; 9; 0; -1] filter, before being
subsampled by a factor of 2. Bypassing this function keeps
the data in the 4 : 2 : 2 format.
Should it be required to format the data to 8 bits, a choice
can be made between rounding and dithered rounding.
Dithered rounding may be applied in the sense that every
odd output sample has had an addition of 0.25 LSB
(relative to 8 bits) before truncation and every even output
sample has had an addition of 0.75 LSB before truncation.
In this way, normally, correct rounding is realized (no DC
shift). Especially for low frequency signals, the resolution
is increased by a factor of 2 by the high frequency
modulation. The phase of dithering is switched 180° from
line-to-line, field-to-field or frame-to-frame in order to
decrease the visibility of the dithering pattern.
This block also performs the subsampling for multi PIP,
with subsampling factors of 1, 2, 3 and 4.
Another output format at bus C is Differential Pulse Code
Modulation (DPCM) 4 : 2 : 2. This data compression
method is applied on the U and V channels, and gives a
50% data reduction. In this way it is possible to convert a
4 : 2 : 2 picture to 2fH using a single 12-bit wide field
memory. This format is especially useful for graphics
conversion with high amplitude and high saturation input
signals. The not connected output pins of bus C including
WEC and IEC (depending on the application) can be set to
3-state to allow short-circuiting of these pins at board
production. Short-circuiting at not connected outputs can
not be tested by BST. For outputs in 3-state mode it is not
allowed to apply voltages higher than VDDO + 0.3 V.
7.2.16 BUS D REFORMATTER: THE VARIOUS INPUT
FORMATS ARE ALL CONVERTED TO THE INTERNAL
9 BITS 4 : 2 : 2 (see Table 1)
Bus D can handle 4 : 1 : 1 external 8 or 9 bits, 4 : 2 : 2
external 8 or 9 bits, 4 : 2 : 2 internal 9 bits and DPCM
4 : 2 : 2.
Bus D is selectable in 1fH and 2fH mode. In 1fH mode the
internal input can also be used.
For dithered 8-bit luminance signals an undither block is
provided that restores the 9th bit for low frequency and low
noise. This is needed before the peaking circuit to prevent
amplification of the 1¤2fs dither modulation.
In the event of 8-bit inputs, the LSB of the input bus should
be externally connected to a fixed logic level.
In the event of a 4 : 1 : 1 input, the U and V channels are
reformatted and upsampled by generating the extra
samples with a 1¤16 ´ [-1; 9; 9; -1] filter. The other U and V
samples remain equal to the original 4 : 1 : 1 sample
Peaking in the SAA4978H can be used in two ways:
1. The first way is to give the luminance a linear boost of
the higher frequency ranges, which makes no
distinction between small and large details or edges.
2. The second way is to use the peaking dynamically, in
order to boost smaller details and provide less gain on
large details and edges. The effect is detail
enhancement without the creation of unnaturally large
overshoots and undershoots on large details and
Basically, the three peaking filters (1 high-pass and
2 band-pass) filter the incoming luminance signal.
The high-pass filter is made with [-1; 2; -1] coefficients,
giving a maximum throughput at 1¤2fs (equals 8 MHz).
The first band-pass filter has [-1; 0; 2; 0; -1] coefficients,
giving a maximum throughput at 1¤4fs (equals 4 MHz).
The second band-pass filter has a cascade of
[-1; 0; 0; 2; 0; 0; -1] and [1; 2; 1] coefficients, giving a
maximum throughput at 2.38 MHz.
With a separate gain control on each of the peaking filters
[possible gain settings of (0, 1¤16, 2¤16, 3¤16, 4¤16, 5¤16, 6¤16
and 8¤16)], a desired frequency characteristic can be
obtained with steps of maximum 2 dB gain difference at
the centre frequencies.
The sum of the filter outputs is fed through a coring circuit
with a user definable transfer curve between
-7 and +7 LSB at a 12-bit level. The definition of the coring
LUT is realized with two control registers. Herein, for each
of the points in the transfer curve, the user can define an
output between 0 and the input value. For the LUT
points +7 (and -7), a choice can be made from
(-4) +4 to (-7) +7. By setting control bit CORING to LOW,
the coring transfer curve is switched to a coarse coring
which is only dependent on the threshold (see Fig.13).
The so formed peaking signal can be added to the original
luminance signal, the sum of which then becomes the 9-bit
output signal (black-to-white), with an additional DA shift
fitting within 10 bits.
For dynamic use of the peaking circuit, an additional gain
is provided on the peaking signal. This gain is made
dependent on the energy in the peaking signal.
To overcome an unwanted coring on structured small
signals, the output of the low-pass filter is also used to
monitor if the high frequency contents are large enough to
refrain from coring. Therefore the coring is set off if the HF
energy level rises above a user definable threshold.
Spectral measurements are performed with the
spectr_meas subpart, by calculating the sum of the
absolute values from a chosen one of the three (high-pass
and band-pass) filter outputs over a vertical window in a
video field. With this window it is possible to disable
subtitles. The maximum value of the chosen filter output
within a windowed video field is also monitored. For the
generally lower HF contents of the video signal, a
weighting by a factor 4 can be switched in, while
measuring on the High-Pass Filter (HPF).
7.2.18 NON-LINEAR PHASE FILTER BEFORE DAC
This non-linear phase filter adjusts for possible group
delay differences in the Y, U and V output channels, and
for sinus x/x bandwidth loss of the ADCs. The filter
coefficients are [-L ´ (1 - u); 1 + L; -L ´ u]; where
L determines the strength of the filter and u determines the
asymmetry. The effect of the asymmetry is that for higher
frequencies the delay is decreased for u £ 0.5. Settings
are provided for L = 0, 1¤8, 2¤8, 3¤8 and u = 0, 1¤4, 1¤2.
The Digital Colour Transient Improvement (DCTI) is
intended for U and V signals originating from a 4 : 1 : 1
source. Horizontal transients are detected and enhanced
without overshoots by differentiating, making absolute and
again differentiating the U and V signals separately. This
signal is used as a pointer to make a time modulation.
This results in a 4 : 4 : 4 U and V bandwidth. To prevent
third harmonic distortion, typical for this processing, a so
called ‘over the hill protection’ prevents peak signals from
becoming distorted. It is possible to control gain, width,
connect U and V and over the hill range via the
At the output of the DCTI a post-filter is situated to make a
correction for the simple upsampling in DCTI which is a
linear interpolation [1; 2; 1]. The post-filter coefficients are
[-1; 2; 6; 2; -1], convolution of both filters gives
[-1; 0; 9; 16; 9; 0; -1]. This post-filter should only be used
when the DCTI is off, and the source material is 4 : 2 : 2
7.2.20 BORDER BLANK
The border and blanking processing is operating at a
4 : 4 : 4 level, just before the analog-to-digital conversion.
Here it is possible to generate a blanking window and
within this window a border window. The blanking window
is used to blank the non-visible part of the output to the
clamp level. The border window is the visible part of the
video that contains no video, such as the sides in
compression mode, this part can be programmed to
display any luminance or colour level in an 8-bit accuracy;
pixel repetition is also possible here. In case of multi PIP
this block can generate separation borders in the
horizontal and vertical direction.
7.3 Analog output blocks
7.3.1 TRIPLE 10-BIT DIGITAL-TO-ANALOG CONVERSION
Three identical DACs are used to convert Y, U and V with
a 32 or 16 MHz data rate.
7.3.2 ANALOG ANTI-ALIASING POST-FILTER
A 3rd-order linear phase filter is applied to each of the Y,
U and V channels. It provides a notch on fclk (32 MHz at Y,
U and V) to strongly prevent aliasing to low frequencies,
which would be most disturbing. The filters can be
bypassed if external filtering with other characteristics is
desired. Bandwidth and gain accuracy are given in
The PLL consists of a ring oscillator, Discrete Time
Oscillator (DTO) and digital control loop. The PLL
characteristic is controlled by means of the
A SNERT interface is built-in to transform the parallel data
from the microcontroller into 1 or 2 Mbaud switchable
SNERT data. This interface is also capable of reading data
from the SNERT bus should it be required to access read
The read or write operation must be set by the
microcontroller. When writing to the bus, 2 bytes are
loaded by the microcontroller; one for the address, the
other for the data. When reading from the bus, 1 byte is
loaded by the microcontroller for the address, the received
byte is the data from the addressed SNERT location.
The SNERT interface replaces the standard UART
interface. In contrast to the 80C51 UART interface there
are additional control registers, other I/O pads and no byte
separation time between address and data. After
power-on reset the 1 Mbaud mode is active. Switching
baud rate during transmission should be avoided.
For dynamically changing data such as timing signals, the
programmable signal positioner generates them on the
basis of parameters sent by the microcontroller. For the
reset function of the microcontroller, a watchdog timer is
also built-in that creates a reset pulse unless it is triggered
by a change in the Bone signal within a preset time
The SAA4978H contains an embedded 80C51
microcontroller core including a 1 kbyte RAM and a
32 kbyte ROM. It also includes an I2C-bus user control
interface. For development reasons an external ROM can
be accessed with 64 kbyte maximum size. An external
emulator can be connected.
The main difference to most existing 80C51 derivatives is:
· 768 byte auxiliary RAM from which 128 bytes can be
accessed as subtitle RAM
· Interrupt vector address for the I2C-bus is 33H
· On-chip ROM code protection
· SNERT at 1 or 2 Mbaud with additional Sample
Frequency Registers (SFRs) instead of UART
· Host interface containing all control registers access
e.g. via MOVX instruction.
SAA4992H Field and line rate converter with noise reduction (FALCONIC):
· Upconversion of all 1fH film and video standards up to
292 active input lines per field
· 100/120 Hz 2 : 1, 50/60 Hz 1 : 1 and 100/120 Hz 1 : 1
· 4 : 1 : 1, 4 : 2 : 2 and 4 : 2 : 2 Differential Pulse Code
Modulation (DPCM) input colour formats; 4 : 1 : 1 and
4 : 2 : 2 output colour formats
· Full 8-bit accuracy
· Scalable performance by applying 1, 2 or 3 external
· Improved recursive de-interlacing
· Film (25 Hz, 30 Hz) upconversion to 100/120
movement phases per second
· Variable vertical sharpness enhancement
· Motion compensated 3D dynamic noise reduction
· High quality vertical zoom
· 2 Mbaud serial interface (SNERT).
2 GENERAL DESCRIPTION
The SAA4992H is a completely digital monolithic
integrated circuit which can be used for field and line rate
conversion of all global TV standards.
It features improved ‘Natural Motion’ performance and full
film upconversion for all 50 and 60 Hz film material.
It can be configured to emulate the SAA4990H as well as
the SAA4991WP. For demonstration purposes a split
screen mode to show the Dynamic Noise Reduction
(DNR) function and a colour vector overlay is available.
The SAA4992H supports a Boundary Scan Test (BST)
circuit in accordance with IEEE 1149.
The FAL (fal_top) module builds the functional top level of
the SAA4992H. It connects the luminance data path (KER,
kernel), the chrominance data path (COL, colour) and the
luminance (de)compression (YDP, Y-DPCM) with
SAA4992H inputs and outputs as well as controlling logic
(LSE, line sequencer; SNE, SNERT interface). Outside of
fal_top there are only the pad cells, boundary scan test
cells, the boundary scan test controller, the clock tree, the
test enable tree and the input port registers.
Figure 4 shows a simplified block diagram of fal_top. It
displays the flow of pixel data (solid lines) and controls
(broken lines) between the modules inside.
Basic functionality of the modules in fal_top is as follows:
· KER (kernel): Y (luminance) data path
· COL (colour): UV (chrominance) data path
· YDP (Y-DPCM): compression (and decompression) of
luminance output (and input) data by Differential Pulse
Code Modulation (DPCM)
· LSE (line sequencer): generate line frequent control
· SNE: Synchronous No parity Eight bit Reception and
Transmission (SNERT) interface to a microcontroller.
The SNERT interface operates in a slave receive and
transmit mode for communication with a microprocessor,
which resides on peripheral circuits (e.g. SAA4978H)
together with a SNERT master. The SNERT interface
transforms serial data from the microprocessor (via the
SNERT bus) into parallel data to be written into the
SAA4992Hs write registers and parallel data from
SAA4992Hs read registers into serial data to be sent to the
microprocessor. The SNERT bus consists of 3 signals:
1. SNCL: used as serial clock signal, generated by the
2. SNDA: used as bidirectional data line
3. SNRST: used as a reset signal, generated by the
microprocessor to indicate the start of a transmission.
The processing of a video field begins on the rising edge
of the RE_F input signal. As indicated in Fig.4, the
SAA4992H expects its inputs and generates its outputs at
the following clock cycles after RE_F
SAA4997H VErtical Reconstruction IC (VERIC) for PALplus:
The VErtical Reconstruction IC (VERIC) for PALplus
(VERIC) is especially designed for use in conjunction with
the Motion Adaptive Colour Plus And Control IC
(MACPACIC) to decode the transmitted PALplus video
signal in PALplus colour TV receivers. It provides the full
vertical resolution of a PALplus picture from the letter box
part and the decoded helper information.
· PALplus decoding
· Vertical reconstruction
· Quadrature mirror filter
· Luminance and chrominance processing
As shown in Fig.2 the PALplus module consists of two
special integrated circuits:
· Motion Adaptive Colour Plus And Control IC
· VErtical Reconstruction IC (VERIC)
and four field memories TMS4C2970.
The MACPACIC and the VERIC are intended to generate
digitally decoded 50 Hz YUV signals. The MACPACIC
performs the decompanding function for the helper lines
and the motion adaptive luminance/chrominance
separation. Furthermore, PALplus system controlling,
memory controlling and clock generation are carried out in
The function of the VERIC is to reconstruct the separated
2 ´ 72 helper lines and the 430 main lines into a standard
576 lines frame according the PALplus system description
“REV 2.0”. Chrominance is converted from 430 lines to
576 lines using a vertical sample rate converter.
The data of the VERIC are clocked out with 16 MHz.
The Y : U : V bandwidth ratio is 4 : 1 : 1.
The functional block diagram of the VERIC is shown in
Fig.1. The device consists of 3 main parts:
· Luminance processing
· Chrominance processing
The input data are delivered by the field memories FM2
and FM3, which include multiplexed first and second field
data processed by the MACPACIC. The luminance and
chrominance input data of the VERIC are clocked with
32 MHz (CLK_32B3). Internally the device operates at
32 or 16 MHz clock frequency.
In the PALplus encoder the luminance signal is separated
vertically into two sub-bands by a special Quadrature
Mirror Filter (QMF).
A vertical low-pass sub-band consists of the 430 main
letter box lines per frame, and a vertical high-pass
sub-band includes the 144 helper lines per frame.
The used QMF technique has two advantages:
· Essentially loss-free data processing
· Cancellation of alias components in the main and helper
signal in the decoder.
The luminance vertical conversion process in the decoder
is complementary to that of the encoder.
In the decoder the inverse QMF function is implemented to
recombine the two separated sub-bands and to generate
the original video signal with 576 active lines per frame.
Each output line is calculated from up to seven input lines
stored in line memories containing main or helper
information. The various lines are multiplied by switched
coefficients, changing every line within a sequence of four
lines, depending on the specific mode (CAMERA or FILM).
In case of standard PAL reception, the VERIC is switched
to bypass mode controlled by the signal INTPOL.
For multi-PIP processing the VERIC is also switched to
bypass mode, but controlling of FM2/3 is different (see
Fig.6). The total signal delay between the MACPACIC
input and the VERIC output is one line for this mode.
FM2/3 are driven with 32 MHz clock frequency.
The non-multiplexed input data are clocked out with
The chrominance processing is carried out by the vertical
interpolation filter (poly phase filter).
In CAMERA and FILM mode, intra-field vertical sample
rate conversion is carried out.
One output line is calculated out of three or four lines in
CAMERA or FILM mode using different coefficients or
passed through in bypass mode.
The VERIC controller generates the necessary internal
control signals for the line memories, formatters,
reformatters, the selector signals for the multiplexers and
the read signals for the field memories FM2/3.
The system control input signals EVEN_FIELD, INTPOL
and FILM are derived from the control part of the
MACPACIC. The field selection information EVEN_FIELD
is related to the input data of the MACPACIC and is
adapted in the VERIC to its input data.
Modes and delays
The PALplus module can operate in two different
· Full PALplus configuration (MACPACIC and VERIC)
· Stand alone MACPACIC.
The vertical interpolation of the VERIC can be activated by
the signal INTPOL depending on the PALplus signalling
bits, transmitted in line 23 indicating the type of signal
However, the delay between input data of the MACPACIC
and output data of the VERIC always has to be 1.5 fields.
This is achieved with a suitable read timing of the field
memories FM2 and FM3 controlled by VA_AI which is
derived from the field length measurement in the
In case of INTPOL = LOW and additionally FILM = HIGH
(FILM mode), the VERIC is switched to multi-PIP mode.
In case the delay between input of the MACPACIC and
output of the VERIC is one line (1024 CLK_16 periods).
The luminance input range of the main and helper signal
has the following values:
Main signal: black = 16, white = 191 (straight binary)
Helper signal: ±70, mid = 128 (straight binary)
Chrominance format: ±90, mid = 0 (two’s complement).
Luminance format: black = 16, white = 191 (straight
Blanking: code 16
Chrominance format: ±90, mid = 0 (two’s complement)
Blanking: code 0.
The pins TEST1, TEST2 and TEST3 are provided to
perform the IC test activities, such as scan test.
The pins TRSTN, TDI, TMS, TCK and TDO_VE are
intended for a boundary scan test.
SAA4996H Motion Adaptive Colour Plus And Control IC (MACPACIC) for PALplus:
· Motion adaptive colour plus decoding
· Helper AGC/AOC
· Helper decompanding
· Memory controlling
· VERIC controlling.
2 GENERAL DESCRIPTION
The SAA4996H (MACPACIC) performs the Motion
Adaptive Colour Plus (MACP) processing which is a
dedicated field comb filter technique exploited for the
The integrated circuit is especially designed to be used in
conjunction with the SAA4997H Vertical Reconstruction IC
(VERIC) to decode the transmitted PALplus video signals
in PALplus colour TV receivers.
In addition, a hardware configuration ‘stand-alone
MACPACIC’ with only two field memories (FM1 and FM4)
is also possible. In this condition no helper lines are
processed and no vertical reconstruction is applied.
This configuration enables the Motion Adaptive Colour
Plus processing to be performed in non PALplus receivers.
The MACPACIC is designed to be used in the PALplus
decoder module of a PALplus colour TV receiver. The full
PALplus decoder module consists of two special
integrated circuits and four field memories, as illustrated in
The special ICs are as follows;
· Motion Adaptive Colour Plus And Control IC
(MACPACIC) for PALplus (SAA4996H)
· Vertical Reconstruction IC (VERIC) (SAA4997H).
Besides the full PALplus module, a configuration for
stand-alone Motion Adaptive Colour Plus processing
(MACP) is also possible (see Fig.6). In this event only
MACPACIC with FM1 and FM4 are necessary.
This configuration enables the MACP processing in
non-PALplus receivers to be performed.
The PALplus module is designed to operate in conjunction
with a 100 Hz feature box. All special requirements such
as the delay of the PALplus module, bypass modes and
generation of the necessary control and clock signals will
7.1.1 DATA PROCESSING
The MACPACIC includes the decompanding functions for
the helper lines and the motion adaptive
luminance/chrominance separation in accordance with the
PALplus system description REV. 3.0 with some
· The system operates at a clock frequency of 16 MHz
· The Y:U:V format is 4:1:1 instead of 4:2:2
· The filter DEC_MD_UV_LPF is not implemented
· If noisy helper signals are received, the helper
bandwidth and/or amplitude can be reduced
· Automatic gain control of the helper signal with respect
to the luminance signal.
The input signals are the BB(helper)/CVBS and
chrominance signals which are derived from the
analog-to-digital converter (ADC).
At its outputs the MACPACIC delivers separate luminance
and chrominance signals, each one free from
cross-artefacts as main signal, as well as decompanded
and filtered helper signals. For standard input signals and,
in the event of MultiPIP mode with the help of a
PIP module, the MACPACIC can be switched to different
Memory control, PALplus system controlling and clock
generation (from the incoming 16 MHz and 32 MHz
line-locked clocks) are implemented in the MACPACIC.
All clocks and control signals necessary for the PALplus
module (excluding read control of FM2/FM3) are
generated in the controller part. Inputs are reference
signals, clocks and control signals delivered by the
colour/helper decoder IC (TDA9144), and the 100 Hz
memory controller, i.e. ECO4 (SAA4952) or ECOBENDIC
(SAA4970). The MACPACIC also receives control
information via a three-wire serial interface (SNERT-bus)
from the microprocessor in the 100 Hz feature box.
7.2 General requirements
The PALplus IC set is designed to operate in conjunction
with the PHILIPS 100 Hz feature box. All requirements
with respect to this combination are fulfilled.
The special requirements are as follows;
· The signal processing is adapted to the analog
preprocessing in the TDA9144 for luminance, helper
and chrominance signals
· Clock rate and clock generation
· Some special control signals are generated in the
· The field length must be measured and used to set the
delay of the full PALplus module to 1.5 fields
· A SNERT interface is used to transfer control data to
and from the PALplus module
· MultiPIP with the help of a PIP module is possible
· Results of noise measurements influence the helper
· Automatic gain and offset control is implemented
· Reference signals in line 22 are used for inverse set-up
· Noise measurement implemented
· Boundary scan test implemented
· Preset of internal recursive parts for testing.
7.3 Hardware configurations and delays
Two general hardware configurations are possible.
7.3.1 FULL PALPLUS MODULE (see Fig.5)
The delay from input to output is 1.5 fields rounded to
complete lines, also in the bypass mode. Therefore, the
number of input lines of the odd and even fields must be
measured. The result of this measurement is then used to
generate the required delay.
In the MultiPIP mode the delay of the full PALplus module
is one line.
7.3.2 STAND-ALONE MACPACIC (see Fig.6)
In this situation only the MACPACIC with FM1 and FM4
are necessary. No helper lines are processed and no
vertical reconstruction with the VERIC is applied.
The delay from input to output is one field, one line and
some clocks of processing delay, this also applies in the
bypass mode. In the MultiPIP mode the delay is two clocks
7.4 Analog processing in front of the PALplus
In front of the MACPACIC an analog colour/helper
decoder (TDA9144) performs the colour and helper
Because of the requirement that a standard ADC with
clamping on 16 should be used for CVBS and helper
analog-to-digital conversion, a black (letter box lines) and
mid grey (helper lines) shift is applied in the colour/helper
decoder. For reshifting without errors in the digital domain
these shift levels are inserted as a reference in line 22.
In the event of stand-alone MACPACIC and PALplus input
signals the helper demodulation must be switched off.
No special actions are taken in the colour/helper decoder
for chrominance processing.
In this document U will refer to -(B - Y) and V will refer to
-(R - Y).
In combination with the full PALplus module with letter box
input signals (16:9), the PAL delay line of the colour/helper
decoder must be switched off. This is because this function
is also implemented in the vertical reconstruction filter of
the VERIC. For all other input signals and for stand-alone
MACPACIC the PAL delay line must be switched on.
The device consists of
4 main parts:
· Luminance and helper processing
· Chrominance processing
· Chrominance motion detection
The clock rate of the input data is 16 MHz. Internally, the
device operates at a 32 MHz clock frequency. The clock
rate of the output data is either 32 MHz (in combination
with FM2, FM3 and VERIC) or 16 MHz for stand-alone
The delay of the full PALplus module is 1.5 fields in the
PALplus and bypass mode. A field length measurement is
implemented. For MultiPIP with the help of a PIP module
the delay of the PALplus module is one line.
For stand-alone MACP the delay is one field, one line and
some clocks of processing delay.
For MultiPIP with the help of a PIP module the delay of
MACPACIC is two clocks (CLK_16).
7.6 Luminance and helper processing
7.6.1 INPUT RANGE
To use a standard ADC with clamping on 16, a black
set-up for the CVBS signal and a black/mid grey set-up for
the helper signal has to be performed in the colour/helper
decoder. The shift values for black set-up and mid grey
set-up are inserted in line 22.
All values are nominal values.
clamp level: 16
black set-up: 51
format: 8-bit, straight binary
mid grey set-up: 121
range: (121 - 60) to (121 + 60) = 61 to 181
format: 8-bit, offset binary
Y (standard input):
peak white: 191
format: 8-bit, straight binary
7.7 Luminance processing
The luminance and the helper processing have two input
branches. One input is an 8-bit wide 16 MHz data stream
from the ADC. The other is an 8-bit wide 16 MHz data
stream from the field memory (FM1). The odd field of an
input frame is stored in the field memory FM1. In the even
field of a frame, the even field together with the delayed
odd field is processed by the MACPACIC.
To remove the chrominance part of the incoming
composite video signal, the Motion Adaptive Colour Plus
technique is applied. Colour Plus is a dedicated comb filter
technique, which makes full use of the correlation of two
During processing the data of the odd and even fields are
separated in a high-pass and low-pass part. The high-pass
part consists of the luminance high-pass component and
the modulated chrominance signal. Due to the phase
difference of the colour carrier of 180° from the odd to the
even field, the chrominance signal can be removed by
adding the high-pass signals.
This processing will work successfully in the film mode,
because scanned film material is motionless within the two
fields of one frame. In the camera mode a motion detector
fades down the luminance high-pass component if motion
The following vertical low-pass filters perform a vertical
interpolation of the high-pass part by the factor of two.
In the event of bad signal conditions, the residual
cross-luminance signal, caused by clock jitter between two
fields, can be reduced by using this filter as a 2D comb
filter. Therefore different sets of coefficients can be
selected via SNERT.
The luminance high-pass part and the luminance low-pass
part are then added.
The automatic gain control (AGC) and automatic offset
control (AOC) functions use reference lines 23,
623 and 22 to reduce errors in the vertical reconstruction
in the VERIC. This is to reduce the effects of any errors
that might be caused due to variations in the conventional
PAL references in the signal during the transmission chain
with respect to the levels of the luminance letter box and
LUMINANCE HELPER PROCESSING
In the event of incoming helper, the switchable low-pass
filter acts as an inverse shaping and bandwidth reduction
filter for the helper lines. If a distorted helper signal is
transmitted, the bandwidth can be reduced from 2.2 MHz
(0 dB) to 1.0 MHz or to 0.5 MHz (-3 dB).
The high-pass part of the luminance processing is not
used for the helper processing.
To stabilize the transmitted helper signal against noise
disturbances, the encoder performs a companding of the
signal. In the decoder the decompanding is performed in
the AGOC block (see Fig.7).
7.8 Output signals
In the event of full PALplus configuration, odd and even
field data are multiplexed to a 32 MHz data stream.
For the stand-alone MACPACIC, the processed even field
data is connected to the field memory FM1 and the odd
field data is switched to the output Y_MA. In the next field
the stored even field data is read out of the field memory
FM1 and then connected to the output of the MACPACIC.
If MultiPIP mode is selected, the luminance input data from
the ADC (Y_ADC) is switched directly to the output Y_MA.
In the bypass mode the luminance data processing is
switched off and multiplexed data is connected to the
The clock frequency of the output data Y_MA is 32 MHz for
the MACPACIC in combination with the VERIC, or 16 MHz
for the stand-alone MACPACIC.
The digital data stream at the input of the PALplus decoder
module contains three reference lines;
· Reference line 22 consists of the black and mid grey
set-up, inserted by the colour/helper decoder
· The second half of line 23 contains the black level
reference and the maximum negative reference for the
PALplus helper lines
· The first half of line 623 contains reference values for
the black level and the peak white level for the main
The reference lines 23 and 623 are generated by the
PALplus encoder and are used to reduce the effects of any
errors that might be caused due to variations in the
transmission chain with respect to the levels of the
luminance letter box and helper signals.
The content and the timing of the reference lines are
illustrated in Figs 13, 14 and 15.
7.9.1 LINE 22 OFFSET REFERENCE MEASUREMENT
Due to the fact that a standard ADC with a clamping level
of 16 should be inserted for CVBS and helper
analog-to-digital conversion, a black offset for the letter
box lines and a mid grey offset for the helper lines are
carried out in the colour/helper decoder. These offset
values are inserted as references in line 22 to reshift the
CVBS and helper signals in the digital domain without
errors. Therefore, a measurement of the offsets in line 22
is necessary. The average value of the real offset is
calculated from 64 samples and substacted from the
CVBS and helper signal. The CVBS and helper input
signal are illustrated in Fig.16.
7.9.2 LINE 23 AND 623 AMPLITUDE REFERENCE
The helper and luminance amplitude measurement
consists of averaging 64 samples each of;
Helper zero (MHZ).
Helper maximum (MHM).
Luminance black (MLB).
Luminance white (MLW).
Measured helper amplitude = helper maximum minus
Measured luminance amplitude = luminance white minus
Frame integration is performed with a feed back factor of
(1 - K) = 1¤16. The frame integration part can be preset with
the first measured value. Preset is controlled with the
preset bit transmitted via SNERT.
7.9.3 NOISE MEASUREMENT IN LINE 23 AND 623
For the helper lines the noise measurement is carried out
in reference line 23 and for the letter box lines in reference
line 623. Both measurements are active in the black
reference levels of line 23 and line 623 respectively.
The processing of the noise measurement for the helper
signal and the letter box signal is performed in the same
First the average value of 64 samples is calculated.
The single actual sample values are subtracted from this
average value and the sum of these absolute differences
are frame integrated. The integration factor is 1 - K = 1¤16.
The frame integration part can be preset with the first
measured value. Preset is controlled via a bit from the
7.10 Automatic gain and offset control
The automatic gain and offset control circuit evaluates the
results of the reference data, which are derived from
reference lines 22, 23 and 623 to eliminate any offset and
gain differences between the letter box lines and the
helper lines. This is caused during transmission of the
7.10.1 SNERT CONTROL BITS INFLUENCING THE AGC AND
MacpOn: If line 22 is not detected this bit will be ignored
and the MACP processing (and thus AGC and AOC) is
FilmOn: If line 22 is not detected, the VERIC operates in
HlpM1, HlpM0: In adaptive and fixed helper processing
modes (HlpM1 = 1, HlpM0 = X) AGC and AOC are
Table 1 Control bits HlpM1 and HlpM0
7.10.2 GAIN CONTROL
If line 22 reference is present in a frame, the luminance
input signal contains black set-up and reduced amplitude.
The luminance gain then is 1.25. If line 22 is not valid the
luminance gain is 1.0.
The helper gain is controlled by the measured helper
amplitude in line 23 to match the helper amplitude to the
decompanding table. After decompanding the helper
amplitude is controlled by the measured luminance
amplitude in line 623, to obtain the correct
luminance/helper ratio for the QMF filter in the VERIC.
HlpM1 HlpM0 FUNCTION
0 0 no helper processing
(any aspect ratio, without helper)
0 1 helper set to zero
(up-conversion without helper)
1 0 adaptive helper processing (helper
processing controlled by reference
amplitudes and noise in the helper
1 1 fixed helper processing (fixed gain
values loaded via SNERT-bus)
The helper amplitude is reduced when the measured noise
exceeds a certain threshold level. These thresholds are
conveyed via the SNERT-bus. The reduction of the helper
amplitude, before decompanding, ensures that more noise
is cancelled by the coring. The adaptive helper gain control
is switched off when the SNERT bits HlpM1 and HlpM0 are
both at logic 1. In this condition the helper gain is defined
by the values FixHlp and FixMain via the SNERT-bus.
If the measured helper or luminance amplitude is below
the threshold level, or when line 22 is not valid, the helper
is switched off.
7.10.3 OFFSET CONTROL
As long as line 22 reference is present, luminance and
helper offset are controlled by line 22. If line 22 is not valid
the offset value is fixed to 16.
For luminance offset control a hysteresis function,
controlled by SNERT, is applied to the measured
7.10.4 HELPER AMPLITUDE AND BANDWIDTH CONTROL
In the event of noisy helper signals the helper amplitude
and bandwidth can be reduced to avoid disturbances in
the inverse QMF processing in VERIC.
Five thresholds are therefore transmitted via SNERT.
These thresholds are compared with the measured helper
noise value. The results are used to control a state
machine with five states.
The state machine is initialized with the preset bit from
SNERT or when line 22 is valid for the first time.
The output states are used to control the helper amplitude
and bandwidth as shown in Fig.8 and Tables 2 and 3.
7.11 Output range
Luminance lines: straight binary, black = 16, white = 191.
PALplus helper lines: offset binary, 128 ±70.
7.12.1 INPUT RANGE
The input is a 4:1:1 sequential 4-bit wide UV signal with a
16 MHz clock frequency. Originally the U and V signals
were 8 bits wide with a sampling frequency of 4 MHz each.
The range is 0 ±90 in two’s complement format for
U and V.
7.12.2 CHROMINANCE PROCESSING
The Motion Adaptive Colour Plus technique is also applied
in the chrominance processing to remove the luminance
part from the incoming demodulated UV signal.
In the modulated domain the chrominance signal can be
generated by subtracting the odd and even field data due
to the 180° phase difference of the colour subcarrier.
The colour decoder eliminates the phase difference of the
chrominance signals, but now the luminance signals will
obtain the phase difference of 180°.
By adding the odd and even field data, the cross-colour
free chrominance signal (UVifa) is generated.
This processing will work successfully in the film mode,
because scanned film material is motionless within the two
fields of one frame. In the camera mode, where each field
represents an individual picture, a motion detector fades
down the chrominance high-pass component if motion is
When chrominance motion occurs, the encoder fades
down the high-pass luminance signal. In that event, the
motion detector in the decoder will switch the chrominance
part from intra frame average processing to the incoming
Odd and even field data are multiplexed and connected to
the output of MACPACIC.
The chrominance processing has two input branches (see
Fig.9). One input branch is the direct chrominance input
path from the ADC. The other input branch is the output of
the field memory FM1. The odd field of a frame is stored in
the field memory FM1. In the even field of a frame the
delayed odd field and the incoming even field are
processed with the motion adaptive colour plus algorithm
to the cross-colour free chrominance output data.
By adding the incoming chrominance signals of the odd
and even fields, the intra frame average chrominance
signal (UVifa) is generated.
For the chrominance motion detector this signal is stored
after formatting in the memory FM4 (UV_TO_FM4).
7.12.3 OUTPUT SIGNALS
The output data rate is 32 MHz for MACPACIC in
combination with VERIC and 16 MHz for stand-alone
MACPACIC or in the MultiPIP mode.
In the MultiPIP mode the chrominance data from the ADC
(UV_ADC) is switched directly to the output UV_MA.
In the bypass mode the chrominance data processing is
switched off and the multiplexed odd and even field data
are connected to the MACPACIC output.
7.12.4 OUTPUT RANGE
The range is 0 ±90 in two’s complement format for
U and V
Chrominance motion detection
The PALplus system has two modes of operation.
These are called film mode, which is only used with film
sources, and camera mode which is applied for normal
50 Hz interlaced video sources. The motion detector is
only necessary in the camera mode because, in the
film mode, the two fields of a frame are sampled from the
same picture of the film.
The chrominance motion detector has two input branches
(see Fig.10). One input branch is the intra frame average
of the actual frame, the other input branch is the intra
frame average signal of the previous frame. This signal is
delivered by the field memory FM4.
Subtraction of the two intra frame average signals
generates the chrominance inter frame difference.
PAL averaging eliminates phase errors. This PAL
averaging can be switched off when the PAL delay line in
the colour decoder is active.
A look-up table (LUT) generates the motion signal from the
chrominance signal. A comparator generates a
chrominance control switch signal (CS). A horizontal
interpolation filter interpolates a 16 MHz motion signal.
The motion high-pass luminance control signal M_YL is
provided by another LUT.
7.14 Intelligent residual cross-luminance reduction
The IRXR block diagram is illustrated in Fig.10.
The MACP algorithm requires good stability of the
sampling clock between both fields, because samples
from both fields will be combined, in order to suppress
cross-colour and cross-luminance. Investigations with
currently used sync/clock circuitry have shown that the
stability of these clocks is not as good as it should be for
perfect performance of the MACP algorithm.
When a MACP signal is received the colour subcarrier trap
in the TDA9144 is bypassed and the input signal of the
SAA4996H still contains the modulated colour component.
The MACP technique always processes corresponding
lines of two successive fields (having an offset of
312 lines). These lines will have the same high-frequency
luminance information (YH) and inverted colour
information due to the phase/line relationship in PAL.
With an ideal sampling grid, the two inverted colour signals
will be cancelled completely by addition so that no
cross-luminance (XL) remains in the resulting picture.
When the sampling grid is not optimum (e.g. shifted a little
in one field with respect to the other field), the cancellation
of both modulated colour signals will not be complete and
some residual XL will remain. The amount of residual XL
is proportional to the amplitude of the modulated colour
signal and to the following formula;
The timing error is determined by the type of circuitry used
for the sync/clock generation and by the amount of
noise/disturbance in the input signal (more
noise/disturbance generally leads to larger timing errors).
The intelligent residual cross-luminance reduction (IRXR)
tries to cancel this residual cross-luminance (XL), by
reducing the amount of YH depending of the amplitude of
the modulated colour signal.
The saturation indication signal (SD) is generated by the
intra frame average signal of the actual frame with the help
of a look-up table (LUT). A horizontal interpolation filter
interpolates a 16 MHz saturation detection signal SD.
Another LUT transforms the SD signal into the signal
SD_YL, which determines the amount of YH to be
reduced. Different characteristics curves of the LUT can
be selected either via SNERT (SEL_SD_YL) or
automatically depending on the measured noise value
(SelSdYl), see Fig.11 and Table 4.
The IRXR function can be disabled or enabled via SNERT
by the EN_IRXR bit.
The output signal YL is generated from the three YH
reduction signals SD_YL, M_YL and NM_YL.
This combination is performed with a minimum detection
circuit. The amount of YH that is allowed is the lowest of
the three input signals. Whenever one input signal
indicates a reason to reduce the YH, this should be
performed independently of the other input signals.
In the event of film mode the signals NM_YL (Fig.12 and
Table 5) and M_YL are over-written with the value 4.
Motion detector processing is not active for these signals
in the film mode. Such film overriding is not allowed for the
SD_YL signal, because the residual XL can occur in the
film mode as well as in the camera mode.
SAB9077H Picture-In-Picture (PIP) controller:
· 50/60 Hz PIP modes possible
· Twin PIP in interlaced mode at 8-bit resolution
· Sub-title mode features built in
· Large display fine positioning area, both channels
· Only 2 Mbit needed as external VDRAM
(2 ´ 1 Mbit or 1 ´ 2 Mbit)
· Four 8-bit Analog-to-Digital Converters (ADCs; > 7-bit
performance) with clamp circuit
· Most PIP modes handle interlaced pictures without joint
· Two PLLs which generate the line-locked clocks for the
· Display PLL to generate line-locked clock for the display
· Three 8-bit Digital-to-Analog Converters (DACs)
· 4 : 1 : 1 data format
· Data reduction factors 1 to 1, 1 to 2, 1 to 3 and 1 to 4,
horizontal and vertical independent.
· Single and double PIP modes can be set
· Full field still mode available
· Several aspect ratios can be handled
· Reduction factors can be set freely
· Selection of vertical filtering type
· Freeze of live pictures
· Fine tuned display position, H (8-bit), V (8-bit),
both channels independent
· Fine tuned acquisition area, H (4-bit), V (8-bit),
both channels independent
· Eight main borders, sub-borders and background
· Border and background brightness adjustable, 30%,
50%, 70% and 100% IRE
· Several type of decoder input signals can be set.
The SAB9077H is a picture-in-picture controller for
multi-standard TV-sets. The circuit contains ADCs,
reduction circuitry, memory control, display control and
It inserts one or two live video signals with original or
reduced sizes into a live video signal. All video signals are
expected to be analog base band signals. The conversion
into the digital environment and back to the analog
environment is done on chip. Internal clocks are generated
by two acquisition PLLs and a display PLL.
The two PIP channels and a large external memory offer a
wide range of PIP modes. The emphasis is put on single
PIP, double PIP, split-screen mode and many multi-PIP
The internal chrominance format used is 4 : 1 : 1. It is
expected that the bandwidth of the input signals is limited
to 4.5 MHz for the Y input and 1.125 MHz for the U/V
The Y input is sampled with a 1728 ´ Hsync (»27.0 MHz)
clock and is filtered and down sampled to the internal
864 ´ Hsync (»13.5 MHz) pixel rate.
The U and V inputs are multiplexed and sampled with a
432 ´ Hsync clock and down sampled to the internal
216 ´ Hsync (»3.375 MHz) pixel rate.
Synchronization is done via the acquisition HSync and
VSync pins. With the acquisition fine positioning added to a
system constant the starting point of the acquisition can be
The acquisition area is 672 pixels/line and 228 lines/field
for NTSC and 276 lines/field for PAL. Both main and
sub-channel are equivalent in handling the data.
The internal display pixel rate is 864 ´ DPHsync which is
13.5 MHz. This pixel rate is upsampled by interpolation to
1728 ´ DPHsync before the DAC stage.
The display background is an area of 696 pixels for both
PAL and NTSC, 238 lines for NTSC and 286 lines for PAL.
This can be put on/off by the BGON bit independent of the
PIPON bits. This area can be moved by the display
background fine positioning (BGHFP and BGVFP).
Its colour is determined by the BGCOL and BGBRT bits.
Within this area PIPs are defined dependent on the
PIP mode. The PIP sizes are determined by the display
reduction factors as is shown in Table 2. Whether a PAL or
NTSC fixed number is used is depends on the DPAL bit.
The display fine positioning determines the location of the
PIPs with respect to the background. sub and
main-channel both have their independent PIP size and
The two independent acquisition channels can also be
controlled independently on the display side. A wide
variety of modes is possible but a subset of 7 modes is
fixed and can be set easily by the I2C-bus. An overview of
the preconditioned modes is given in Table 3. For all PIP
modes the main and sub-display fine positioning must be
set to obtain a display configuration.
The internal data path has an 8-bit resolution and 4 : 1 : 1
data format. The communication to the external VDRAM
takes place at 864 ´ Hsync (both display and acquisition).
Approximately 800 8-bit words can be fetched from the
external VDRAM in one display line which is not enough to
display one complete display line with true 8-bit resolution.
Two methods of reducing data are available. One is simply
skipping the 8-bit to 6-bit (SKIP6, I2C-bus bit) and the other
is a small form of data reduction to come from 8-bit to 6-bit
(SMART6, I2C-bus bit). If both bits are set to logic 0 the
device is in true 8-bit resolution mode. For the twin PIP
mode the main channel is not placed in the VDRAM but in
an internal buffer, 8 bit resolution is then possible for both
TDA6111Q Video output amplifier
· High bandwidth and high slew rate
· Black-current measurement output for Automatic
Black-current Stabilization (ABS)
· Two cathode outputs; one for DC currents, and one for
· A feedback output separated from the cathode outputs
· Internal protection against positive appearing
Cathode-Ray Tube (CRT) flashover discharges
· ESD protection
· Simple application with a variety of colour decoders
· Differential input with a designed maximum common
mode input capacitance of 3 pF, a maximum differential
mode input capacitance of 0.5 pF and a differential input
voltage temperature drift of 50 mV/K
· Defined switch-off behaviour.
The TDA6111Q is a video output amplifier with 16 MHz
bandwidth. The device is contained in a single in-line 9-pin
medium power (DBS9MPF) package, using high-voltage
DMOS technology, intended to drive the cathode of a
The cathode output is protected against peak currents
(caused by positive voltage peaks during high-resistance
flash) of 5 A maximum with a charge content of 100 mC.
The cathode is also protected against peak currents
(caused by positive voltage peaks during low-resistance
flash) of 10 A maximum with a charge content of 100 nC.
The TDA6111Q incorporates protection diodes against
CRT flashover discharges that clamp the cathode output
pin to the VDDH pin. The DC supply voltage at the VDDH pin
has to be within the operating range of 180 to 210 V to
ensure that the Absolute Maximum Rating for VDDH of
250 V will not be exceeded during flashover. To limit the
diode current, an external 680 W carbon high-voltage
resistor in series with the cathode output and a 2 kV spark
gap are needed (for this resistor-value, the CRT has to be
connected to the main PCB). This addition produces an
increase in the rise and fall times of approximately 5 ns
and a decrease in the overshoot of approximately 4%.
VDDH to GND must be decoupled:
1. With a capacitor >20 nF with good HF behaviour
(e.g. foil). This capacitance must be placed as close
as possible to pins 6 and 4, but definitely within 5 mm.
2. With a capacitor >10 mF on the picture tube base print
(common for three output stages).
VDDL to GND must be decoupled:
1. With a capacitor >20 nF with good HF behaviour
(e.g. ceramic). This capacitance must be placed as
close as possible to pins 2 and 4, but definitely within
The switch-off behaviour of the TDA6111Q is defined:
when the bias current becomes zero, at VDDL (pin 2) lower
than approximately 5 V, all the output pins
(pins 7, 8 and 9) will be high.
TDA8177 VERTICAL DEFLECTION BOOSTER
Designed for monitors and high performance TVs,
the TDA8177 vertical deflection booster delivers
flyback voltages up to 70V.
The TDA8177 operates with supplies up to 35V and
provides up to 3APP output current to drive the yoke.
The TDA8177 is offered in HEPTAWATT package.
.OUTPUT CURRENT UP TO 3.0APP
.FLYBACK VOLTAGE UP TO 70V (on Pin 5)
.SUITABLE FOR DC COUPLING APPLICATION
83C654 CMOS single-chip 8-bit microcontrollerDESCRIPTION
The P83C654 Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
83C654 has the same instruction set as the
80C51. Two versions of the derivative exist:
83C654 — 16k bytes mask programmable
87C654 — EPROM version (described in a
separate data sheet)
This device provides architectural
enhancements that make it applicable in a
variety of applications for general control
systems. The 83C654 contains a non-volatile
16k × 8 read-only program memory, a volatile
256 × 8 read/write data memory, four 8-bit I/O
ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), a
multi-source, two-priority-level, nested
interrupt structure, an I2C interface, UART
and on-chip oscillator and timing circuits. For
systems that require extra capability, the
8XC654 can be expanded using standard
TTL compatible memories and logic.
The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte and 17
three-byte. With a 16(24)MHz crystal, 58% of
the instructions are executed in 0.75(0.5)ms
and 40% in 1.5(1)ms. Multiply and divide
instructions require 3(2)ms.
• 80C51 central processing unit
• 16k × 8 ROM expandable externally to
• 256 × 8 RAM, expandable externally to
• Two standard 16-bit timer/counters
• Four 8-bit I/O ports
• I2C-bus serial I/O port with byte oriented
master and slave functions
• Full-duplex UART facilities
• Power control modes
– Idle mode
– Power-down mode
• ROM code protection
• Extended frequency range: 3.5 to 24 MHz
• Three operating ambient temperature
0 to +70°C
–40 to +85°C
–40 to +125°C
ROM CODE PROTECTION
The 83C654 has an additional security
feature. ROM code protection may be
selected by setting a mask–programmable
security bit (i.e., user dependent). This
feature may be requested during ROM code
submission. When selected, the ROM code
is protected and cannot be read out at any
time by any test mode or by any instruction in
the external program memory space.
The MOVC instructions are the only
instructions that have access to program
code in the internal or external program
memory. The EA input is latched during
RESET and is “don’t care” after RESET
(also if the security bit is not set). This
implementation prevents reading internal
program code by switching from external
program memory to internal program memory
during a MOVC instruction or any other
instruction that uses immediate data.
XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol,
To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.
A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-on, the voltage on VDD and RST must
come up at the same time for a proper
In the idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 2
shows the state of the I/O ports during low
current operating modes.
I2C SERIAL COMMUNICATION —
The I2C serial port is identical to the I2C
serial port on the 8XC552. The operation of
this subsystem is described in detail in the
8XC552 section of this manual.
Note that in both the 8XC652/4 and the
8XC552 the I2C pins are alternate functions
to port pins P1.6 and P1.7. Because of this,
P1.6 and P1.7 on these parts do not have a
pull-up structure as found on the 80C51.
Therefore P1.6 and P1.7 have open drain
outputs on the 8XC652/4.
PHILIPS 32PW9525 /12 MATCH LINE Video signal scan conversion CHASSIS MG3.1E
1. A scan conversion method of generating an output video signal from an interlaced input signal, comprising the steps of:
furnishing a first signal having first lines (Fi (x-(0, 1)T, n)) corresponding to original lines of said interlaced input signal, and second separate lines (Fi (x, n)) in addition to said first lines (Fi (x-(0, 1)T, n)); and
providing a second signal which is delayed or advanced with respect to said first signal, said second signal having first processed lines (Fout (x-(0, 1)T -D, n-1)) corresponding to said original lines, and second processed lines (Fout (x-D, n-1)) corresponding to said second lines (Fi (x, n));
characterized in that output lines (Fout (x, n)) of said output video signal are obtained in dependence upon
a first mixer-generated difference between said first processed lines (Fout (x-(0, 1)T -D, n-1)) and said first lines (Fi (x-(0, 1)T, n)), and
a second mixer-generated difference between said second processed lines (Fout (x-D, n-1)) and said second lines (Fi (x, n)).
2. A method as claimed in claim 1, wherein said output video signal is a sequentially scanned video signal, and wherein the method comprises the further step of combining said first signal and said second signal to obtain an output sequentially scanned video signal having first output lines (Fout (x-(0, 1)T, n)) corresponding to said original lines, and said output lines (Fout (x, n)) between said first output lines (Fout (x-(0, 1)T, n)).
3. A method as claimed in claim 2, wherein said output lines (Fout (x, n)) of said output video signal are obtained further in dependence upon a relation (k2) between said first lines (Fi (x-(0, 1)T, n)) and said first output lines (Fout (x-(0, 1)T, n)).
4. A method as claimed in claim 1, wherein said first processed lines (Fout (x-(0, 1)T -D, n-1)) and said second processed lines (Fout (x-D, n-1)) are obtained by means of a motion-compensated interpolation.
5. A method as claimed in claim 2, wherein said output lines are obtained in dependence upon said second difference and a third difference between said first output lines (Fout (x-(0, 1)T, n)) and said first processed lines (Fout (x-(0, 1)T -D, n-1)).
6. A method as claimed in claim 2, wherein said combining step is controlled such that a difference between said output lines (Fout (x, n)) and said second processed lines (Fout (x-D, n-1)) corresponds to a difference between said first output lines (Fout (x-(0, 1)T, n)) and said first processed lines (Fout (x-(0, 1)T -D, n-1)).
7. A method as claimed in claim 1, wherein said first and second differences are absolute differences.
8. A scan conversion apparatus for generating an output video signal from an interlaced input signal, comprising:
means for furnishing a first signal having first lines (Fi (x-(0, 1)T, n)) corresponding to original lines of said interlaced input signal, and separate second lines (Fi (x, n)) in addition to said first lines (Fi (x-(0, 1)T, n)); and
means for providing a second signal which is delayed or advanced with respect to said first signal, said second signal having first processed lines (Fout (x-(0, 1)T -D, n-1)) corresponding to said original lines, and second processed lines (Fout (x-D, n-1)) corresponding to said second lines (Fi (x, n));
characterized in that said scan conversion apparatus further comprises means for generating output lines (Fout (x, n)) of said output video signal in dependence upon
a first mixer-generated difference between said first processed lines (Fout (x-(0, 1)T -D, n-1)) and said first lines (Fi (x-(0, 1)T, n)), and
a second mixer-generated difference between said second processed lines (Fout (x-D, n-1)) and said second lines (Fi (x, n)).
9. An apparatus as claimed in claim 8, wherein said output video signal is a sequentially scanned video signal, and wherein the apparatus further comprises means for combining said first signal and said second signal to obtain an output sequentially scanned video signal having first output lines (Fout (x-(0, 1)T, n)) corresponding to said original lines, and said output lines (Fout (x, n)) between said first output lines (Fout (x-(0, 1)T, n)).
10. An apparatus as claimed in claim 9, wherein said output lines (Fout (x, n)) of said output video signal are obtained further in dependence upon a relation (k2) between said first lines (Fi (x-(0, 1)T, n)) and said first output lines (Fout (x-(0, 1)T, n)).
11. An apparatus as claimed in claim 9, wherein said output lines are obtained in dependence upon said second difference and a third difference between said first output lines (Fout (x-(0, 1)T, n)) and said first processed lines (Fout (x-(0, 1)T -D, n-1)).
12. An apparatus as claimed in claim 9, wherein said combining means are controlled such that a difference between said output lines (Fout (x, n)) and said second processed lines (Fout (x-D, n-1)) corresponds to a difference between said first output lines (Fout (x-(0, 1)T, n)) and said first processed lines (Fout (x-(0, 1)T -D, n-1)).
13. A video signal display apparatus comprising:
means for supplying an interlaced input signal;
a scan conversion apparatus for generating an output video signal from said interlaced input signal, as claimed in claim 8; and
means for displaying (16) said output video signal.
1. Field of the Invention
The invention relates to a method and apparatus for video signal scan conversion, and to a video signal display apparatus comprising such a conversion apparatus.
2. Description of the Related Art
WO-A-95/27362, corresponding to U.S. Pat. No. 5,532,750 (Attorney's reference PHN 14,794), discloses a method of converting an interlaced video signal into an output sequentially scanned video signal. A first sequentially scanned video signal is furnished in dependence upon the interlaced video signal. Subsequently, a motion-compensated sequentially scanned signal is furnished in dependence upon the first sequentially scanned video signal. All video lines of the output sequentially scanned video signal are generated in dependence upon both the first sequentially scanned video signal and the motion-compensated sequentially scanned signal to prevent inaccuracies in motion vectors used in the motion-compensated processing operation from resulting in visible distortions. The first sequentially scanned video signal and the motion-compensated sequentially scanned signal are combined to furnish the output sequentially scanned video signal by means of a first mixer for first lines positionally corresponding to original lines of a present field of the interlaced video signal, a second mixer for second lines positionally corresponding to interpolated lines between the original lines, and a multiplexer for line-alternately selecting an output of the first mixer or an output of the second mixer.
It is, inter alia, an object of the invention to provide an improved video signal scan conversion.
Accordingly, a first aspect of the invention provides a method of generating an output video signal from an interlaced input signal, comprising the steps of:
furnishing a first signal having first lines (F i (x-(0, 1) T , n)) corresponding to original lines of the interlaced input signal, and second lines (F i (x, n)) in addition to the first lines (F i (x-(0, 1) T , n)); and
providing a second signal which is delayed or advanced with respect to the first signal, the second signal having first processed lines (F out (x-(0, 1) T -D, n-1)) corresponding to the original lines, and second processed lines (F out (x-D, n-1)) corresponding to the second lines (F i (x, n));
in which output lines (F out (x, n)) of the output video signal are obtained in dependence upon
a first difference between the first processed lines (F out (x-(0, 1) T -D, n-1)) and the first lines (F i (x-(0, 1) T , n)), and
a second difference between the second processed lines (F out (x-D, n-1)) and the second lines (F i (x, n)).
Preferably, the output video signal is a sequentially scanned video signal, and the method comprises the further step of combining the first signal and said second signal to obtain the output sequentially scanned video signal having first output lines (F out (x-(0, 1) T , n)) corresponding to the original lines, and the output lines (F out (x, n)) between the first output lines (F out (x-(0, 1) T , n)). Advantageously, the output lines (F out (x, n)) of the output video signal are obtained further in dependence upon a relation between the first lines (F i (x-(0, 1) T , n)) and the first output lines (F out (x-(0, 1) T , n)).
A refinement of the first aspect of the invention provides that the output lines are obtained in dependence upon the second difference and a third difference between the first output lines (F out (x-(0, 1) T , n)) and the first processed lines (F out (x-(0, 1) T -D, n-1)), in which the first difference as well as the relation between the first lines and the first output lines are replaced by a third difference which is equivalent thereto in a preferred embodiment of the invention.
Another refinement of the first aspect of the invention provides that the combining step is controlled such that a difference between the output lines (F out (x, n)) and the second processed lines (F out (x-D, n-1)) corresponds to a difference between the first output lines (F out (x-(0, 1) T , n)) and the first processed lines (F out (x-(0, 1) T -D, n-1)). The above-mentioned aspects of the invention improve the consistency along the motion trajectory or, put in other words, a smoother picture is obtained for moving objects.
A second aspect of the invention provides a scan conversion apparatus for generating an output video signal from an interlaced input signal, comprising means for furnishing a first signal having first lines (F i (x-(0, 1) T , n)) corresponding to original lines of said interlaced input signal, and second lines (F i (x, n)) in addition to said first lines (F i (x-(0, 1) T , n)); and means for providing a second signal which is delayed or advanced with respect to said first signal, said second signal having first processed lines (F out (x-(0, 1) T -D, n-1)) corresponding to said original lines, and second processed lines (F out (x-D, n-1)) corresponding to said second lines (F i (x, n)); characterized in that said apparatus further comprises means for generating output lines (F out (x, n)) of said output video signal in dependence upon a first difference between said first processed lines (F out (x-(0, 1) T -D, n-1)) and said first lines (F i (x-(0, 1) T , n)), and a second difference between said second processed lines (F out (x-D, n-1)) and said second lines (F i (x, n)).
A third aspect of the invention provides a video signal display apparatus incorporating such a scan conversion apparatus as described.
In the drawings:
FIG. 1 illustrates an embodiment of a television receiver comprising a sequential scan converter in accordance with the present invention;
FIG. 2 shows an embodiment of a device for calculating mixer coefficients k1 and k2 for use in the embodiment of FIG. 1; and
FIG. 3 shows an embodiment of a device for calculating the mixer coefficient k1 for use in the embodiment of FIG. 1.
De-interlacing is a basic operation required for most video scanning format conversions. Vertical and temporal interpolation of image data cause practical and fundamental difficulties, as the conditions of the sampling theorem are generally not met in video signals. Linear methods, based on sampling rate conversion theory, therefore negatively influence the resolution and/or the motion portrayal. The more advanced algorithms can be characterized by their common attempt to interpolate the 3-D image data in the direction with the highest correlation. To this end, they either have an explicit or implicit detector to find this direction. In case of 1-D temporal interpolation the explicit detector is usually called a motion detector, for 2-D spatial interpolation it is called an edge detector, while the most advanced device estimating the optimal spatio-temporal 3-D interpolation direction is a motion estimator. The interpolation filter can either be recursive or transversal, but the number of taps in the temporal direction is preferably small.
Recently, some papers have been published proposing a recursive scheme for motion compensated sequential scan conversion (References  and ). Experiments indicate that the recursiveness yields a significant improvement of the motion-compensated median (Reference ), on which these algorithms are based, if good quality motion vectors are available. Furthermore, recursiveness is expected to allow an improved performance on critical velocities, compared to recently published methods applying generalized sampling theory (Reference ), if the velocities are accelerating. In this application an improved recursive sequential scan conversion algorithm is introduced that suppresses remaining artifacts of the prior art further. The invention provides the algorithms and a novel evaluation method that shows the improvement in an objective score. For high quality, sub-pixel accurate motion estimation the algorithm of (Reference ) is used.
2. De-interlacing techniques
In general, the samples required for the motion compensated de-interlacing do not exist in the time discrete input signal, e.g. due to non-integer velocities. In the horizontal domain this problem can be solved with linear Sampling Rate Conversion (SRC) theory, e.g. (Reference ), but not in the vertical domain, as the constraints of the sampling theorem are not met. Three different solutions for this problem have been proposed recently in the literature:
(1) A straight extension of the motion vector into earlier pictures until it points (almost) to an existing pixel (Reference ).
(2) The application of a generalized sampling theory (GST) (Reference ).
(3) Recursive de-interlacing of the signal (Reference  and ).
Solution (1) is valid only if we assume the velocity constant over a larger temporal instance. This is a rather severe limitation which makes the method practically useless.
The implication of GST is that it is possible to perfectly reconstruct a signal sampled at 1/n times the Nyquist rate with n independent sets of samples that describe the signal. For the de-interlacing problem n=2, and the required two sets are the current field and the motion compensated previous field. If the two do not coincide, i.e., the object does not have an odd vertical motion vector component, the independency constraint is fulfilled, and the problem can theoretically be solved. Practical problems are:
a) The velocity can have an odd vertical component.
b) A perfect reconstruction requires the use of pixels from many lines, for which the velocity needs not be constant.
c) For velocities near the vertical odds, noise may be enhanced.
Solution (3) is based on the assumption that it is possible at some time to have a perfectly de-interlaced picture in a memory. Once this is true, the picture is used to de-interlace the next input field. With motion compensation, this solution can be perfect as the de-interlaced picture in the memory allows the use of SRC-theory also in the vertical domain. If this new de-interlaced field is written in the memory, it can be used to de-interlace the next incoming field etc. Limitations of this method are:
(I) Propagation of errors due to motion vector inaccuracy and interpolation defects
(II) Even a perfectly de-interlaced picture can contain alias in the vertical frequency domain, assuming the common case of a camera without optical pre-filter.
In practice problem (I) is the more serious, particularly for nearly odd vertical velocities and/or noisy input signals.
We concluded that recursive de-interlacing and de-interlacing based on GST are the best methods presently known. However, even these best methods are imperfect. It is our target to present an improvement that can be applied in combination with both methods to suppress the remaining artifacts in the de-interlaced output signal. In fact, our proposal can be used to improve any de-interlacing algorithm.
3. Description of the Applied Algorithms
In Reference  a time-recursive de-interlacing algorithm is proposed in which the lines that need to be interpolated are found by motion compensating the previously found de-interlaced output frame: ##EQU1## where F(x, t) is the interlaced input signal, F out (x, n) the sequential output, n the field number, and x is the spatial position.
To prevent errors from propagating, in Reference  several additional measures are described to protect the interpolated lines. Particularly, the median filter is proposed to realize this protection:
Although further alternatives are suggested in Reference , we will use this algorithm as the basis for our comparison. ##EQU2##
As we expect the quality of Reference the resulting algorithm to depend heavily on the performance of the motion estimator, we applied the motion estimation method of . This high quality algorithm yields a quarter pixel accuracy, and a close to true-motion vector field which is considered very important for scan rate conversion. Rather than calculating all possible candidate vectors, this recursive search block-matcher takes spatial and/or temporal "prediction vectors" from a 3-D neighborhood, and a single updated prediction vector. This implicitly assumes spatial and/or temporal consistency. The updating process involves update vectors added to either of the spatial prediction vectors. We applied a candidate set CS(X, n), from which the block-matcher selects its result vector, defined by: ##EQU3## where the update vectors U a (X, n) and U b (X, n) are alternatingly (on block basis) available, and are taken from a limited fixed integer update set, in our case: ##EQU4## To realize sub-pixel accuracy, the update set of equation (4) is extended with fractional update values. We realized a quarter pixel resolution by adding the following fractional update vectors to the update set: ##EQU5## Because of the small number of candidate vectors, the method is very efficient and realizes, due to the inherent smoothness constraint, very coherent and close to true-motion vector fields, most suitable for scanning format conversion.
4. Recursive de-interlacing algorithm
The main imperfection of the recursive de-interlacing algorithm is remaining alias in the output signal. Although this imperfection is usually worse for alternative methods, further improvement seems attractive. Difficulty with this defect is that it is hardly visible in single images but mainly in moving sequences. This makes it difficult to illustrate, while also quantitative measures to show the improvement seem to lack.
A common method for evaluating the de-interlacing quality is comparing an original sequentially scanned image with a de-interlaced result using a, what we will call here, MSEs-criterion: ##EQU6##
This criterion is not exclusively sensitive for remaining alias, as it sums all differences without discriminating for different backgrounds, e.g., due to resolution losses, noise, vector errors, etc. An additional inconvenience of this criterion is that it cannot be applied to check the performance of the algorithm on original interlaced source signals.
In a perfectly de-interlaced picture (without residual alias), a characteristic is that the sequence is stationary along the motion trajectory, in picture parts for which the motion model is valid. Based upon this characteristic, an alternative was suggested in where we measured how well the current interlaced input field n was predicted by the motion compensated previously de-interlaced field: ##EQU7## This method has the advantage that it can be applied to judge the performance in absence of an original sequentially scanned sequence. However, the measure has limited value in case of critical velocities, as in that case the quality of the interpolated lines is not reflected in the figure.
In an attempt to improve on this aspect, it is possible to measure a "Motion Trajectory Inconsistency" (MTI(n)) for all output lines in field n, which we will define as: ##EQU8## A problem with this measure is that a good score on this criterion is a necessary but not sufficient constraint in the processing. It is possible, e.g. applying a strong temporal filtering, to force this MTI to very low values, while obviously the picture quality is degraded. However, a lower score on the MTI criterion coupled to a hardly varying MSE score is a strong indication for quality improvement. There is a clear analogy with the motion vector smoothness constraint (see Reference ), where motion estimation techniques have been improved by adding a smoothness term in the match criterion which yields a significant consistency improvement accepting a slight MSE degradation. Quite similarly, it is possible here to introduce a de-interlacing cost figure defmed as: ##EQU9## The parameter α allows tuning of the cost function to match the subjective impression.
After quantifying "remaining alias" applying equation (9), an improvement of the MTI figure could be realized by suppressing non-stationarities along the motion trajectory. As long as this does not seriously degrades the MSE-score, it brings an improved Cost-score and, with α tuned correctly, also an improved subjective performance.
As non-stationarities can reside on interpolated lines as well as on original lines, the implication would be that both have to be temporally filtered. That filtering of original lines, which is somewhat contra-intuitive, helps to suppress remaining alias can also be understood from the vertical frequency spectrum of the signal on original and interpolated lines respectively. In the original recursive de-interlacing algorithm, the lines existing in the input field are always directly transferred to the output and never modified. As the first repeat spectrum of the interpolated lines will almost always suffer from inaccuracies in the motion vector estimates and the protection features, this spectrum cannot fully compensate for the (anti-phase) repeat spectrum resulting from the original lines.
As a consequence of the above, the recursive de-interlacing method that we propose interpolates not only the new lines, but, in an attempt to maximize the motion trajectory consistency on both type of lines equally strong, also the lines existing in the interlaced signal: F out (x, n)=k(R).(F out (x-D(x, n), n-1)+(1-k(R)).(F i (x, n))(10)
where k(R) is a control parameter that reflects the reliability R of the motion vectors. F i (x, n) can be calculated according to equation (2) but also, with little disadvantage as we will show later, using a simpler intra-field interpolation: ##EQU10## In the literature, sometimes the match error, or the match error corrected for the local picture contrast is used. When applying the 3-D Recursive Search block-matcher described in Reference , another indication for motion vector reliability is available. This recursive estimator, due to the use of spatial and temporal predictions, implicitly assumes consistent motion vector fields. If the output vector field is not smooth than the implicit assumption may be false, and therefore the motion vectors unreliable.
For this smoothness, any sum of absolute (or squared) differences of the current vector with its spatial and temporal neighbors can be applied, but using the 3-D RS block-matcher, we obtained good results using the following definition for the vector smoothness S: ##EQU11## where p=(x, y, t) T is the spatio-temporal position, α is a constant selected experimentally, while the neighborhood N in which the neighboring vectors are found defined as: ##EQU12## In this definition X and Y denote the horizontal and vertical block dimensions as used in the motion estimator respectively.
5. Refinements of the Algorithm
The severest drawbacks that were found with the above-described algorithm were:
(1) Large homogeneously moving picture parts occasionally break up into several areas with slightly different velocities (earthquakes).
(2) In areas where large displacement discontinuities occurred, blocking artifacts were sometimes visible. These are due to the reliability indicator being available on block base only.
The first of these difficulties is directly related to the fundament of the proposed method and, therefore, most difficult to cure: by recursively filtering both the original and the interpolated lines, the output becomes more and more "isolated from the input" if the reliability of the motion vectors is considered to be good. In this section, therefore, we introduce a solution to prevent the output pictures from drifting too far from the input material.
The basis for the refinement is to detect directly how far the filtered information on an original line differs from the unfiltered information and to reduce the filtering in case the deviation becomes to large. As this adaptation of the filtering can easily be realized on a pixel base, it further provides a means to cope with the drawback mentioned under number (2). The same difference is used to reduce the filtering of the interpolated lines, albeit that much larger differences turned out to be tolerable.
In the refined algorithm (modification of equation (2) the output luminance is found as: ##EQU13## and using a limiter function "clip" defined as: ##EQU14## k 2 is calculated as: ##EQU15## Consequently, k 2 is a function of the vector smoothness S, defined in equation (4), and of the (pixel-) difference, Diff, in the motion compensated recursive loop measured on original lines of the interlaced grid only: ##EQU16## where W is a window containing the six pixels nearest to the currently interpolated pixel on the lines directly above and below the interpolated pixel. As Diff is related to the MSE i (n) of equation (7), it is possible by appropriately choosing C 1 , to tune the relative importance of MSE i (n) and MTI(n).
Although this tuning seems rather straightforward for the original lines, it is more complicated for the interpolated lines. For these lines, an MTI(n) figure can be calculated, but a significant MSE i (n) cannot be found, as the quality of the input lines to this temporal filter depends on the quality of the initial sequential scan conversion algorithm. To escape from this fundamental problem, we propose here to tune k 1 such that the contribution of original lines and interpolated lines to the MTI(n) figure is identical per pixel, disregarding the energy over the temporal filter for the interpolated lines. The assumption leads to: ##EQU17## while at the same time: F out (x, n)=k 1 F i (x, n)+(1-k 1 )F out (x-D, n-1)(19)
where F i (x, n) is the output of the initial de-interlacing algorithm, e.g., using equation (2) or (11). Combination of equations (18) and (19), results in a calculation of k 1 according to: ##EQU18## Combining this result with the lower part of equation (14) results in: ##EQU19## As an implication, the temporal recursive filtering on the interpolated lines depends on the quality of the initial de-interlacing method. A simple line averaging algorithm will cause stronger temporal filtering, of the interpolated lines, than e.g. a motion compensated median filter. Experimentally, we could show that the difference in resulting de-interlacing performance was small.
The assumption of equation (18) leads to an adaptation of temporal recursive filtering on the interpolated line applying differences measured on the upper neighboring original line. Rather than using the upper original line as a reference, the lower neighboring line can be used equally well. For symmetry considerations, the average effect on the two neighboring original lines seems advantageous. Elaborating this results in a symmetrical alternative for equation (20): ##EQU20## with: ##EQU21##
Rather than averaging the absolute differences, it is possible to take the absolute value of the average, the maximum of the two averages, or apply (2-D) spatial filters before and/or after the rectifier (abs). The choices resemble those commonly applied in motion detectors. It is furthermore possible to apply the above control of the temporal filter on the interpolated lines, while fixing the value of k 2 to no filtering on the original lines (k 2 =1). Generally, this will lead to somewhat lower MSE i (n) figures, but a significantly higher MTI(n) score.
In an alternative embodiment, k 2 is calculated as: ##EQU22## with: Diff(x, n)=abs(F out (x-D(x, n), n-1)-(F i (x, n)) (25)
Consequently, k 2 is a function of the prediction error, Diff, in the motion compensated recursive loop. As Diff is related to the MSE(n) of equation (7), it is possible by appropriately choosing C 2 , to tune the relative importance of MSE i (n) and MTI(n).
As the quality of the interpolated pixels, as resulting from the initial de-interlacing method, is obviously less than that of the original pixels, the filtering of these pixels should be stronger. As, furthermore, Diff(x, n), at the position of the interpolated lines, has little value to determine the quality of the motion compensated prediction, we propose to control k 1 using: ##EQU23## where C 1 is smaller than C 2 , and the control of the recursive filter for interpolated pixels is derived from the quality of the motion compensated prediction at the vertically neighboring existing pixels.
There is a risk in filtering alternate lines differently, as it potentially introduces visible line structures. Although the advantage of high quality de-interlacing will be apparent in areas with vertical detail, there is no advantage in regions that lack such high vertical frequency components. Therefore, in order to prevent the introduction of line structure in image parts that never profit from individual filtering, k 1 is made equal to k 2 if: ##EQU24##
To evaluate the proposals resulting from the previous section, we selected a set of 4 critical sequences. The sequences contain vertical detail, and motion with various sub-pixel values in many directions. Using the algorithm of Reference , in the version described in section 2 as a above reference, we calculated MSEs and MTIs for another two algorithms, illustrating the proposals of this paper. The first algorithm is the one illustrated in FIG. 1, in which the control of the recursive loop is according to equations (24,26). The second algorithm has k 2 fixed at 1, i.e., no recursive filtering of the original pixels, and is further identical. Compared to the reference algorithm, both proposed new algorithms yield a slightly improved MSE i figure, which is expected to be mainly due to the elimination of median defects in the high spatial frequencies. The MTI figures, however, have been improved dramatically, particularly for the first algorithm, i.e., the algorithm that performs recursive filtering even on the original lines. MSE i figures of both algorithm differ only little. The additional recursive filtering of the original pixels mainly improves the MTI figure (with little or no disadvantage for the MSE i figure).
FIG. 1 shows the resulting architecture of the proposed de-interlacing algorithm. In FIG. 1, an interlaced input signal is applied from an input I to an initial sequential scan converter 1 which supplies original lines at its lower output and interpolated lines at its upper output. The original lines are applied to a motion compensation stage 7 thru a mixer 3 and a field memory 5. Similarly, the interpolated lines are applied to the motion compensation stage 7 thru a mixer 9 and a field memory 11. Motion vectors D for the motion compensation stage 7 are determined by a motion estimator 13 on the basis of the original lines supplied by the initial sequential scan converter 1 (or on the basis of the lines supplied by the mixer 3), and shifted lines supplied by the motion compensation stage 7. Motion compensated shifted lines are supplied by the motion compensation stage 7 to the mixers 3 and 9. The mixer 3 mixes the original lines and the motion compensated shifted lines in the ratio k2: (1-k2). The mixer 9 mixes the interpolated lines from the initial sequential scan converter 1 and the motion compensated shifted lines in the ratio k1:(1-k1). Output signals from the mixers 3 and 9 are applied to a compress and multiplex stage 15 to generate a de-interlaced output signal, which is displayed on a display unit 16.
While this embodiment largely corresponds to that described in WO-A-95/27362 (Attorney's reference PHN 14,794), the present invention is mainly concerned with providing optimal values for k1 (and k2). To this end, FIG. 2 shows an embodiment of a device for calculating the mixer coefficients k1 and k2 for use in the embodiment of FIG. 1. The mixer coefficients calculating device of FIG. 2 contains a first calculation circuit 17 for calculating a vector smoothness S in response to the motion vectors D in accordance with equations 12, 13, and a second calculation circuit 19 for calculating the mixing factors k1 and k2 in dependence upon the four signals applied to the mixers 3 and 9 in accordance with equations 14 thru 23.
FIG. 3 shows an embodiment of a device for calculating the mixer coefficient k1 for use in the embodiment of FIG. 1. The mixer coefficient k2 has a fixed value of 1. The mixer coefficient k1 is calculated in accordance with equation 20 by a calculating device 20.
A generally applicable improvement to existing de-interlacing algorithms and a new evaluation measure for such algorithms have been proposed in this application. A motion-compensated temporal recursive filtering is used. A typical feature of the proposal is that this filtering is not limited to the interpolated pixels only, but is extended to the filtering of the pixels existing in the interlaced input signal. This somewhat contra-intuitive action followed from the assumption that in order to have the repeat spectra of original lines compensated by that of the interpolated ones, it is essential that the two have identical frequency response. As it cannot be prevented that of the interpolated pixels may be distorted by the limited accuracy of the applied motion vectors, a similar distortion can best be applied to that of the original pixels in order to maximally suppress alias. The application of the improvement to time-recursive de-interlacing was elaborated and the improved performance was verified. The verification has to be understood in a sense that the classical MSE i performance measure had not suffered (in fact, even showed some improvement), whereas the new proposed "consistency along the motion trajectory" (MTI) had greatly improved.
In a preferred embodiment, the invention provides a method of sequential scan conversion which uses a recursive temporal filtering of at least the interpolated lines, in which the filter is controlled by locally giving a resulting consistency along the motion trajectory a fixed relation (e.g. 1), to the values determined for adjacent lines.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. While absolute differences are described, in some embodiments, normal differences are used to preserve the sign of the difference. FIG. 1 shows a recursive embodiment, in which the outputs of the mixers 3, 9 are applied to the motion-compensation stage 7 thru the field memories 5, 11; of course, a non-recursive embodiment in which the inputs of the field memories 5, 11 are directly connected to the outputs of the initial sequential scan convertor 1 is also possible. In FIG. 1, the interpolated lines supplied by the initial sequential scan convertor 1 may be just white, black or grey lines; if an interpolation algorithm is used to obtain the interpolated lines, any algorithm will do. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer.
Accordingly, a preferred embodiment of the invention provides a method of generating a sequentially scanned video signal from an interlaced input signal, comprising the steps of: furnishing a first signal having first lines (F i (x-(0, 1) T , n)) corresponding to original lines of the interlaced input signal, and second lines (F i (x, n)) in addition to the first lines (F i (x-(0, 1) T , n)); and
providing a second signal having first motion-compensated lines (F out (x-(0, 1) T -D, n-1)) corresponding to the original lines, and second motion-compensated lines (F out (x-D, n-1)) corresponding to the second lines (F i (x, n));
combining the first signal and the motion-compensated signal to obtain an output sequentially scanned video signal having first output lines (F out (x-(0, 1) T , n)) corresponding to the original lines, and second output lines (F out (x, n)) between the first output lines (F out (x-(0, 1) T , n));
wherein the second output lines (F out (x, n)) are obtained in dependence upon (see equations 21 and 27):
a first difference between the first motion-compensated lines (F out (x-(0, 1) T -D, n-1)) and the first lines (F i (x-(0, 1) T , n)),
a second difference between the second motion-compensated lines (F out (x-D, n-1)) and the second lines (F i (x, n)), and
a relation (k 2 ) between the first lines (F i (x-(0, 1) T , n)) and the first output lines (F out (x-(0, 1) T , n)).
However, it is not necessary that the output video signal is a sequentially scanned video signal, as the invention can advantageously be used to derive an output interlaced signal having its output lines vertically positioned between the lines of the input interlaced signal. Such an interlaced-to-interlaced conversion is needed in 100 Hz conversion, where the lines one of the input interlaced fields need to be vertically shifted towards the positions of the lines of the other input interlaced field. The combining step is advantageous in a sequential scan conversion, but not necessary in other scan conversions.
Also, while the second signal is preferably obtained by means of a motion-compensated interpolation, satisfactory results can already be obtained when a less complex method is used to obtain a second signal which is delayed or advanced with respect to the first signal, like one which uses a median filter.
Finally, the dependence on the relation (k 2 ) between the first lines and the first output lines appeared to contribute to an improved result, while good results were already obtained when the output lines were dependent only on the first and second differences.
The invention can advantageously be applied in a video signal display apparatus like a television receiver or a personal computer.
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