PHILIPS 24CE7770 /10R STRAUSS CHASSIS 3A INTERNAL VIEW

I've read somewhere on the WEB that a guy wrote that the PHILIPS CHASSIS 3A is " very simple " !

Now few questions:

- That guy was smoking crack

- That guy don't have any clue

- That guy was drunk

- That guy is an Idiot

This is indeed a complex and sophisticated chassis.

It has many features and all fucntions are controlled by 2 PHILIPS Microcontrollers MAB8461.
type.

It introduces many technological improvements:

- CTI - Color transient Improvement

- Computerized teletext

- Digital Geometry Control TDA8432

- multi AV selections capability.

- 2 uController system.

- Picture Crisp Improvement even selectable via remote.


TDA8432 is an l2C bus-controlled deflection processor (analog picture geometry processor)

DESCRIPTION
The TDA8432 is an l2C bus-controlled
deflection processor (analog picture ge-
ometry processor) which contains the
control and drive functions of the deflec-
tion circuits in a computer-controlled TV
(CCTV) or monitor. This IC replaces all
picture geometry settings which are per-
formed manually during manufacturing.
The alignment of 10 picture geometry
parameters for the vertical and horizon-
tal deflection is accomplished by means
of a microcontroller via the l2C bus.
Furthermore, it eliminates the external
components needed for adjusting the
horizontal frequency and phase position,
vertical linearity, picture height, east-
west parabola, and picture width. The
east-west shaping circuit is also eliminat-
ed. Provisions have been incorporated
to make several sync processor
(TDA2579 and TDA2595) functions |20
bus-controllable.


FEATURES

0 I2C bus Interface for all functions
0 Input for vertlcal sync from sync
processor
o Vertical sawtooth generator with
frequency-Independent amplitude
0 Vertical output stage with
feedback Input for drlvlng a
vertlcal deflection ampllfler
0 East-west raster correction drive
output
0 EHT modulatlon lnput, providing
optlmum picture geometry
compensation for static and
dynamlc EHT load varlatlone
0 I2C bus-controlled alignment of
10 deflectlon parameters
0 Provlslons for controlling a sync
processing IC which does not
have an I C bus Interface,
lncludlng:
- Two dlgltal-to-analog converters
for alignment of the free-
runnlng horizontal frequency
and horizontal phase posltlon
- An I/O pln enabllng computer
alignment of the free-runnlng
horizontal frequency
- A speclal purpose 4-level
output for time constant
swltchlng of the horizontal
phase-locked loop
- A special purpose 3-level Input
for detection of the mute
function and the 50Hz/60Hz
state of the sync processor
o A switchable output (e.g., for
controlling a video source
selector)
APPLICATIONS
0 Video monitors
0 Color TV recelvers



I2C Bus Interface
The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external
pull-up resistor to VCC (open drain output stage).
The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains
"1", information changes on the data bus indicate the start or the end of data transfer between two
components.
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" a stop
condition. During a data transfer the information on the data bus will only change while the clock line
SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an I2C Bus system, the memory component can operate as a receiver and as a
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is
always transmitted in byte-organized form. Between the trailing edge of the eighth clock pulse and a ninth acknowledge clock pulse, the memory component sets the SDA line to low as a confirmation
of reception, if the chip select conditions have been met. During the output of data, the data output
of the memory is high in impedance during the ninth clock pulse (acknowledge master).
The signal timing required for the operation of the I2C Bus is summarized in figure 2.
Control Functions of the I2C Bus
The memory component is controlled by the controller (master) via the I2C Bus in two operating
modes: read-out cycle, and reprogramming cycle, including erase and write to a memory address.
In both operating modes, the controller, as transmitter, has to provide 3 bytes and an additional
acknowledge clock pulse to the bus after the start condition. During a memory read, at least nine
additional clock pulses are required to accept the data from the memory and the acknowledge
master, before the stop condition may follow. In the case of programming, the active programming
process is only started by the stop condition after data input (see figure 3).
The chip select word contains the 3 chip select bits CS0, CS1 and CS2, thus allowing 8 memory
chips to be connected in parallel. Chip select is achieved when the three control bits logically
correspond to the selected conditions at the select inputs.
Check for End of Programming or Abortion of Programming Process
If the chip is addressed during active reprogramming by entering CS/E, the programming process
is terminated. If, however, it is addressed by entering CS/A, the entry will be ignored. Only after
programming has been terminated will the chip respond to CS/A. This allows the user to check
whether the end of the programming process has been reached (see figure 3).
Memory Read
After the input of the first two control words CS/E and WA, the resetting of the start condition and the
input of a third control word CS/A, the memory is set ready to read. During acknowledge clock
nine, the memory information is transferred in parallel mode to the shift register. Subsequent to the
trailing edge of the acknowledge clock, the data output is low impedance and the first data bit can
be sampled, (see figure 4).
With every shift clock, an additional bit reaches the output. After reading a byte, the internal address
counter is automatically incremented when the master receiver switches the data line to “low” during
the ninth clock (acknowledge master). Any number of memory locations can thus be read one after
the other. At address 128, an overflow to address 0 is not initiated. With the stop condition, the data
output returns to high-impedance mode. The internal sequence control of the memory component
is reset from the read to the quiescent with the stop condition.
TDA2579 Horizontal/vertical synchronization circuit

GENERAL DESCRIPTION
The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;
a transmitter identification signal and also 50/60 Hz identification.
Features
· Horizontal phase detector, (sync to oscillator), sync separator and noise inverter
· Triple current source in the phase detector with automatic selection
· Second phase detector for storage compensation of the horizontal output
· Stabilized direct starting of the horizontal oscillator and output stage from mains supply
· Horizontal output pulse with constant duty cycle value of 29 ms
· Internal vertical sync separator, and two integration selection times
· Divider system with three different reset enable windows
· Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified
· Vertical comparator with a low DC feedback signal
· 50/60 Hz identification output combined with mute function
· Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration
· Automatic adaption of the burst-key pulsewidth.

FUNCTIONAL DESCRIPTION
Vertical part (pins 1,2,3,4)
The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an
internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period
equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with
3 different divider reset windows for maximum interference/disturbance protection.
The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the
separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse
is not present.
Large (search) window: divider ratio between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow window limits.
3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.
4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kW to earth or connecting a 3.6 V
diode stabistor between pin 18 and ground.
Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz).
The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved
vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the
divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the
divider system switches over to the large window mode.
Standard TV-norm
When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to
the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a
value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset
at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value
by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode.
The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.
No-TV-transmitter found: (pin 18 <>
In this condition, only noise is present, the divider is rest to count 628. In this way a stable picture display at normal height
is achieved.
Video tape recorders in feature mode
It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted
pictures that the no-TV-transmitter detection circuit can be activated as pin V18 drops below 1.2 V. This would imply a
rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in
the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628
when V18 is below 1.2 V is inhibited when a vertical sync pulse is detected.
The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync.
pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of
the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.



PHILIPS CHASSIS 3A Horizontal deflection waveform correction circuit

A deflection apparatus comprises a deflection amplifier coupled to a deflection waveform modulation circuit such as a diode modulator. An East-West modulation signal is generated by a digital to analog convertor in accordance with a reference potential coupled thereto. The modulation signal has a DC component for width control, and is coupled to an input of a comparator. The reference potential is also coupled to an input of the comparator to establish a reference bias therefor. The comparator has an output coupled to the deflection waveform modulation circuit to provide the East-West modulation.

1. A deflection apparatus comprising:
a deflection amplifier;
a deflection waveform modulation circuit coupled to said deflection amplifier;
a digital to analog converter for generating a modulation signal;
means for generating a reference signal that is coupled to said digital to analog converter thereby subjecting said modulation signal to signal variations in accordance with variations of said reference signal; and,
a comparator having two inputs, said digital to analog converter being coupled to one of the inputs, and said reference signal being coupled to one of the inputs, such that signals developed at said comparator inputs track one another in accordance with said variation of said reference signal, said comparator having an output coupled to said deflection waveform modulation circuit for waveform modulation.


2. The apparatus of claim 1, wherein said reference signal is coupled to said comparator via a potential divider.

3. The apparatus of claim 1, wherein said modulation signal comprises a vertical rate parabolic signal.

4. The apparatus of claim 1, wherein said modulation signal comprises a DC component for determining an amplitude of said deflection waveform modulation.

5. The apparatus of claim 3, wherein said modulation signal further comprises a DC component for determining an amplitude of said deflection waveform modulation.

6. The apparatus of claim 4, wherein said DC component varies in accordance with said reference signal.

7. The apparatus of claim 1, wherein said modulation signal is directly coupled to one of said comparator inputs and said comparator output is directly coupled to said deflection waveform modulation circuit such that a DC component of said modulation signal establishes an amplitude of said deflection waveform.

8. The apparatus of claim 1, wherein said digital to analog converter and said means for generating a reference signal are within an integrated circuit.

9. The apparatus of claim 1, wherein one of the inputs of said comparator is further coupled to a horizontal rate ramp signal, an instantaneous amplitude of said modulation signal and said ramp signal varying with respect to said reference signal to produce a pulse width modulated signal at said output, having a fixed horizontal rate and a pulse width responsive to said modulation signal.

10. The apparatus of claim 1, wherein said digital to analog converter is controlled responsive to a data word coupled via a data bus.

11. The apparatus of claim 1, wherein said digital to analog converter is controlled responsive to said data word coupled from a memory.

12. The apparatus of claim 11, wherein said digital to analog converter is controlled responsive to a data word coupled from a memory, said memory being coupled to a data bus.

13. The apparatus of claim 1, wherein said deflection waveform modulation circuit comprises a diode modulator.

14. A deflection apparatus comprising:
a deflection amplifier;
a deflection waveform modulation circuit coupled to said deflection amplifier;
a source of a deflection waveform correction signal, where said signal is controlled in level by a digital to analog converter responsive to a data word;
means for generating a reference potential that is coupled to said digital to analog converter for generating said deflection correction signal wherein variation of said reference potential is tracked by corresponding variation of said deflection waveform correction signal; and,
a comparator having two inputs, one of the inputs being coupled to said deflection correction signal and one of the inputs being coupled to said reference potential, said deflection correction signal and said reference potential tracking one with the other such that a comparator output responds to differences between said inputs, said comparator output being coupled to said deflection waveform modulation circuit for waveform modulation.


15. The apparatus of claim 14, wherein said source of a deflection waveform correction signal is an integrated circuit.

16. The apparatus of claim 15, wherein said integrated circuit is controllably coupled to a data bus.

17. The apparatus of claim 14, wherein said reference potential developing means is incorporated within said source.

18. The apparatus of claim 14, wherein said deflection waveform correction signal comprises a vertical rate signal of parabolic wave shape for pincushion correction and a DC component for horizontal deflection width control.

19. The apparatus of claim 14, wherein said reference potential is coupled to one of said comparator inputs via a potential divider.

20. The apparatus of claim 14, wherein said digital to analog converter is controlled responsive to a data word coupled from a memory.

Description:

BACKGROUND OF THE INVENTION
This invention relates to the field of cathode ray tube deflection amplitude control, such as East-West waveform correction of horizontal deflection signals generated by a bus controlled integrated circuit.
The development of single integrated circuits containing both analog and digital television signal processing has greatly reduced receiver parts count, improved reliability and reduced manufacturing cost. Such integrated circuits frequently employ sync separation circuitry to lock a reference oscillator from which horizontal and vertical rate deflection signals are developed. To facilitate control of the IC functions with a minimum of circuit board potentiometers and to minimize the IC pin count, the integrated circuit may be controlled via a data bus. An example of a data bus system is the Thomson logic protocol which comprises three control lines, data, clock and enable respectively. The IC usually contains memory registers which store digital values that correspond to setup, alignment or user determined values for specific parameters. The stored digital data is converted to an analog value by a digital to analog converter. This analog value is coupled out of the IC to control the specific parameter in external circuitry.
To reduce the IC pin count, certain waveforms and control signals may output on common IC pins. For example, a horizontal pincushion correction waveform, namely a vertical rate parabola, may be output together with a horizontal width determining DC voltage. Thus a single IC pin is used for two circuit control functions. The selection of horizontal pincushion, and horizontal width control parameters is advantageous since both parameters may be controlled by a common deflection circuit configuration, for example a pulse width modulator coupled to a pincushion diode modulator. Thus the vertical rate parabola may be superimposed on a horizontal width determining DC voltage. However, this composite control signal requires DC coupling to the point of circuit control. Furthermore, control requirements may exist for certain deflection yoke/tube combinations which require control signal amplitudes which tend to exceed the output voltage swing capability of the multifunction IC. Hence constraints exist within the IC which limit the maximum amplitude ratio of the two control signals. Additional constraints exist within the IC in terms of the range of digital control, i.e. number of control data bits, and the consequential size requirements for control value memory.
SUMMARY OF THE INVENTION
A deflection apparatus comprising a deflection amplifier and a deflection waveform modulation circuit coupled thereto. A digital to analog converter for generating a modulation signal coupled to a means for generating a reference signal thereby subjecting said modulation signal to signal variations in accordance with variations of said reference signal. A comparator having two inputs, said digital to analog converter being coupled to one of the inputs, and said reference signal being coupled to one of the inputs, such that signals developed at said comparator inputs track one another in accordance with said variation of said reference signal. The comparator having an output coupled to said deflection waveform modulation circuit for waveform modulation.

PHILIPS  24CE7770 /10R  CHASSIS  3A  Switched-mode self oscillating supply voltage circuit: CHASSIS 3A POWER SUPPLY (SOPS - Self Oscillating Power Supply)

A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or a load connected to the output voltage. The circuit comprises a first controllable switch connected in series with a transformer winding and a second controllable switch for turning-off the first switch. The conduction period of the first switch is controlled by means of a control voltage present on a control electrode of the second switch. The circuit can be switched-over to a stand-up state in which the energy supplied to the load is reduced to zero. A starting network is connected between the input voltage and the second switch so that the current therein flows through the second switch during the period of time this switch conducts and does not flow to the control electode of the first switch in the stand-by state.

1. A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage, comprising a transformer having a primary and a feedback winding, a first controllable switch connected in series with the primary winding, the series arrangement thus formed being coupled between terminals for the input voltage, a second controllable switch coupled via a turn-off capacitor to the control electrode of the first switch to turn it off, means coupling the feedback winding to said control electrode, a transformer winding being coupled via a rectifier to an output capacitor having terminals which supply the output voltage, an output voltage-dependent control voltage being present on a control electrode of the second switch for controlling the conduction period of the first switch, the circuit being switchable between an operating state and a stand-by state in which relative to the operating state the supply energy supplied to the load is considerably reduced, a starting network connected to a terminal for the input voltage, means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off, a connection which carries current during the conduction period for the second controllable switch being provided between the starting network and said second switch, and means providing a connection between the starting network and the control electrode of the first switch, which connection does not carry current in the stand-by state.

2. A supply voltage circuit as claimed in claim 1, further comprising a resistor included between the connection of the starting network to the second switch and a turn-off capacitor present in the connection to the control electrode of the first switch.

3. A supply voltage circuit as claimed in claim 2, characterized in that the second controllable switch comprises a thyristor having a main current path included in the control electrode connection of the first controllable switch, said thyristor having a first control gate electrode for adjusting the turn-off instant of the first switch and a second control electrode to which the starting network and the resistor are connected.

4. A supply voltage circuit as claimed in claim 1, characterized in that a resistor is included in the connection to the control electrode of the second controllable switch so that a current flows through said resistor in the stand-by state of a value sufficient to cut-off the first controllable switch.

Description:

The invention relates to a switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage. This circuit comprises a transformer having a primary and a feedback winding and a first controllable switch arranged in series with the primary winding. The series arrangement thus formed is coupled between the terminals of the input voltage. A second controllable switch which is coupled via a turnoff capacitor to the control electrode of the first switch to turn it off. The feedback winding is coupled to this control electrode and the primary winding is coupled via a rectifier to an output capacitor the terminals of which are the terminals for the output voltage. An output voltage-dependent control voltage is present on a control electrode of the second switch for controlling the conduction period of the first switch. The circuit is switchable between an operating state and a stand-by state in which relative to the operating state the energy supplied to the load is considerably reduced, and the circuit further comprises a starting network connected to a terminal for the input voltage.
Such a supply voltage circuit is disclosed in German Patent Application No. 2,651,196. With this prior art circuit supply energy can be applied in the operating state to the different portions of a television receiver. In the stand-by state the majority of the output voltages of the circuit are so low that the receiver is substantially in the switched-off condition. In the prior art circuit the starting network is formed by a resistor connected to the unstabilized input voltage and through which on turn-on of the circuit a current flows via the feedback winding to the control electrode of the first controllable switch, which is a switching transistor, and brings it to and maintains it in the conductive state, as a result of which the circuit can start.
In the stand-by state the transistor is non-conducting in a large part of the period of the generated oscillation so that little energy is stored in the transformer. However, the starting resistor is connected via a diode to the second controllable switch, which is a thyristor. As the sum of the voltages across these elements is higher than the base-emitter threshold voltage of the transistor, the diode and the thyristor cannot simultaneously carry current. This implies that current flows through the starting resistor to the base of the transistor via the feedback winding after a capacitor connected to the feedback winding has been charged.
The invention has for its object to provide an improved circuit of the same type in which in the stand-by state the supply energy applied to the load is reduced to zero. The prior art circuit cannot be improved in this respect without the use of mechanical switches, for example relays. According to the invention, the switched-mode self-oscillating supply voltage circuit does not comprise such relays and is characterized in that it further comprises means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off. A connection which carries current during the conduction period of the second controllable switch is provided between the starting network and said second switch while a connection present between the starting network and the control electrode of the first switch does not carry current in the stand-by state.
The invention is based on the recognition that the prior art supply voltage circuit cannot oscillate, so that the energy supplied by it is zero, if the control voltage obtains a value as referred to, while the starting network is connected in such a manner that in the stand-by state no current can flow through it to the control electrode of the first controllable switch.
It should be noted that in the said German Patent Application the starting network is in the form of a resistor which is connected to an unstabilized input d.c. voltage. It is, however, known, for example, from German Patent Specification No. 2,417,628 to employ for this purpose a rectifier network connected to an a.c. voltage from which the said input d.c. voltage is derived by rectification.


The invention will now be further described by way of example with reference to the accompanying drawing, which shows a basic circuit diagram of a switched-mode self-oscillating supply voltage circuit.


The self-oscillating supply circuit shown in the FIGURE comprises a npn-switching transistor Tr1 having its collector connected to the primary winding L1 of a transformer T, while the emitter is connected to ground via a small resistor R1, for example 1.5 Ohm. Resistor R1 is decoupled for the high frequencies by means of a 150 nF capacitor C1. One end of winding L1 is connected to a conductor which carries an unstabilized input d.c. voltage V _B of, for example, 300 V. Voltage V _B has a negative rail connected to ground and is derived from the electric power supply by rectification. One end of a feedback winding L2 is connected to the base of transistor Tr1 via the parallel arrangement of a small inductance L3 and a damping resistor R2. A terminal of a 47 μF capacitor C2 is connected to the junction of the elements L2, L3 and R2. The series arrangement of a diode D1 and a 2.2 Ohm-limiting resistor R3 is arranged between the other terminal of capacitor C2 and the other end of winding L2 and the series arrangement of a resistor R4 of 12 Ohm and a diode D2 is arranged between the same end of winding L2 and the emitter of transistor Tr1. A 150 nF capacitor C3 is connected in parallel with diode D2. The anode of diode D1 is connected to that end of winding L2 which is not connected to capacitor C2, while the anode of diode D2 is connected to the emitter of transistor Tr1. In the FIGURE the winding sense of windings L1 and L2 is indicated by means of dots.
The junction of capacitor C2 and resistor R3 is connected to a 100 Ohm resistor R5 and to the emitter of a pnp-transistor Tr2. The base of transistor Tr2 is connected to the other terminal of resistor R5 and to the collector of an npn-transistor Tr3, whose emitter is connected to ground. The base of Tr3 is connected to the collector of transistor Tr2. Transistors Tr2 and Tr3 form an artificial thyristor, i.e. a controllable diode whose anode is the emitter of transistor Tr2 while the cathode is the emitter of transistor Tr3. The base of transistor Tr2 is the anode gate and the base of transistor Tr3 is the cathode gate of the thyristor formed. Between the last-mentioned base and the emitter of transistor Tr1 there is arranged the series network of a 2.2 kOhm resistor R6 with the parallel arrangement of a 2.2 kOhm resistor R7 and a 100 μF capacitor C4. The series arrangement of a diode D11 and a 220 Ohm limiting resistor R19 is arranged between the junction of components R6, R7 and C4 and the junction of components C2, L2, R2 and L3. The cathode of diode D11 is connected to capacitor C2.
Because of the feedback the described circuit oscillates independently as soon as the steady state is achieved. It will be described hereinafter how this state is obtained. During the time transistor Tr1 conducts the current flowing through the resistor R1 increases linearly. The resistor R4 then partly determines the base current of transistor Tr1. Capacitor C4 and resistor R7 form a voltage source the voltage of which is subtracted from the voltage drop across resistor R1. As soon as the voltage on the base of transistor Tr3 is equal to approximately 0.7 V this transistor becomes conductive, as a result of which the thyristor formed by transistors Tr2 and Tr3 becomes rapidly conductive and remains so. Across capacitor C2 there is a negative voltage by means of which transistor Tr1 is turned off. The inverse base current thereof flows through thyristor Tr2, Tr3. This causes charge to be withdrawn from capacitor C2, while the charge carriers stored in transistor Tr1 are removed with the aid of inductance L3. As soon as the collector current of transistor Tr1 has been turned off, the voltage across winding L2 reverses its polarity, which current recharges the capacitor. Now the voltage at the junction of components C2, R3 and R5 is negative, causing thyristor Tr2, Tr3 to extinguish.
Secondary windings L4, L5 and L6 are provided on the core of transformer T with the indicated winding senses. When transistor Tr1 is turned off, a current which recharges a smoothing capacitor C5, C6 or C7 via a rectifier D3, D4 or D5 flows through each of these windings. The voltages across these capacitors are the output voltages of the supply circuit for loads connectable thereto. These loads, which are not shown in the FIGURE, are, for example, portions of a television receiver.
In parallel with winding L1 there is the series network of a 2.2 nF tuning capacitor C8 and a 100 Ohm limiting resistor R8. The anode of a diode D6 is connected to the junction of components R8 and C8, while the cathode is connected to the other terminal of resistor R8. Winding L1 and capacitor C8 form a resonant circuit across which an oscillation is produced after windings L4, L5 and L6 have become currentless. At a later instant the current through circuit L1, C8 reverses its direction. As a result thereof a current is generated in winding L2 which flows via diode D2 and resistor R4 to the base of transistor Tr1 and makes this transistor conductive and maintains it in this state. The dissipation in resistor R8 is reduced by means of diode D6. A clamping network formed by the parallel arrangement of a 22 kOhm resistor R9 and a 120 nF capacitor C9 is arranged in series with a diode D7. This whole assembly is in parallel with winding L1 and cuts-off parasitic oscillations which would be produced during the period of time in which transistor Tr1 is non-conductive. The output voltages of the supply circuit are kept substantially constant in spite of variations of voltage V _B and/or the loads, thanks to a control of the turning-on instant of thyrisistor Tr2, Tr3. For this purpose the emitter of a light-sensitive transistor Tr4 is connected to the base of transistor Tr3. The collector of transistor Tr4 is connected via a resistor R10 to the conductor which carries the voltage V _B and to a Zener diode Z1 which has a positive voltage of approximately 7.5 V, while the base is unconnected. The other end of diode Z1 is connected to ground. A light-emitting diode D8, whose cathode is connected to the collector of an npn-transistor Tr5, is optically coupled to transistor Tr4. By means of a potentiometer R11 the base of transistor Tr5 can be adjusted to a d.c. voltage which is derived from the voltage V ₀ of approximately 130 V across capacitor C6. The anode of diode D8 is connected to a d.c. voltage V ₁ of approximately 13 V. A resistor R12 is also connected to voltage V ₁ , the other end of the resistor being connected to the emitter of transistor Tr5, to the cathode of a Zener diode Z2 which has a voltage of approximately 7.5 V and to a smoothing capacitor C10. The other ends of diode Z2 and capacitor C10 are connected to ground. Voltage V1 can be generated by means of a transformer connected to the electric AC supply and a rectifier, which are not shown for the sake of simplicity, more specifically for a remote control to which constantly supply energy is always applied, even when the majority of the components of the receiver in what is referred to as the stand-by state are not supplied with supply energy.
A portion of voltage V ₀ is compared with the voltage of diode Z2 by means of transistor Tr5. The measured difference determines the collector current of transistor Tr5 and consequently the emitter current of transistor Tr4. This emitter current produces across resistor R6 a voltage drop whose polarity is the opposite of the polarity of the voltage source formed by resistor R7 and capacitor C4. Under the influence of this voltage drop the turn-on instant of thyristor Tr2, Tr3 is controlled as a function of voltage V ₀ . If, for example, voltage V ₀ tends to decrease owing to an increasing load thereon and/or in response to a decrease in voltage V _B , then the collector current of transistor Tr5 decreases and consequently also the said voltage drop. Thyristor Tr2, Tr3 is turned on at a later instant than would otherwise be the case, causing transistor Tr1 to be cut-off at a later instant. The final value of the collector current of this transistor is consequently higher. Consequently, the ratio of the time interval in which transistor Tr1 is conductive to the entire period, commonly referred to as the duty cycle, increases, while the frequency decreases.
The circuit is protected from overvoltage. This is ensured by a thyristor which is formed by a pnp-transistor Tr6 and an npn-transistor Tr7. The anode of a diode D9 is connected to the junction of components R3 and C2 and the cathode to the base of transistor Tr6 and to the collector of transistor Tr7. The base of transistor Tr7, which base is connected to the collector of transistor Tr6, is connected via a zener diode Z3 to a voltage which, by means of a potentiometer R13 is adjusted to a value derived from the voltage across capacitor C7. The emitter of transistor Tr6 also is connected to the voltage of capacitor C7, more specifically via a resistor R14 and a diode D10. If this voltage increases to above a predetermined value then thyristor Tr6, Tr7 becomes conductive. Since the emitter of transistor Tr7 is connected to ground, the voltage at its collector becomes very low, as a result of which diode D9 becomes conductive, which keeps transistor Tr1 in the non-conducting state. This situation is maintained as long as thyristor Tr6, Tr7 continues to conduct. This conduction time is predominantly determined by the values of capacitor C7, resistor R14 and a resistor R15 connected between the base and the emitter of transistor Tr6. A thyristor is advantageously used here to render it possible to switch off a large current even with a low level signal and to obtain the required hysteresis.
The circuit comprises a 1 MOhm starting resistor R16, one end of which is connected to the base of transistor Tr2 and the other end to the conductor which carries the voltage V _B . Upon turn-on of the circuit current flows through resistors R16 and R5 and through capacitor C2, which has as yet no charge, to the base of transistor Tr1. The voltage drop thus produced across resistor R5 keeps transistor Tr2, and consequently also transistor Tr3, in the non-conductive state, while transistor Tr1 is made conductive and is maintained so by this current. Current also flows through winding L2. In this manner the circuit can start as energy is built up in transformer T.
The supply circuit can be brought into the stand-by state by making an npn-transistor Tr8, which is non-conductive in the operating state, conductive. The emitter of transistor Tr8 is connected to ground while the collector is connected to the collector of transistor Tr5 via a 1.8 kOhm resistor R17. A resistor R18 has one end connected to the base of transistor Tr8 and the other end, either in the operating state to ground, or in the stand-by state to a positive voltage of, for example, 5 V. Transistor Tr8 conducts in response to this voltage. An additional, large current flows through diode D8 and consequently also through transistor Tr4, resulting in thyristor Tr2, Tr3 being made conductive and transistor Tr1 being made non-conductive and maintained so. So to all appearances a large control current is obtained causing the duty cycle to be reduced to zero. A condition for a correct operation is that the emitter current of transistor Tr4 be sufficiently large in all circumstances, which implies that the voltage drop produced across resistor R6 by this current is always higher than the sum of the voltage across voltage source R7, C4, of the base-emitter threshold voltage of transistor Tr3 in the conductive state thereof, and of the voltage at the emitter of transistor Tr1. So the said voltage drop must be higher than the sum of the first two voltages, which corresponds to the worst dimensioning case in which the stand-by state is initiated while transistor Tr1 is in the non-conductive state.
If thyristor Tr2, Tr3 conducts, either in the operating state or in the stand-by state, current flows through resistor R16 via the collector emitter path of transistor Tr3 to ground. This current is too small to have any appreciable influence on the behaviour of the circuit. When thyristor Tr2, Tr3 does not conduct, the voltage on the left hand terminal of capacitor C2 is equal to approximately 1 V, while the voltage across the capacitor is approximately -4 V. So transistor Tr1 remains in the non-conductive state and a premature turn-on thereof cannot occur. If in the operating state transistor Tr1 conducts while thyristor Tr2, Tr3 is cut-off, then the current flows through resistor R16 in the same manner as it flows during the start to the base of transistor Tr1, but has relatively little influence as the base current caused by the energy stored in winding L2 is many times larger. If both transistor Tr1 and thyristor Tr2, Tr3 are non-conductive, then the current through resistor R16 flows through components R5, C2, L2, R4, C3 and R1. In this stand-by state capacitor C2 has indeed substantially no negative charge any longer but, in spite thereof, transistor Tr1 cannot become conductive since no current flows to its base. It will furthermore be noted that the circuit is protected in the event that thyristor Tr2, Tr3 has an interruption. Namely, in such a case the circuit cannot start.
In the foregoing a circuit is described which may be considered to be a switched-mode supply voltage circuit of the parallel ("flyback") type. It will be obvious that the invention may alternatively be used in supply voltage circuits of a different type, for example converters of the type commonly referred to as up-converters. It will also be obvious that transistor Tr1 may be replaced by an equivalent switch, for example a gate-turn-off switch.

PHILIPS  24CE7770 /10R STRAUSS CHASSIS  3A Switched-mode power supply having a standby state: PHILIPS SOPS SUPPLY ST-BY FEATURED.

switched-mode power supply circuit with having an operating state and a stand-by state in which the value of a first output voltage is considerably lower than in the operating state, whereas the value of a second output voltage is substantially the same. With the aid of a duration-determining circuit (Tr7, Tr8, R17, C12) which is controlled by a switch (Tr6) operative during the stand-by state, a low-frequency burst mode is maintained during this state in which the switch of the supply circuit conducts a number of consecutive times and subsequently becomes non-conductive during a given period. As a result the dissipation in the circuit is reduced.

 1. A self-oscillating power supply circuit having an operating state and a stand-by state comprising: a pair of terminals for connection to a source of DC voltage, a transformer having a primary winding and at least first and second secondary windings, a first controllable switch connected in series arrangement with the primary winding of the transformer, means coupling said series arrangement to said pair of terminals, said first and second secondary windings supplying first and second DC output voltages, respectively, in the operating state of the power supply circuit, a second controllable switch for controlling the power supply circuit into the stand-by state wherein the first secondary winding supplies a lower value of the first DC output voltage than in the operating state, a third controllable switch coupled to the second secondary winding and controlled by the second switch so that in the stand-by state the second secondary winding maintains the second output voltage at approximately the same value as in the operating state, a comparison stage for comparing an output voltage with a reference voltage and for generating a control signal for controlling the duration of periodically occurring drive pulses applied to the first switch, and a duration-determining circuit controlled by the second switch in the stand-by state so as to maintain a burst oscillation mode in which the first switch conducts a number of consecutive times and subsequently is non-conductive for a given time period and with an oscillation frequency much lower than the repetition frequency of said drive pulses.

2. A power supply circuit as claimed in claim 1 wherein the first switch comprises a transistor having a control electrode and the transformer further comprises a feedback winding, said power supply circuit further comprising, a turn-on path and a turn-off path coupled to said control electrode, said turn-on path comprising a first series circuit including a capacitor, said feedback winding and a diode, and said turn-off path comprises a second series circuit including said capacitor, a second transistor and an inductor.

3. A power supply circuit as claimed in claim 1 wherein said duration-determining circuit comprises a monostable multivibrator having an RC time constant network.

4. A power supply circuit as claimed in claim 1 wherein the transformer includes a further winding coupled to the second secondary winding via a diode that also rectifies the voltage generated in the second secondary winding thereby to develop said second DC output voltage, means coupling said third switch to said further winding so that operation of the third switch in the stand-by state provides a path for current to flow through the further winding, the turns ratio of the second secondary winding and the further winding being chosen so that said diode conducts during the operating state and is cut-off in the stand-by state of the power supply circuit.

5. A power supply circuit as claimed in claim 1 further comprising, a light emitting diode (LED) controlled by said duration-determining circuit, and a light-sensitive semiconductor element optically controlled by said LED and electrically coupled to a control electrode of the first switch so that the conduction periods of the first switch are determined by the LED in a sense so as to maintain the output voltages of the power supply circuit constant in spite of variations of the DC voltage at said pair of terminals and/or of loads coupled to the secondary windings.

6. A power supply circuit as claimed in claim 1 further comprising a capacitor coupled in parallel with said primary winding to form a parallel resonant circuit.

Description:

BACKGROUND OF THE INVENTION
This invention relates to a switched-mode power supply circuit having an operating state and a standby state and comprising a controllable first switch arranged in series with the primary winding of a transformer. The series arrangement thus formed is coupled to the terminals of a d.c. input voltage. The transformer has a first secondary winding for providing a first d.c. output voltage in the operating state and a second secondary winding for providing a second d.c. output voltage. The circuit also comprises a second switch for bringing the supply circuit into the stand-by state in which the value of the first output voltage is considerably lower than in the operating state, and a third switch controllable by means of the second switch and coupled to the second secondary winding for maintaining the second output voltage in the stand-by state at substantially the same value as in the operating state. The circuit further comprises a comparison stage for comparing an output voltage with a reference voltage and for generating a control signal for controlling the duration of periodically occurring drive pulses applied to the first switch.
A power supply circuit of this type is known from German Patent Application No. 3,223,756. In this known circuit, which is intended for use in a television receiver, both the first output voltage and other output voltages, which are derived from secondary windings of the transformer, have a lower value in the stand-by state than in the operating state so that the power consumption is smaller, while the second output voltage, to which a remote control is connected, has substantially the same value. In the stand-by state the first switch continues to operate normally, though every time with a shorter conduction period than in the operating state. This continuous operation at a high frequency, i.e. 25 to 30 kHz involves, however, quite a considerable power dissipation.

SUMMARY OF THE INVENTION
It is an object of the invention to provide a power supply circuit of the type described above having a lower dissipation relative to that of the known circuit. To this end the power supply circuit according to the invention is characterized in that a duration-determining element is coupled to the second secondary winding and to the comparison stage for maintaining an oscillation mode in the stand-by state. The first switch is conductive a number of consecutive times and subsequently becomes non-conductive during a given period under the influence of the control signal. The frequency of said oscillation is many times lower than the repetition frequency of the drive pulses applied to the first switch.
In accordance with this mode of oscillation the first switch conducts every time for only a short period during which energy is built up in the transformer, and subsequently the switch is rendered non-conducting. Since this is a low-frequency process, of the order of, for example, 100 to 200 Hz, the losses, predominantly the losses in the transformer and in the switch, are fairly low.
The circuit is advantageously characterized in that the second switch is coupled to the duration-determining element for controlling said element. The duration-determining element then comprises a time constant network. Thus, the second switch controls both the third switch and the duration-determining element.
The circuit according to the invention is preferably characterized in that the comparison stage is controllable by means of the second switch for comparing the second output voltage with a reference voltage during the stand-by state and for generating a control signal during a period determined by the time-constant network. This control signal is suitable for rendering the first switch non-conducting after the first output voltage has reached a given value. This measure ensures that the control circuit remains operative under all circumstances.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in greater detail by way of example with reference to the accompanying drawing in which:

FIG. 1 is a basic circuit diagram of a power supply circuit according to the invention, and
FIG. 2 shows waveforms occurring therein.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The self-oscillating power supply circuit of FIG. 1 comprises an npn power switching transistor Tr1 whose collector is connected to the primary winding L1 of a transformer T, while the emitter is connected to ground. The other end of winding L1 is connected to the positive rail of an unstabilized power supply source V_B whose negative rail is also connected to ground and which is, for example, a mains rectifier. The turn-on path of transistor Tr1, which is connected between the base of the transistor and ground, comprises a capacitor C1, a feedback winding L2 of transformer T, a diode D1 and a resistor R1. The base current flowing during the conduction period of transistor Tr1 produces a negative voltage across capacitor C1. The turn-off path of transistor Tr1, which is also connected to the base thereof, comprises capacitor C1, the emitter-collector path of a pnp transistor Tr2 having a base-emitter resistor R2, and an inductance L3. Upon turn-off a reverse base current of transistor Tr1 flows through elements C1, Tr2 and L3 so that the charge carriers stored in this transistor during the conduction period are removed. A negative voltage for capacitor C1 is generated with the aid of a further winding L4 of transformer T and a diode D2 in case the forward base current of transistor Tr1 flows for too short a time, under given circumstances, to build up a sufficiently constant voltage across capacitor C1. FIG. 1 shows the winding sense of the windings of transformer T by means of dots.
One end of a winding L5 of transformer T is connected to a diode D3, the other end of which is connected to the series network of a resistor R3 and a capacitor C2. Winding L5 has such a winding sense and diode D3 has such a conductivity direction that a charge current for capacitor C2 flows through resistor R3 during the conduction period of transistor Tr1. The bottom end of capacitor C2 is connected to the junction of capacitor C1, winding L2 and the collector of transistor Tr2. With respect to the d.c. voltage level present at this junction, a sawtooth voltage is produced across capacitor C2. This voltage is passed on to the base of an npn transistor Tr4 via an RC parallel network R4, C3. The emitter of transistor Tr4 is connected to the said junction, while the collector is connected to the base of transistor Tr2. At a given instant the voltage at the base of transistor Tr4 reaches a value at which the transistor is rendered conducting. As a result transistor Tr2 is also rendered conducting. The voltage at the emitter of this transistor assumes substantially the same value as the negative voltage of approximately -5 V which is present across capacitor C1, which initiates the turn-off of transistor Tr1. During the period of time when transistor Tr1 is non-conductive, capacitor C2 is discharged via a resistor R5, a diode D4 and winding L4, while a reverse current flows through transistor Tr2 which current also flows through resistor R1 and through a capacitor C4 which is connected in parallel with diode D1.
A starting resistor R6 having a high value is arranged between the positive rail of source V_B and the base of transisor Tr2. When the circuit is turned on, a current flows through resistors R6 and R2 which also flows through capacitor C4 and winding L2 so that energy is built up in transformer T. Due to this current the voltage at the base of transistor Tr1 increases until a value is reached at which the transistor becomes conducting. Also during normal operation a current flows through resistor R6, but its value is too low to have a noticeable influence on the behaviour of the circuit.
Secondary windings are provided on the core of transformer T. FIG. 1 shows a number of these windings, for example, L6 and L7. When transistor Tr1 is turned off, a current for recharging smoothing capacitors C5 and C6 flows via rectifiers, for example, D5 and D6, respectively, through each secondary winding. The other ends of capacitors C5 and C6 are connected to ground. The voltages across these capacitors are the output voltages of the supply circuit for loads connectable thereto. These loads, which are not shown in FIG. 1, are, for example, parts of a television receiver.
A network comprising a tuning capacitor C7 and a damping resistor R7, as well as a clamping network with a diode D7 is arranged in parallel with winding L1. Winding L1 and capacitor C7, as well as parasitic capacitances, constitute a resonant circuit in which an oscillation is produced in the intervals when transistor Tr1 and rectifiers D5 and D6 carry no current. Parasitic oscillations which might be produced during the period of time when transistor Tr1 is non-conducting are reduced by means of the said clamping network.
The output voltages of the supply circuit are kept substantially constant in spite of variations of the voltage V_B and/or of the loads by controlling the conduction periods of transistor Tr1. For this purpose the circuit includes a light-emitting diode D8 which is optically coupled to a light-sensitive npn-transistor Tr5 having an emitter resistor R8 which is connected in the base lead of transistor Tr4, as is the network R4, C3. A collector resistor R9 is connected to the source V_B and the base is unconnected. The collector of transistor Tr5 is also connected via an RC parallel network R10, C8 to the junction of windings L2 and L4 and capacitor C1 and is further connected via a diode D9 to the junction of winding L2 and diode D1. A positive voltage is thus present at the said collector. If the current through diode D8 varies in a manner to be described hereinafter, the emitter current of transistor Tr5 also varies. An increase of this current, for example, involves an increase in the voltage at the base of transistor Tr4 so that transistor Tr1 is turned off at an earlier instant than would otherwise be the case. The final value of transistor Tr1 is thus lower, resulting in the output voltages of the circuit also being lower. This control is also dependent on variations of the voltage V_B by means of a network comprising a Zener-diode D10 which is connected between the junction of resistors R4 and R8 and the junction of resistor R3 and diode D3.
The foregoing is well known to those skilled in the art and does not require any further explanation. Further details are therefore not discussed. The same applies to safety precautions against overvoltages and overcurrents which are formed in known manner. For a better understanding of the operation of the circuit, FIG. 2 shows some idealized waveforms: FIG. 2a shows the variation as a function of time of the voltage V across winding L1, i.e. the same variation but for a d.c. level, more specifically that of source V_B, as that of the voltage across the collector of transistor Tr1, and FIG. 2b shows the variation of the current i flowing through winding L1.
Transistor Tr1 is turned off at an instant t_o. Before this instant the current i increases linearly, while the voltage v has the value -V_B. After instant t_o the voltage v increases in accordance with a sine function of time, whereas current i varies in accordance with a cosine function. At an instant t₁ voltage v reaches the value of zero and the current i has a maximum value. Voltage v continues to increase until the value is reached at an instant t₂ when the rectifiers on the secondary side start conducting. If the voltage across capacitor C5 is equal to V_o and if the tranformation ratio of windings L1 and L6 is n:1, voltage v remains equal to nV_o after the instant t₂, whereas the current i decreases linearly, more specifically until the value of zero is reached at an instant t₃. After the instant t₃ the rectifiers do not carry any current, and the voltage v decreases in accordance with a sine function by at the same resonance frequency as between the instants t_o and t₂, but at a lower peak value, being nV_o, while the current i becomes negative. Current i flows to capacitor C7 and varies in accordance with a cosine function. Without any further measures a current would thus be produced in winding L2 which would flow through diode D1 to the base of transistor Tr1. FIGS. 1 and 2a show that transistor Tr1 would thereby be rendered conducting at an instant after instant t₃ when the sum of the voltage across winding L2 and the voltage across capacitors C1 and C4 will be lower than the base-emitter threshold voltage of the transistor. This instant occurs shortly after instant t₃ before the voltage v becomes zero, that is to say, upon turnon, the voltage at the collector of transistor Tr1 would be slightly lower than the value V_B +nV_o.
It appears from the foregoing that without any further measures the voltage at the collector of transistor Tr1 is fairly high upon turn-on which causes a considerable switching dissipation in transistor Tr1 and in resistor R7. To reduce the turn-on losses, the circuit of FIG. 1 includes an npn transistor Tr3 whose emitter is connected to the junction of capacitor C1 and winding L2 and whose collector is connected to the base of transistor Tr2 via a diode D11 having the same conductivity direction as the collector-emitter path of transistor Tr3. One end of winding L8 of transformer T is connected to the emitter of transistor Tr3 and the other end is connected to an integrating network consisting of a resistor R11 and a capacitor C9, said capacitor being arranged between resistor R11 and the said emitter. The junction of capacitor C9 and resistor R11 is connected via a limiting resistor R12 to the base of transistor Tr3. The winding sense of winding L8 is such that the voltage at the junction of resistor R11 has the same polarity as the voltage shown in FIG. 2a, that is to say, the voltage under consideration is negative before the instant t₁ and positive after this instant. Under these circumstances the voltage v' across capacitor C9 which is proportional to the integral of the voltage at the last-mentioned junction has the same time variation as the current i in FIG. 2b but a polarity opposed thereto. In fact, current i is proportional to the integral of voltage v.
FIG. 2c shows the variation of the voltage v'. Since both the voltage across winding L8 and the current through capacitor C9 have a mean value of zero over one oscillation period, the mean value of the voltage v' is also zero. This means that voltage v' reverses its polarity and becomes positive at an instant t₆ which is located earlier than instant t₃. The time constant of the RC network R11, C9 is chosen so that the voltage v' will exceed the value of the base-emitter threshold voltage of transistor Tr3 after instant t₃. This shows that this transistor conducts after instant t₃ and maintains transistor Tr1 in the non-conducting state in the same manner as transistor Tr4 does at the instant t_o, more specifically because transistor Tr2 conducts. Since the base of transistor Tr1 carries a negative voltage via the conducting transistor Tr2, while the voltage at the base of transistor Tr3 is positive, a current would flow through the base-collector diode of transistor Tr3, which would cause a distortion of the waveforms. This is prevented by the diode D11.
At an instant t₄ which occurs one fourth of the resonance period of winding L1 and capacitor C7 later than instant t₃, voltage v becomes zero while the current i reaches a minimum value. At an instant t₅ voltage v reaches a minimum value, while the current i again becomes zero and subsequently becomes positive. Instants t₃ and t₅ are symmetrical relative to instant t₄ so that the minimum value of the voltage v is substantially equal to -nV_o, while the minimum value of the voltage at the collector of transistor Tr1 is substantially equal to V_B -nV_o. Due to the symmetry, voltage v' decreases to a lower value than the threshold voltage of transistor Tr3 after the instant t₅ so that this transistor is rendered non-conducting. The voltage at the base of transistor Tr2 becomes positive so that this transistor also becomes non-conductive resulting in transistor Tr1 being rendered conducting. The voltage at its collector then becomes substantially zero and consequently voltage v becomes equal to -V_B. This state is maintained while the current i increases linearly until transistor Tr1 is again rendered non-conducting under the influence of the control, more specifically at an instant t₇ which is located one oscillation period later than instant t_o, whereafter the variation described is repeated.
It is evident from the foregoing that due to the operation of transistor Tr3 the turn-on instant of transistor Tr1 is delayed until the instant t₅ when the voltage at the collector of transistor Tr1 has a minimum value. This involves a considerable saving in energy and also extends the life of the transistor. It will be obvious that the delay should be fairly accurate because the voltage v before and after the instant t₅ is higher than the minimum value at this instant. In this respect an improvement is obtained by series arranging two diodes D12 and D13 having the same conductivity directions in parallel with capacitor C9, and with the anode of diode D12 connected to the junction of elements R11, R12 and C9. As a result the maximum value of voltage v' at the instant t₄ is approximately equal to twice a diode threshold voltage, i.e. approximately 1.4 V. The maximum value of the base-emitter voltage of transistor Tr3 is therefore equal to one threshold voltage, more specifically during a given time interval starting before the instant t₄ and ending after this instant. The circuit may be dimensioned in such a manner that this interval substantially coincides with the period between the instants t₃ and t₅. In one embodiment of the delay circuit the resistors R11 and R12 had values of 8.2 and 2.2 kOhm, respectively, while the capacitance of capacitor C9 was approximately 4.7 nF, and the frequency of the oscillation, i.e. the inverse of the period between the instants t_o and t₇, could vary between 25 and 60 kHz.
The foregoing description applies to the case where the supply circuit is dimensioned in such a manner that the voltage V_B is lower than nV_o, in which case the minimum value of the voltage at the collector of transistor Tr1 just before turning on the transistor is positive. In the opposite case the said voltage becomes zero at an instant which is located earlier than instant t₅ whereafter a reverse current flows through the base-collector diode of transistor Tr1, while the said voltage is negative. At the instant t₅ this current is switched off in the same manner as described above. If necessary, a diode may be connected in parallel with the collector-emitter path of transistor Tr1, which diode has its conductivity direction opposed to this path and through which the reverse current flows. To ensure that no reverse current flows through the transistor, a diode may be arranged in series with the transistor and with the same conductivity direction as this transistor, while the anti-parallel diode is arranged between the junction of the series diode with winding L1 and ground. It will be noted that the dissipation caused by the reverse current is smaller in this case, because the voltage at the collector is maintained at a low value by the conducting anti-parallel diode, than the dissipation caused by the forward current in FIG. 2 which is many times larger, namely proportional to 1/2Cv² and to the oscillation frequency. In this case C is the capacitance which is effectively in parallel with transistor Tr1. In addition the said reverse current returns to the source V_B.
The series arrangement of a diode D14 and a capacitor C10 is connected to a secondary winding L9 of transformer T with the anode of diode D14 connected to the end of winding L9 which is not connected to ground. One end of a further secondary winding L10 of transformer T, which has more turns than winding L9, is connected to the junction of diode D14 and capacitor C10 and the other end is connected to the cathode of a thyristor Th. The anode of thyristor Th is connected to ground. A series arrangement constituted by the emitter-collector path of a pnp transistor Tr6, a diode D15 and a voltage divider consisting of two resistors R13 and R14 is connected in parallel with capacitor C10. The emitter of transistor Tr6 is connected to the input of a series control circuit S whose output voltage is smoothed by means of a capacitor C11. The series arrangement of the emitter-collector path of a pnp transistor Tr7, a resistor R15 and the above-mentioned light-emitting diode D8 is connected in parallel with capacitor C11. The base of an npn transistor Tr8 is connected to the junction of resistors R13 and R14, while the collector is connected to the base of transistor Tr7 and to a resistor R16 and the emitter is connected to the cathode of a Zener-diode D16, the other end of which is connected to ground. The other end of resistor R16 is connected to the output of circuit S. A diode D17 is incorporated between the collector of transistor Tr6 and the cathode-gate of thyristor Th. This diode has the same conductivity direction as transistor Tr6. An RC-series network R17, C12 is incorporated between the base of transistor Tr8 and the collector of transistor Tr7. Finally, a resistor R18 connects the base of transistor Tr6 to a terminal A.
In the normal operating state transistor Tr6 does not conduct because terminal A is either not connected or is connected to a positive voltage. Diode D17 neither does not conduct and consequently thyristor Th does not conduct either. As a result winding L10 remains currentless and capacitor C10 carries a d.c. voltage of, for example, approximately 7 V which is derived from the voltage across winding L9 by means of diode D14. A voltage of, for example, 5 V for a microprocessor in the control section of the receiver and or remote control is present across capacitor C11. Transistors Tr7 and Tr8 also remain non-conducting.
For controlling the output voltages of the supply circuit, this circuit is provided with a further secondary winding L11 of the transformer T, a rectifier D18 and a smoothing capacitor C13. By means of a voltage divider arranged in parallel with capacitor C5 and consistng of resistors R19, R20, R21 and R22, the base of an npn transistor Tr9, which is connected to the junction of resistors R20 and R21, is adjusted to a d.c. voltage which is proportional to the output voltage V_o across capacitor C5. The emitter of transistor Tr9 is connected to a Zener diode D16. The voltage at the base is compared with the voltage of diode D16 by means of transistor Tr9. The difference measured determines the collector current of a pnp transistor Tr10 whose emitter is connected to capacitor C13 and whose collector is connected via a resistor R23 to the anode of diode D8 and consequently determines the current through diode D8 and therefore the emitter current of transistor Tr5. If, for example, the output voltage increases as a result of a decreasing load and/or as a result of an increase of voltage V_B, the collector current of transistor Tr9 and consequently the control current through diode D8 also increase. In the manner already explained this increase causes a reduction in the conductivity period of transistor Tr1, which counteracts the increase of the output voltage. An RC series network R24, C14 is incorporated between the base and the collector of transistor Tr10 for reducing the loop gain at a high frequency, thereby improving the stability of the control. A diode D19 is arranged between capacitor C6 and the junction of resistors R19 and R20 and provides a safety feature in case the diode D5, with which the highest output voltage V_o is generated, becomes defective. In this case, when diode D5 is interrupted, the voltage across capacitor C5 becomes zero. The control then attempts to increase this voltage, but this is prevented because diode D19 starts conducting so that now the voltage across capacitor C6 is controlled.
By connecting terminal A to ground the supply circuit of FIG. 1 is brought into the stand-by state during which most parts of the television receiver receive very little supply energy. Transistor Tr6 then starts conducting so that current flows through diode D17 to the cathode gate of thyristor Th which also starts conducting, while diode D14 is rendered non-conducting as will be further explained. A current flows through diode D15 to the base of transistor Tr8 which is rendered conducting so that transistor Tr7 also becomes conducting. The increase of the voltage at the collector of transistor Tr7 is passed on to the base of transistor Tr8 by the network R17, C12. Thus, transistors Tr7 and Tr8 constitute a monostable multivibrator which remains in its state reached during a period which is determined, inter alia, by the time constant of network R17, C12, even after the voltage V₁ across capacitor C10 has become low. A part of the voltage V₁ is compared with the voltage of Zener diode D16 by means of transistor Tr8. The difference measured determines the collector current of transistor Tr7, which current flows through diode D8. The part of the circuit including winding L10 thus forms part of a control loop for maintaining the voltage V₁ substantially constant, which control loop is put into operation by switching over to the stand-by state by means of terminal A.
The number of turns of winding L10 has been chosen to be such that during the stand-by state the output voltages of the supply circuit, that is to say, the direct voltages derived from the other secondary windings L6, L7 and L11 are reduced to low values with little power being dissipated in the loads. This may be explained with reference to the following figures. When, for example, winding L6 has 44 turns, L7 has 7 turns, L9 has 2 turns and L10 has 15 turns, respectively, and when the voltage V_o across capacitor C5 is approximately 140 V in the operating state, the voltage across capacitor C6 is ##EQU1## the voltage across capacitor C10 is ##EQU2## and a direct voltage derived from winding L10 by rectification is ##EQU3## When voltage V₁ is maintained at 8 V in the stand-by state, a direct voltage derived from winding L9 by rectification would be ##EQU4## which shows that diode D14 is not conducting, and the voltage across capacitor C6 is ##EQU5## while the voltage across capacitor C5 is ##EQU6## The latter two values are so low that a synchronizing circuit connected to capacitor C6 and a line deflection circuit connected to capacitor C5 cannot operate properly, which produces a very low consumption. The output voltages are proportionally reduced and the different loads need not be turned off, while the voltage across capacitor C11 has substantially the same value as in the operating state.
Under these circumstances the conduction period of transistor Tr1, i.e. the interval between the instants t₅ and t₇ in FIG. 2 becomes increasingly shorter due to the operation of the control after a switch-over to the stand-by state has been effected. This conduction period has, however, a minimum value which is determined by the storage period of the charge carriers in transistor Tr1. During this period which cannot come, for example, below approximately 3 to 5 μs, the collector current of this transistor increases to a peak value which depends on the said period and also on the voltage V_B and which, similar to the storage period, is subject to variations caused by tolerances. Due to this current more energy is stored in transformer T than is extracted from it so that the output voltages tend to increase again after having been low. This is, however, prevented by the control: diode D8 produces such a large control current that transistor Tr1 is turned off and remains in the non-conducting state because transistor Tr4 continuously remains conducting due to the large emitter current of transistor Tr5. In the stand-by state transistor Tr5 has a collector voltage via resistor R9. The output voltages and also the control current now decrease again because capacitors C5, C6, C10 and C13 are discharged, more specifically until the voltage V₁ reaches a value at which the power supply circuit starts again. Transistor Tr1 becomes conducting in the manner already described, resulting in the capacitors on the secondary side of transformer T being charged again. An intermittent current flows through thyristor Th so that the voltage across capacitor C10 reaches a level at which transistor Tr8 is rendered conducting again, which restores the control loop. The process described is subsequently repeated.
It is evident from the foregoing that in the stand-by state the supply circuit of FIG. 1 is in a state in which a burst mode is generated, i.e. with an oscillation which is interrupted periodically, in which state very short current pulses flow through transistor Tr1 while the secondary voltages increase, whereafter the transistor is non-conducting while the secondary voltages decrease slowly. The advantage of such a burst mode is that the efficiency is then favourable. In fact, if the supply circuit continuously operated with low or turned-off loads, the frequency of the oscillation would become high because the interval between the instants t₂ and t₃ in FIG. 2 would become very short. This would involve great losses in the transformer as well as great switching losses in transistor Tr1 and resistor R7. The burst mode is, however, not produced with certainty, particularly not if the value of voltage V_B can vary within a large voltage range. Other reasons therefor may be: short storage time of the power transistor and high power consumption in the stand-by state. To ensure that the supply circuit continues to oscillate in the described manner in the stand-by state, that is to say, that it does not come into a continuous state, the monostable multivibrator make up of transistors Tr7 and Tr8 is provided, with which a hysteresis is obtained. Due to the hysteresis transistor Tr7 is maintained conducting for some time during which time a large current continues to flow through diode D8 so that transistor Tr1 remains non-conducting while the output voltages decrease. This "dead period" of the burst mode is determined by the time constant of the network R17, C12, the starting resistor R6 and the capacitor C4 through which the starting current flows. For this oscillation a low frequency of approximately 100 Hz has been found useful in practice. A substantially constant voltage is obtained with the aid of a circuit S for the voltage across capacitor C11.
The anode of a Zener diode D20 is connected to the cathode of diode D15 and the cathode of diode D20 is connected to capacitor C10. When at an instant when thyristor Th would become inoperative the connection of terminal A to ground is interrupted for switching to the operating state of the receiver, thyristor Th can still remain conducting for some time due to its inertia while the control loop is open. Under these circumstances voltage V₁ would tend to increase, more specifically until the voltage across winding L10 reaches the above-mentioned value of 47.7 V. Thanks to diode D20 the voltage across capacitor C10 does not exceed a given value. The supply circuit thus remains in the burst mode for a short time until thyristor Th is extinguished, whereafter the voltage across capacitor C10 is again determined by diode D14.
A further refinement is to connect the connection of resistor R6, which is not connected to transistor Tr2, to the junction of two resistors which are not shown for the sake of simplicity, instead of to source V_B as is shown in FIG. 1. The other connection of each of these resistors is connected to a terminal of the mains voltage, the said junction being connected to ground via a capacitor having a low capacitance. If without this measure the supply is switched off by operating a mains switch while the receiver is still in the stand-by state, the stand-by state is still maintained for several seconds due to the burst mode before a signal lamp is extinguished. This is prevented because the voltage across the above-mentioned capacitor drops off rapidly so that the starting current goes rapidly to zero. The supply circuit therefore does not leave the "dead period" of the burst mode.
It may be noted that the output voltages can also be decreased in the stand-by state by decreasing the Zener voltage with which a comparison is made. Compared to the above-described measure a drawback of this measure by which diode D16 is switched over, while the windings L9 and L10 and the components connected thereto are omitted, is that the collector current of transistor Tr9 is high during the decrease of the output voltages, which causes a large control current through diode D8 and brings transistor Tr1 into the non-conducting state. The result thereof is that the supply circuit does not apply a voltage for quite some time to the remote control and to the operating microprocessor, which is undesirable.
It will be evident that variants which are within the scope of the invention will be apparent for the circuit described. This applies to, for example, transistor Tr1 which may be replaced by an equivalent power switch, for example, a gate turn-off switch. This also applies to a plurality of circuit-technical details, for example, the circuits for turning off transistor Tr1 or for turning on this transistor. Variants can also be considered for the switch-over from and to the stand-by state, for example, for the switch-over facility consisting of transistor Tr6 and thyristor Th which may have a different form, and for winding L9 which may be a winding of a line output transformer or which may be omitted altogether, while the anode of diode D14 is connected to, for example, capacitor C13, and variants can also be considered for the implementation of the mulivibrator made up of transistors Tr7 and Tr8 and of the time-constant network. This also applies to the number of common elements in the first control loop for maintaining the voltage V_o and the other output voltages constant in the operating state, and in the second control loop for maintaining the voltage V₁ for the remote control constant in the stand-by state, while the other output voltages are greatly reduced. Similarly, the differential amplifier may be common in both control loops.
It will be evident that the manner in which the stand-by state is maintained, both in the circuit of FIG. 1 and in variants of this circuit, can also be used for other supply circuits: it is important that a circuit is concerned which is designed such that a large control current results in the power switch being switched off. Such a circuit has been described, for example, in U.S. Pat. No. 4,486,822 or in the U.S. Pat. No. 4,631,654. The latter circuit is not self-oscillating.

SAB3035 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)

GENERAL DESCRIPTION
The SAB3035 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver

FUNCTIONAL DESCRIPTION
The SAB3035 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).

The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50 l