ITT NOKIA IDEAL COLOR 4210 OS CHASSIS CORE 90° MN PAL RGB /IFB-620 16" INTERNAL VIEW

 ITT NOKIA IDEAL COLOR 4210 OS  CHASSIS  CORE 90° MN PAL RGB /IFB-620 16

Detailed parts:
Line + eht output
Supply:line synchronized master slave with TEA2164 (thomson)
Synch processing + supply control master side with TDA 8372 (PHILIPS TDA8372)
Frame output amplifier with TDA 3654 (PHILIPS):
BU508a Line output transistor.

- Control system with SAA
- Memory MEA2061


TDA4427 VIDEO IF CIRCUIT

Technology: Bipolar
Features:
o Very high input sensitivity
0 Very low intermodulation
products
0 Minimum differential error
o Constant input impedance
independent of AGC
o Fixed video output, voltage
with small tolerance range
o Negative video signal hardly
affected by supply voltage
variations
o Very few external components
TDA 4427 A: For ceramic sound traps
Extreme fast AGC action - gating
largely independent of pulse shape
and amplitude
Positive as well as neg. video signal
available from low-impedance outputs
Positive or negative going gating pulse
Large AFC output current swing
(push-pull output)
Switchable AFC
Connecting and basic circuitry compa-
tible to the TELEFUNKEN electronic
video IF type programme - permits
building block system for video IF
module. 

SDA3202-2  Phase Locked Loop Device - VCO tuner combo PLL synthesizer, I2C Bus.

TDA5330T VHF, UHF and Hyperband mixer/oscillator for TV and VCR 3-band tuners

GENERAL DESCRIPTION
The TDA5330T is a monolithic integrated circuit that performs the band A, band B and band C mixer/oscillator functions
in TV and VCR tuners. This device gives the designer the capability to design an economical and physically small 3-band
tuner which will be capable of meeting the most stringent requirements e.g. FTZ or FCC. The tuner development time
can be drastically reduced by using this device.
Features
· Balanced mixer with a common emitter input for band A
· Amplitude-controlled oscillator for band A
· Balanced mixer with common base input for band B and C
· Balanced oscillator for band B and C
· Local oscillator buffer output for external prescaler
· SAW filter preamplifier with an output impedance of 100 W
· Bandgap voltage stabilizer for oscillator stability
· Electronic bandswitch

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ITT NOKIA IDEAL COLOR 4210 OS CHASSIS CORE 90° MN PAL RGB /IFB-620 16  TEA2164 /2165 SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT


.POSITIVE AND NEGATIVE OUTPUT CURRENT
UP TO 1.2AAND – 1.7A .A TWO LEVEL COLLECTOR CURRENT LIMITATION
.COMPLETE TURN OFF AFTER LONG DURATION
OVERLOADS .UNDER AND OVER VOLTAGELOCK-OUT .SOFT START BY PROGRESSIVE CURRENT
LIMITATION .DOUBLE PULSE SUPPRESSION .BURST MODE OPERATION UNDER STANDBY
CONDITIONS
DESCRIPTION
In amaster slave architecture, the TEA2164control
IC achieves the slave function. Primarily designed
for TV receivers and monitors applications, this
circuit provides an easy synchronizationand smart
solution for low power stand by operation.
Located at the primary side the TEA2164 Control
IC ensures :
- the power supply start-up
- the power supply control under stand-by conditions
- the process of the regulation signals sent by the
master circuit located at the secondary side
- directbasedrive of the bipolarswitching transistor
- the protection of the transistor and the power
supply under abnormal conditions.

II. GENERAL DESCRIPTION
In a master slave architecture, the TEA2164 Control
IC, located at the primary side of an off line
power supply achievesthe slave function ;whereas
the master circuit is located at the secondary side.
The link between both circuits is realized by a small
pulse transformer

In the operation of the master-slave architecture,
four majors cases must be considered :
- normal operating
- stand-bymode
- power supply start-up
- abnormal conditions : off load, short circuit, ...
II.1. Normal Operating (master slave mode)
In this configuration, the master circuit generatesa
pulse widthmodulatedsignal issued from themonitoring
of the output voltage which needs the best
accuracy (in TV applications : the horizontal deflection
stagesupplyvoltage).Themaster circuit power
supply can be supplied by another output.
The PWM signal are sent towards the primary side
through small differentiating transformer. For the
TEA2164 positive pulses are transistor switchingon
commands ; and negative pulses are transistor
switching-offcommands (Figure 4). In this configuration,
only by synchronizing the master oscillator,
the switching transistor may be synchronized with
an external signal.
II.2. Stand-by Mode
In this configuration the master circuit no longer
sends PWM signals, the structure is not synchronized
; and the TEA2164 operates in burst mode.
The average power consumption at the secondary
side may be very low 1W 3 P 3 6W (as it is
consumed in TV set during stand by).
By action on the maximum duty cycle control, a
primary loop maintains a semi-regulation of the
output voltages.Voltage on feed-back is applied on
Pin 9.
Burst period is externally programmedby capacitor
C1.
II.3. Power Supply Start-up
After the mains have been switched-on, the VCC
storage capacitor of the TEA2164 is charged
through a high value resistor connected to the
rectified high voltage.When Vcc reaches VCC start
threshold (9V typ), the TEA2164 starts operatingin
burst mode. Since available output power is low in
burst mode the output power consumption must
remain low before complete setting-up of output
voltage. In TV application it can be achieved by
maintaining the TV in stand-by mode during startup.

Overvoltage Protection
When VCC exceeds VCC max, an internal flip-flop
stops output conduction signals. The circuit will
start again after the capacitor C1 discharge ; it
means : after loss of synchronization or after Vcc
stop crossing (Figure 7).
In flyback converters, this function protects the
power supply against output voltage runaway.
ITT NOKIA IDEAL COLOR 4210 OS CHASSIS CORE 90° MN PAL RGB /IFB-620 16    Synchronized switch-mode power supply:

In a switch mode power supply, a first switching transistor is coupled to a primary winding of an isolation transformer. A second switching transistor periodically applies a low impedance across a second winding of the transformer that is coupled to an oscillator for synchronizing the oscillator to the horizontal frequency. A third winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a DC control voltage in the capacitor that varies in accordance with a supply voltage B+. The control voltage is applied via the transformer to a pulse width modulator that is responsive to the oscillator output signal for producing a pulse-width modulated control signal. The control signal is applied to a mains coupled chopper transistor for generating and regulating the supply voltage B+ in accordance with the pulse width modulation of the control signal.

Description:

The invention relates to switch-mode power supplies.

Some television receivers have signal terminals for receiving, for example, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR or a teletext decoder.

To simplify the coupling of signals between the external devices and the television receiver, the common conductors of the receiver and of the external devices are connected together so that all are at the same potential. The signal lines of each external device are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as of the television receiver, may be held "floating", or conductively isolated, relative to the corresponding AC mains supply source that energizes the device. When the common conductor is held floating, a user touching a terminal that is at the potential of the common conductor will not suffer an electrical shock.

Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials of the terminals of the AC mains supply source that provide power to the television receiver. Such isolation is typically achieved by a transformer. The isolated common conductor is sometimes referred to as a "cold" ground conductor.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled, for example, directly, and without using transformer coupling, to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced that is, for example, referenced to a common conductor, referred to as "hot" ground, and that is conductively isolated from the cold ground conductor. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of an isolating flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce a DC output supply voltage such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver. The primary winding of the flyback transformer is, for example, conductively coupled to the hot ground conductor. The secondary winding of the flyback transformer and voltage B+ may be conductively isolated from the hot ground conductor by the hot-cold barrier formed by the transformer.

It may be desirable to synchronize the operation of the chopper transistor to horizontal scanning frequency for preventing the occurrence of an objectionable visual pattern in an image displayed in a display of the television receiver.

It may be further desirable to couple a horizontal synchronizing signal that is referenced to the cold ground to the pulse-width modulator that is referenced to the hot ground such that isolation is maintained.

A synchronized switch mode power supply, embodying an aspect of the invention, includes a transfromer having first and second windings. A first switching arrangement is coupled to the first winding for generating a first switching current in the first winding to periodically energize the second winding. A source of a synchronizing input signal at a frequency that is related to a deflection frequency is provided. A second switching arrangement responsive to the input signal and coupled to the second winding periodically applies a low impedance across the energized second winding that by transformer action produces a substantial increase in the first switching current. A periodic first control signal is generated. The increase in the first switching current is sensed to synchronize the first control signal to the input signal. An output supply voltage is generated from an input supply voltage in accordance with the first control signal.


ITT NOKIA IDEAL COLOR 4210 OS CHASSIS CORE 90° MN PAL RGB /IFB-620 16   Switch-mode power supply with burst mode standby operation:

In a switch mode power supply, a first switching transistor is coupled to a primary winding of a transformer for generating pulses of a switching current. A secondary winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a control signal in the capacitor. The control signal is applied to a mains coupled chopper second transistor for generating and regulating supply voltages in accordance with pulse width modulation of the control signal. During standby operation, the first and second transistors operate in a burst mode that is repetitive at a frequency of the AC mains supply voltage such as 50 Hz. In the burst mode operation, during intervals in which pulses of the switching current occur, the pulse width and peak amplitude of the switching current pulses progressively increase in accordance with the waveform of the mains supply voltage to provide a soft start operation in the standby mode of operation within each burst group.

Description:

The invention relates to switch-mode power supplies.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of a flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce DC output supply voltages such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver and a voltage that energizes a remote control unit.

During normal operation, the DC output supply voltages are regulated by the pulse width modulator in a negative feedback manner. During standby operation, the SMPS is required to generate the DC output supply voltage that energizes the remote control unit. However, most other stages of the television receiver are inoperative and do not draw supply currents. Consequently, the average value of the duty cycle of the chopper transistor may have to be substantially lower during standby than during normal operation.

Because of, for example, storage time limitation in the chopper transistor, it may not be possible to reduce the length of the conduction interval in a given cycle below a minimum level. Thus, in order to maintain the average value of the duty cycle low, it may be desirable to operate the chopper transistor in an intermittent or burst mode, during standby. During standby, a long dead time interval occurs between consecutively occurring burst mode operation intervals. Only during the burst mode operation interval switching operation occurs in the chopper transistor. The result is that each of the conduction intervals is of a sufficient length.

In accordance with an aspect of the invention, burst mode operation intervals are initiated and occur at a rate that is determined by a repetitive signal at the frequency of the AC mains supply voltage. For example, when the mains supply voltage is at 50 Hz, each burst mode operation interval, when switching cycles occur, may last 5 milliseconds and the dead time interval when no switching cycles occur, may last during the remainder portion or 15 milliseconds. Such arrangement that is triggered by a signal at the frequency of the mains supply voltage simplifies the design of the SMPS.

The burst mode operation intervals that occur in standby operation are synchronized to the 50 Hz signal. During each such interval, pulses of current are produced in transformers and inductances of the SMPS. The pulses of current occur in clusters that are repetitive at 50 Hz. The pulses of current occur at a frequency that is equal to the switching frequency of the chopper transistor within each burst mode operation interval. Such qurrent pulses might produce an objectionable sound during power-off or standby operation. The objectionable sound might be produced due to possible parasitic mechanical vibrations as a result of the pulse currents in, for example, the inductances and transformers of the SMPS.

In accordance with another aspect of the invention, the change in the AC mains supply voltage during each period causes the length of the conduction interval in consecutively occurring switching cycle during the burst mode operation interval to increase progressively. Such operation that occurs during each burst mode operation interval may be referred to as soft start operation. The soft start operation causes, for example, gradual charging of capacitors in the SMPS. Consequently, the parasitic mechanical vibrations are substantially reduced. Also, the frequency of the switching cycles within each burst mode operation interval is maintained above the audible range for further reducing the level of such audible noise during standby operation.

A switch mode power supply, embodying an aspect of the invention, for generating an output supply voltage during both a standby-mode of operation and during a run-mode of operation includes a source of AC mains input supply voltage. A control signal at a given frequency is generated. A switching arrangement energized by the input supply voltage and responsive to the first control signal produces a switching current during both the standby-mode of operation and the run-mode operation. The output supply voltage is generated from the switching current. An arrangement coupled to the switching arrangement and responsive to a standby-mode/run-mode control signal and to a signal at a frequency that is determined by a frequency of the AC mains input supply voltage controls the switching arrangement in a burst mode manner during the standby-mode of operation. During a burst interval, a plurality of switching cycles are performed and during an alternating dead time interval no switching cycles are performed. The two intervals alternate at a frequency that is determined by the frequency of the AC mains input supply voltage.

ITT NOKIA IDEAL COLOR 4210 OS CHASSIS CORE 90° MN PAL RGB /IFB-620 16  PHILIPS PAL decoder TDA3561A

GENERAL DESCRIPTION:


The TDA3561A is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals.

Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages.
The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:

· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded.
The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt transitions from colour to white signals.

· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.

· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.

· Non-synchronized external RGB signals do not disturb the black level of the internal signals.

· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.

· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.

· High current capability of the RGB outputs and the chrominance output.



TDA3653B Vertical deflection and guard circuit (90°)


GENERAL DESCRIPTION
The TDA3653B/C is a vertical deflection output circuit for drive of various deflection systems with currents up to
1.5 A peak-to-peak.
Features
· Driver
· Output stage
· Thermal protection and output stage protection
· Flyback generator
· Voltage stabilizer
· Guard circuit


FUNCTIONAL DESCRIPTION
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
Flyback generator
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
activated.
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.

This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
Guard circuit
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive
current of the output stage being affected by supply voltage variations.
PACKAGE OUTLINES
TDA3653B: 9-lead SIL; plastic (SOT110B); SOT110-1; 1996 November 25.
TDA3653C: 9-lead SIL; plastic power (SOT131); SOT131-2 November 25.
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply (note 1)
Supply voltage range
pin 9 VP = V9-4 10 - 40 V
pin 6 V6-4 - - 60 V
Output (pin 5)
Peak output voltage during flyback V5-4M - - 60 V
Output current I5(p-p) - 1.2 1.5 A
Operating junction temperature range Tj -25 - +150 °C
Thermal resistance junction to mounting base
(SOT110B) Rth j-mb - 10 - K/W
(SOT131) Rth j-mb - 3.5 - K/W.

  TEA2164/TEA2165 EXTENDED OVERLOAD PROTECTION CIRCUIT FOR A SWITCH MODE POWER SUPPLY HAVING CYCLE DETECTOR, MEMORY AND FLIP-FLOP INHIBITION:

 

 A protection device for switch mode power supplies includes a main switch controlled by the output signals of a flip-flop. The flip-flop input receives regulation control signals. A first protection circuit supplies priority signals with respect to the regulation signals on the reset input of the flip-flop. The protection device also includes a cycle detector of the first protection circuit, a memory for accumulating at each cycle a value proportional to the duration between a signal of the detector and the set signal associated with the regulation cycle of the following cycle, and inhibiting of the flip-flop when the memory has accumulated a signal higher than a predetermined threshold.

 

 

Inventors:Maige, Philippe (Syssinet Pariset, FR) Thomson-csf (Paris, FR) 

 

 

 1. A device for protection against long duration overloading in switch mode power supplies comprising a main switch controlled by output signals from a first flip-flop, the set and reset inputs of which receive regulation control signals, a first protection circuit supplying on the reset input priority signals with respect to the regulation signals when the current in the main switch exceeds a predetermined threshold, further comprising a second protection circuit itself comprising:

means for detecting cycles for which the first protection circuit is active and interrupts the on state of the main switch prior to the arrival of the order for the off state of the regulation signal;

memorization means accumulating at each cycle a value proportional to the duration between a signal from the detection means and the set signal associated with the regulation signal of the following cycle; and

inhibition means for inhibiting the set input of the flip-flop when the memorization means has accumulated a signal higher than a predetermined threshold;

wherein the means for detecting includes a second flip-flop, a third flip-flop and an AND gate, the second flip-flop receiving at its reset input the starting output of the regulation signal, the set input of the second flip-flop receiving the output of the AND gate and the output of the second flip-flop controlling the memorization means; the third flip-flop having its set input connected to the reset input of the second flip-flop, the reset input of the third flip-flop connected to the reset regulation signal and the output of the third flip-flop connected to a first input of the AND gate; the second input of the AND gate being connected to the output of the first protection circuit.


2. A device for protection according to claim 1, wherein the memorization means comprise a capacitor permanently discharged by a discharging means and temporarily charged by a charging means only when the detection means supplies a signal.

3. A device for protection according to claim 2, wherein the charge and discharge means are current supplies and the charge current supply is connected to the capacitor through a controlled switch actuated by the output of the second flip-flop of the detection means.

4. A device for protection according to claim 1, wherein the inhibition means comprise a comparator comparing the signal accumulated by the memorization means with a reference value, the output signal of this comparator inhibiting the set input of the first flip-flop when the memorized signal becomes higher than a reference value.

5. A device for protection according to claim 4, wherein the output of said comparator is connected to the set input of a fourth flip-flop of which the output is connected to the set input of the first flip-flop through an AND gate of which the other input receives the sginal for triggering the regulation signal.

6. A device for protection according to claim 5, wherein the AND gate connected to the validation input of the first flip-flop receives other inhibition signals issuing from other switch mode power circuits, such as automatic starting control circuits.

Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention concerns stabilized power supplies known as "switch mode power supplies".

A switch mode supply functions in the following manner: a primary transformer winding receives a current that is, for example, issuing from a rectifying bridge receiving power from the alternating power mains. The current in the transformer is chopped by a switch (for example a power transistor) placed in series with the primary winding.

A control circuit of the transistor establishes periodic square pulses to turn on the transistor. During the square pulse period current passage is authorized; outside of this square pulse period current passage is prohibited.

On one (or several) secondary winding(s) of the transformer, an alternating voltage is thus received. This voltage is rectified and filtered in order to produce a direct voltage that is the output direct voltage of the switch mode supply.

In order to stabilize the value of this direct voltage, the duty cycle of the switch is modified, i.e. the ratio between the conduction duration and the blocking duration in a chopped period.

FIG. 1 represents by way of example a switch mode power structure manufactured by the applicant in which two integrated circuits are used. One of the circuits, CI1, acts to control the base of a power switching transistor Tp for applying thereto periodic control signals for putting under conduction and blocking control. This base control circuit CI1 is placed on the side of the primary winding EP of the transformer TA for reasons which will become apparent from the description given herein-below. The other integrated circuit, regulation circuit CI2, is on the contrary placed on the side of the secondary winding ES1 and is used to examine the output voltage Vs of the power supply in order to produce regulation signals that it transmits to the first integrated circuit through a small transformer TX. The first integrated circuit CI1 uses these regulation signals to modify the duty cycle of conduction of the switching transistor Tp and thus of adjusting the output voltage Vs of the power supply.

FIG. 1 shows the line of the public electric distribution mains under reference 10 (local supply circuit or mains at 110 or 220 volts, 50 or 60 hertz). This line is connected through a filter 12 to the input of a rectifying bridge 14, the output of which is connected on the one hand to a primary electric mass, represented throughout by a black triangle pointing downwards, and on the other hand to one end of the primary winding EP of the supply transformer TA.

A filtering capacitor 16 is placed in parallel on the outputs of the rectifying bridge 14. The other end of the primary winding is connected to the collector of the switching transistor Tp, the emitter of which is connected to the primary mass through a small current measuring resistance 18.

The transformer is provided with several secondary windings that are preferably galvanically insulated from the mains and connected for example to a secondary electric mass galvanically insulated from the primary mass.

In the present description, each of the secondary windings has one end connected to the secondary mass. The other end supplies a respective low-pass filtering capacitor through a respective rectifying diode.

Reference in the following description will be made to a single secondary winding ES1, connected by a diode 20 to a capacitor 22. The direct output voltage of the switch mode supply is the voltage Vs at the terminals of the capacitor 22; but it is well understood that other direct output voltages can be obtained at the terminals of the other filtering capacitors connected to the secondary windings. These output voltages constitute stabilized power supplies for utilization circuits (not represented). By way of example, a secondary winding ES2 supplies a stabilized power voltage of several volts for the regulation integrated circuit CI2 to which reference was made herein-above. It is thus checked that the circuit is not powered and therefore cannot supply signals as long as the switching does not function.

The same is true a priori for the base control integrated circuit CI1 of the power transistor Tp, which circuit is powered by a stabilized voltage supplied from a secondary winding ES3, from a diode 24 and from a capacitor 26 (it will be noted that this winding, although being a secondary winding is connected to the primary ground and not to the secondary mass, this for the very simple reason that the integrated circuit CI1 is necessarily galvanically connected to the primary).

However, as it is necessary to ensure starting of the chopped power supply, it has been foreseen that the power terminal 28 of the integrated circuit CI1 is also directly connected to the mains through a high resistance 30 and a diode 32; this is possible since the integrated circuit CI1 is connected to the primary ground; it is not possible for the circuit CI2 which must remain galvanically insulated from the mains. Once the switch mode power supply functions normally, the stabilized direct voltage issuing from the winding ES3 and from the diode 24 has priority over the voltage issuing from the mains and from the diode 32; this diode 32 is blocked and the direct power supply through the mains no longer intervenes after the initial starting phase.

The role of the integrated circuits CI1 and CI2 will now be defined.

The regulation circuit CI2 receives from a divider bridge 34, placed at the terminals of the capacitor 22, i.e. at the output of the stabilized power supply, data as to the value of the voltage to be stabilized Vs.

This data is compared with a desired value and applied to a pulse width modulator that establishes periodic square pulses having variable width in function of the value of the output voltage Vs; the lower is Vs the larger will be the width of the square pulses.

The square pulses are established at the switching frequency of the switch mode supply. This frequency is thus established on the side of the secondary of the circuit; it is generated either inside the circuit CI2, or outside in a circuit (not shown) in the form of a saw-tooth shaped voltage at the selected switching frequency. This saw-tooth voltage is used in a manner known per se to perform the width modulation.

The variable width square pulses, at the switching frequency, are applied to a primary winding 36 of a small transformer TX, the secondary winding, 38, of which is galvanically insulated from the primary, supplies positive and negative pulses to the rising and descending edges, respectively of the variable width square pulses.

It is these position and frequency pulses determined by the regulation circuit CI2, which constitute regulation signals applied to an input 40 of the base control circuit CI1.

The transformer TX is constituted by several coil turns wound on a ferrite rod, the turns of the primary and the turns of the secondary being sufficiently spaced apart from one another to respect the galvanic insulation standards between primary circuits and secondary circuits of the switch mode supply.

The base control integrated circuit CI1 comprises various inputs among which have been mentioned herein-above a power input 28 and a regulation signal input 40; a current measuring input 44 connected to the current measuring resistor 18; and an inhibition input allowing to check the magnetization state of a transformer. Furthermore, inputs can be provided to connect the elements (resistors, capacitors) that should form part of the integrated circuit itself but which for technological reasons (of bulk) or for practical reasons (possibilities of adjustment by the user) are externally mounted.

The integrated circuit CI1 furthermore comprises an output 46 which is intended to be connected by a direct galvanic connection to the base of the power transistor Tp. This output supplies square pulses for bringing the transistor Tp to the on or off state.

FIG. 2 represents partially the general structure of the integrated circuit CI1.

The output 46 of the circuit, intended for the base control of the transistor Tp, is the output of a push-pull amplification stage designated by the reference 48, this stage preferably comprising two separated amplifiers one of which receives square pulses which are inverted and delayed by several microseconds for to producing to the on state. Such amplifiers are well known.

The signals for switching to the on stae are issued from a logic flip-flop 50 having a set input 52 and a reset input 54. The set input triggers the on state of the power transistor. The reset input triggers the off state.

The set input 52(S) receives the pulses that pass through an AND gate 58, so that the triggering of the on state only occurs when several conditions are simultaneously satisfied; if a single condition is not satisfied, this is sufficient to inhibit the triggering of the on state.

The reset input 54(R) receives the pulses which pass through an OR gate 60, so that the interruption of the on state (after triggering of the on state) occurs once a halt signal is present on one of the inputs of this gate.

On the diagram of FIG. 2, the AND gate 58 has three inputs. One of these inputs receives periodic pulses issuing from an output 62 of a high frequency oscillator 64; the other inputs act to inhibit the transmission of these pulses.

The oscillator defines the switching period of the power supply (20 kilohertz for example). In normal operating state the oscillator 64 is synchronized by the regulation signals. In starting state it is self-oscillating at a free frequency defined by the values of a resistor Ro and of a capacitor Co outside the integrated circuit CI1 and respectively connected to an access terminal 66 and an access terminal 68. The free frequency Fo is as a rule slightly lower than the normal switching frequency.

The oscillator 64 is a relaxation oscillator that produces on an output 70 a saw-tooth, the reset to zero of which is set by the appearance of a positive pulse arriving at the terminal 40. This is the reason why the oscillator 64 is represented with an input connected to an output 72 of a separation and shaping circuit 74 that receives the regulation signals from the terminal 40 and shapes them by separating the positive pulses from the negative pulses. The shaping circuit 74 has two outputs: 72 for the positive pulses, 76 for the negative pulses (the notation of positive pulse and negative pulse will be retained in order to distinguish the triggering pulses for the on state and the triggering pulses for the off state even if the shaping circuit establishes pulses of a single sign on its two outputs 72 and 76).

The oscillator 64 has two outputs; an output 70 supplying a saw-tooth signal and an output 62 supplying a short pulse when the saw-tooth is reset to zero.

A pulse width modulator 78 is connected on the one hand to the output 70 of the oscillator and on the other hand to an adjustable reference voltage through a resistor R1 outside the integrated circuit and connected to an access terminal 80 to the circuit. The modulator 78 supplies periodic square pulses synchronized with the oscillator signals, these square pulses defining a maximal duration of the on state Tmax beyond which the off state of the power transistor must be triggered in any case as a matter of security. These square pulses of modulator 78 are applied to an input of the OR gate 60. The duration Tmax is adjustable through the external resistor R1.

The elements that have been described herein-above ensure the essential of the operating at normal condition of the integrated circuit CI1. The following elements are more specifically provided for controlling the anomalous operating or the starting of the power supply.

A very low frequency oscillator 82 is connected to an external capacitor C2 through an access terminal 86. This external capacitor adjusts the very low oscillation frequency. The frequency can be 1 hertz, for example.

The oscillator 82 is a relaxation oscillator supplying a saw-tooth signal which is applied on the one hand to a threshold comparator 88 which establishes periodic square pulses which are synchronized on the saw-tooth at a low frequency of the oscillator. These square pulses have a brief duration compared to the saw-tooth period. This duration is fixed by the threshold of the comparator 88. It can be for example of 10% of the period. It must be long with respect to the free oscillation period of the high frequency oscillator 64 so that a burst of numerous pulses of the high frequency oscillator can be emitted and utilized during this 10% of the period at very low frequency. This burst defines an attempt at starting during the first part of a starting cycle. It is followed by a pause during the remainder of the period, i.e. during the remaining 90% of the period.

The oscillator 82 only functions for the starting. It is inhibited when the regulation signals appear on the terminal 40 and indicate that the switch mode supply is functioning. This is the reason why an inhibition control of this oscillator has been represented, connected to the output 72 of the shaping circuit 74 through a flip-flop 89 which changes its condition under the effect of the pulses appearing at the output 72. It is returned to its initial condition by the output 62 of the oscillator 64 when there are no more pulses on the output 71.

The saw-tooth signals of the oscillator at very low frequency are furthermore transmitted to a circuit 90 for producing a variable threshold whose function is to establish a threshold signal (current or voltage) having a first value Vs1 in normal operating condition, and a cyclically variable threshold between the first value and a second value at starting condition.

The threshold signal established by the circuit 90 is applied to an input of a comparator 92, the other input of which is connected to the terminal 44 already mentioned, in order to receive on this input a signal that is representative of the amplitude of the current flowing through the power switching device. The output of the comparator 92 is applied to an input of the OR gate 60. It thus triggers the off state of the power transistor Tp, after an on state firing, the off state occuring, when exceeding the threshold (fixed or variable) defined by the circuit 90 has been detected.

Another threshold comparator 94 has an input connected to the current measuring terminal 44 while another input receives a signal representing a third threshold value Vs3. The third value Vs3 corresponds to a current in the switch which is higher than the first value vs1 defined by the circuit 90. The output of the comparator 94 is connected through a latch 96 to an input of the AND gate 58 whereby if the current in the power switch exceeds the third threshold value Vs3, an interruption of the on state of the transistor Tp is not triggered (this interruption is triggered by the comparator 92) but an inhibition of any firing of the transistor. This inhibition lasts until the flip-flop 96 is reset to its initial state corresponding to a normal operating.

As a rule, this return will only occur when the integrated circuit CI1 will have ceased to be normally supplied with power and will be again set under voltage. For example, the return of the latch 96 occurs through a hysteresis threshold comparator 98 which compares one fraction of the power supply voltage Vcc of the circuit (drawn off from the terminal 28) with a reference value and which resets the latch during the first passage of Vcc above this reference after a drop of Vcc below another reference value that is lower than the first one (hysteresis).

Moreover, it can be specified that the output of the flip-flop 89 (which detects the presence of regulation signals on the terminal 40 thus the normal operating of the power supply) is connected to an input of an OR gate 100 which receives on another input the output of the comparator 88 so that the output of the comparator 88 ceases to inhibit the firing of the transistor Tp (inhibition during 90% of the very low frequency cycles) once the operating of the power circuit becomes normal.

OBJECT OF THE INVENTION

Therefore, in the device previously manufactured by the applicant and described in detail herein-above, particular procedures for the starting phases and particular protective procedures in the case of functioning incidents are foreseen.

The present invention aims at further improving the operating safety by detecting operating deficiencies over a longer period of time than was the case with circuits of the prior art. Although the invention presents a novel and distinct contribution with respect to the process of the prior art, the prior device has been described in full detail herein-above in order to render apparent the numerous restrictions which are imposed during production of a novel safety device which must take into account all the possible types of operating foreseen in an already existing circuit without introducing deficiencies or blockages in the normal operating of the circuit in its differnt modes. Consequently, any novel contribution to a complex structure such as that described herein-above requires numerous selections and very numerous attempts between various solutions that could appear a priori as simple must be carried out.

SUMMARY OF THE INVENTION

Therefore, the present invention provides a device for protection against extended overloading in switch mode power supplies comprising a main switch controlled by output signals from a flip-flop of which the inputs for setting to 1 and for resetting to zero receive regulation control signals, a first protection circuit supplying on the input for resetting to zero signals which have priority with respect to the regulation signals when the current in the main switch exceeds a predetermined threshold, further comprising a second protection circuit itself comprising:

means for detecting cycles for which the first protection circuit operates and interrupts the on state of the main switch prior to the arrival of the switching off order of the regulation signal;

memorization means accumulating at each cycle a value proportional to the duration between a signal of the detection means and the setting to 1 signal associated to the regulation signal of the following cycle; and

inhibition means for inhibiting the set input of the flip-flop when the memorization means have accumulated a signal higher than a predetermined threshold.

According to one embodiment of the present invention, the detection means comprise a second flip-flop, a third flip-flop and an AND gate:

the second flip-flop receiving at its reset input the output for starting the regulation, the set input of this flip-flop receiving the output of the AND gate and the output of this flip-flop controlling the memorization means;

the third flip-flop having its set input connected to the reset input of the second flip-flop, its reset input connected to the reset signal of the regulation signal, and its output connected to a first input of the AND gate,

the second input of the AND gate being connected to the output of the first protection circuit.

According to one embodiment of the present invention, the memorization means comprise a capacitor permanently discharged by discharging means and temporarily charged by charging means only when the detection circuit supplies a signal.

According to another embodiment of the invention, the inhibition means comprise a comparator comparing the signal accumulated by the memorization means with a reference value, the output signal of this comparator inhibiting the set input of the flip-flop when the memorized signal becomes higher than a reference value.

BRIEF DESCRIPTION OF THE DRAWING

These objects, features and advantages and others of the present invention will become apparent from the following embodiment given by way of non-limitative illustration with reference to the appended drawing in which:

FIGS. 1 and 2 illustrate a switch mode power supply according to the prior art and have been described herein-above;

FIG. 3 is a simplified representation of a protection circuit against the overloading of a switch mode power supply according to the prior art;

FIG. 4 illustrates the protection circuit against overloads of long duration according to the present invention for switch mode power supplies; and

FIGS. 5-a to to 5-b are time charts intended to illustrates the functioning of the circuits represented in FIGS. 3 and 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 once again represents in a simplified manner the essential components of the circuit represented in FIG. 2 constituting a protection circuit against the excess currents in the main transistor Tp. The on state in the transistor Tp is normally controlled by a signal available on a terminal 40, resulting from a pulse width modulation circuit which controls a flip-flop 50 through a shaping circuit 74. The flip-flop 50 energizes the base of the power transistor Tp through a preamplification circuit (driver) 48 and an access terminal 46. When the current in the power transistor exceeds a given threshold, the voltage at the terminals of a resistor 18 available at the terminal 44 is compared with a threshold voltage Vs by a comparator 92 and, should this voltage exceed the threshold, the reset input R of the flip-flop 50 is energized through an OR gate 60, the other input of which receives an output signal from the shaping circuit 74.

This protection device effectively protects the switch Tp against a current overloading but does not always allow good protection of the power supply, for example in the case of long duration overloading. In fact, there is no protection against excessive heating of the transformer TA or of the rectifying diodes 20 (cf. FIG. 1) or of other components of the circuit connected to the secondary of the main transformer and it is generally necessary to over-size these components in order to take into account long duration overloadings which could occur as a result, for example, of short-circuiting on the secondary winding.

The invention which will be described herein-below with respect to FIGS. 4 and 5 concerns a device which, added to the conventional current limitation circuit described herein-above, provokes the total and definitive shut down of the power supply in the case of long duration functioning of the current limitation system. Expensive over-sizing of certain components is thus avoided and the operating safety of the power supply is as a whole increased.

The restarting of the power supply can be obtained by the momentary setting out of voltage of the system or at least of the device concerned.

As represented on FIG. 4, the present invention comprises a circuit 100 for detecting the operating of an overload circuit, comprising flip-flops FF2 and FF3 and an AND gate 101, and a circuit 102 for memorization and inhibition of the switch mode power supply. The circuit 102 operates the above described base current control flip-flop 50 through an AND gate 58.

The memorization and inhibition circuit 102 comprises a capacitor 103, a discharge system constituted by a current supply 104 functioning permanently, a system for charging this capacitor constituted by a current supply 105 controlled in all or nothing by a switch 107 receiving the output of the detection circuit 100. When the detection circuit 100 indicates that the current limitation circuit in the power switch Tp does not function, only the discharge system 104 functions and the capacitor 103 remains discharged. When the current limitation system 100 is energized, the charge system (current supply 105) is activated. The ratio between the discharge current and the charge current is selected so that overall the capacitor 103 is charged. When the voltage at the terminals of the capacitor reaches a determined value, fixed by a comparator 106, a flip-flop FF4 is triggered which definitively inhibits the on state of the switch Tp.

In the circuit 100 for detecting the functioning of the current limitation circuit, the flip-flop FF2 has its reset input R2 connected to the output 72 of the form shaping circuit 74, its set input S2 connected to the output of the AND gate 101 and its output Q2 connected to the control terminal of the switch 107 of the circuit 102. The second flip-flop FF3 has its set input S3 connected to the output 72 of the shaping circuit 74, its reset input R3 connected to the output 76 of this shaping circuit and its output Q3 connected to a first input of the AND gate 101 of which the other input is connected to the output of the comparator 92 detecting the excess currents in the power transistor Tp.

FIG. 5 indicates a time chart of the signals appearing in different points of the circuit in four particular operating cases. In FIG. 5

the line a indicates the signals present at the terminal 40 or more exactly the control signals from which result the signals at the terminal 40 following the action of the insulating transformer TX (cf. FIG. 1). Those signals correspond to more or less long square pulses according to the error signal detected;

the line b indicates the signal present at the output 76 of the shaping circuit 74, normally provoking the setting to 1 of the flip-flop 50;

the line c indicates the signal at the output 76 of the shaping circuit 74, normally controlling the reset of the flip-flop 50;

the line d indicates the signal at the output Q2 of the flip-flop FF2 controlling the switch 107;

the line e indicates the signal Q3 at the output of the flip-flop FF3;

the line f indicates the signal at the input R of the flip-flop 50, i.e. the signal at the output of the OR gate 60. This signal corresponds to the rising edge of the pulse at the output 76 of the shaping circuit 74 or at the output of the comparator 92;

the line g indicates the current in the power transistor that corresponds to the signal present on the input 44 of the comparator 92;

the line h indicates the signal at the output of the comparator.

The operating of this circuit in four possible functioning modes will now be studied.

1. Normal operating without overloading

No signal is supplied to the output of the comparator 92 and it is the outputs 72 and 76 (signals of lines b and c) that control the inputs S and R of the flip-flop 50. The circuit 102 not receiving any output signal from the circuit 100 supplies to the output Q4 of the flip-flop FF4 a high level signal and the AND gate 58 is validated thereby allowing the output signal 72 of the shaping circuit 74 to reach the input S of the flip-flop 50.

2. Functioning in lower overloading limit

As shown by line g of FIG. 5, it concerns the case where the reset pulse of the flip-flop 50 tends to bring the switch Tp at the off state prior to an overloading detection (current in Tp higher than I Max) occuring, but where an overloading occurs between the off state order and the effective off state of the power transistor. This delay is due to the blocking period or storing time ts of the switch which is not nil in particular in the case where a high voltage bipolar transistor is utilized. The current limitation comparator 92 is thus energized. However, the output signal of the comparator 92 does not reach the flip-flop FF2 to supply an output signal Q2 since the flip-flop FF3 has been previously reset by the signal 76 and blocks the AND gate 101. the flip-flop FF2 thus remains at zero and as in the preceding case, the circuit 102 is not energized and the regulation circuit continues to operate normally. It would in fact be inconvenient to shut down the operating of the chopping power supply in this particular case.

3. Operating in moderate overloading

As in the previous case, it is the output signal 72 of the shaping circuit 74 that provokes the bringing to the on state of the power transistor but, as shown by line g, the overload level of the power transistor Tp is reached prior to the normal off state signal of the transistor (line c) occuring. In this case, the comparator 92 supplies a signal which is transmitted through AND gate 101 enabled by the flip-flop FF3 to the flip-flop Q2 which is set to 1. The switch 107 of the memorization and inhibition circuit 102 is thus closed and the charge process of the capacitor 103 begins.

It will be noted that the signal Q2 (line d) remains at high level until the triggering pulse of the following cycle (bringing of the output 72 at high level). Therefore, the earlier overloading arrives in the cycle, the more the signal Q2 is present during a long period. After several functioning cycles, the voltage accumulated on the capacitor 103 will be higher than the reference voltage VRef applied to the second terminal of the comparator 106. Subsequently, the flip-flop FF4 supplies a signal at low level to its output Q4 and the AND gate 58 invalidates the input S of the flip-flop 50. This occurs only if the overloading lasts over a certain number of cycles. Thus, the functioning of the switch mode power supply is definitively brought to the off state indicating an operating failure of the device, for example a short-circuiting of a secondary winding of the transformer TA (cf. FIG. 1). To start up again the switch mode power supply, it is necessary to apply a new signal to the input R4 of the flip-flop FF4. This input can for example be connected to an initialization device when the whole of the switch mode power supply is powered.

4. Operating under strong overloading

This operating mode is illustrated on the right side of FIG. 5. It is as a whole identical to the case of a moderate overloading but it has been represented only to show the elongation of the pulses Q2 when the overloading occurs very early in an operating cycle of the switch mode power supply.

The various advantages of the present invention thus become apparent. On the one hand; the operating delay time is easily programmable by means of a single component, for example the value of the capacity of the capacitor 103. On the other hand, automatically, due to the elongation of the pulse Q2 when the overloading occurs early in a cycle, the action delay is modulated in function of the intensity of the overloading. Therefore, the greater is the overloading, the shorter is the operating delay time.

Another advantage lies in the perfect simultaneity of the triggering of the timing of the device according to the invention and of the operating of the conventional limitation of the current as described in the description of the prior art. This results in very good operating security. The risk of spurious triggering of the device close to the lower current limit is thus prevented.

On the other hand, as has been seen, the device according to the invention operates well with a power switch constituted by a bipolar transistor in which the storage time is relatively long, but this circuit is perfectly adaptable to a switch of which the off state delay tends towards zero such as a MOS power transistor.

Similarly, accordng to another advantage of the invention, this circuit is perfectly compatible with the other protection and starting assistance circuits which utilized the circuits according to the prior art. Indeed, it will be noted that the components of the circuit according to the invention are perfectly compatible with the components of the current limitation circuit described herein-above. Furthermore, the AND gate 58 that has the circuit at the off state when it is not operating bears the same reference as the AND gate 58 described in relation with FIG. 2. In fact, it can be the same gate comprising simply a supplementary input. Herein lies another advantage of the invention, i.e. it is perfectly compatible with the automatic starting circuit described in relation with FIGS. 1 and 2. In this automatic starting mode, which may be called burst mode, it is also desired to be able to detect and stop the power supply in the case of overloading. However, as mentioned herein-above in the initial burst method, the circuit operates only with a duty cycle of about 10%. In this case, the capacitor 103 risks to be insufficiently charged during this brief action period and to discharge during the 90% of non-operating. To overcome this, it is foreseen according to the present invention to inhibit the discharging of the capacitor 103 by providing a controlled switch (not represented) in series with the discharge current supply 104 and energized by a signal indicative of the fact that operating is taking place in the burst mode. Therefore, in the case of overloading in the burst method, the capacitor is charged a little at each burst and retains its voltage between the bursts. It is therefore possible to reach the voltage VRef after a certain number of burst.

 
ITT NOKIA IDEAL COLOR 4210 OS CHASSIS CORE 90° MN PAL RGB /IFB-620 16  CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:
A stabilized supply voltage circuit for a picture display device comprising a chopper wherein the switching signal has the line frequency and is duration-modulated. The coil of the chopper constitutes the primary winding of a transformer a secondary winding of which drives the line output transistor so that the switching transistor of the chopper also functions as a driver for the line output stage. The oscillator generating the switching signal may be the line oscillator. In a special embodiment the driver and line output transistor conduct simultaneously and in order to limit the base current of the line output transistor a coil shunted by a diode is incorporated in the drive line of the line output transistor. Other secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode of the chopper so as to generate further stabilized supply voltages.

1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4. A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.

Description:

The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.

Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply voltage device.

In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.

It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.

The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.

As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.

Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.

In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:

FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.

FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.

FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.

FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.

In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.

The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V _i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V _o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V _o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V ₀ . In fact, it is readily evident that output voltage V _o is proportional to the ratio δ :

V _o = V _i ^. δ

Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V ₀ . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V _o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V _o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).

However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V _o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.

In addition this facilitates smoothing of voltage V _o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V _o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.

It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.

In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.

A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.

In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V _o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.

It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i _C which flows in the collector of transistor 16 and of the drive voltage v ₁₄ across the terminals of secondary winding 14. During the flyback period (0, t ₁ ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v ₁₄ must then be absolutely negative. During the scan period (t ₁ , t ₄ ) a sawtooth current i _C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t ₃ when current i _C becomes zero lies, as is known, before the middle of the scan period. At the end t ₄ of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t _s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v ₁₄ is positive must end at the latest at the instant (t ₄ - t _s ) located after the commencement (t = 0) of the previous flyback.

The time δ T may be initiated at any instant t ₂ which is located between the end t ₁ of the flyback period and the instant t ₃ when collector current i _C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t ₂ , but collector current i _C is not influenced thereby, at least not when the supply voltage (= V _o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i _C of FIG. 2a represents the current flowing through the said efficiency diode.

After the instant t ₃ voltage v ₁₄ must be positive. In other words, the minimum duration of the period T when voltage v ₁₄ must be positive is (t ₄ - t _s ) - t ₃ whilst the maximum duration thereof is (t ₄ - t _s ) - t ₁ . In a television system employing 625 lines per raster the line period t ₄ is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t ₃ would be located approximately 26 μus after the instant t ₁ , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t _s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V _i has a peak-to-peak value of 40 V and V _i is nominally 270 V, then the lowest occurring V _i is:

0.85 × 270 V - 20 V = 210 V and the highest occurring V _i is

1.1 × 270 V + 20 V = 320 V. For an output voltage V _o of 135 V the ratio must thus vary between

δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.

A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V _i - V _o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V _o is maintained constant at nominal mains voltage V _o = δ V _inom . However, if as a result of an increase or a decrease of the mains voltage V _i increases or decreases proportionally therewith, i.e., V _i = V _i nom + Δ V, the positive portion of V ₁₄ becomes equal to n(V _i nom - V _o +Δ V) = n [(1 -δ)V _i nom +ΔV] = n(0.5 V _inom +ΔV) if δ = 0.5 for V _i = V _i nom. Relatively, this is a variation which is twice as great. For example, if V _i nom = 270 V and V _o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V _i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.

This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i _b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i _b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V _i = V _i nom +Δ V, then ##SPC1## because V _i nom = 2 V _o . Thus this variation is equal to that of the mains voltage and is not twice as great.

During switching off, t ₂ , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.

The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.

FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V _i - V _o = 0.5 V _i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V _i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.

Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.

In this connection it is to be noted that it is possible to obtain an output voltage V _o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V _i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.

The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.

If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V _o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V _o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.

The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V _o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V _i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.

Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V _o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.

Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.

As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.

A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V _o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.

Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.

The 50 Hz ripple voltage which is superimposed on the rectified input voltage V _i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V _i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.

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[8] Peterson, W.A., A FREQUENCY-STABILIZED FREE-RUN-
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EXTENSION TECHNIQUE FOR SINGLE ENDED FORWARD
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More References:
Buhler H (1986) Sliding mode control (in French: Reglage  ́
 par mode de glissement). Presses
Polytechniques Romandes, Lausanne
Carpita M, Marchesoni M (1996) Experimental study of a power conditioning system using sliding
mode control. IEEE Trans Power Electron 11(5):731–742
Carrasco JM, Quero JM, Ridao FP, Perales MA, Franquelo LG (1997) Sliding mode control of a
DC/DC PWM converter with PFC implemented by neural networks. IEEE Trans Circuit Syst I
Fundam Theor Appl 44(8):743–749
DeBattista H, Mantz RJ, Christiansen CF (2000) Dynamical sliding mode power control of wind
driven induction generators. IEEE Trans Energy Convers 15(4):728–734
DeCarlo RA, Zak  ̇
 SH, Drakunov SV (2011) Variable structure, sliding mode controller design. In:
Levine WS (ed) The control handbook—control system advanced methods. CRC Press, Taylor
& Francis Group, Boca Raton, pp 50-1–50-22
Emelyanov SV (1967) Variable structure control systems. Nauka, Moscow (in Russian)
Filippov AF (1960) Differential equations with discontinuous right hand side. Am Math Soc
Transl 62:199–231
Guffon S (2000) Modelling and variable structure control for active power filters (in French:
“Modelisation  ́
 et commandes `
 a structure variable de filtres actifs de puissance”). Ph.D. thesis,
Grenoble Institute of Technology, France
Guffon S, Toledo AS, Bacha S, Bornard G (1998) Indirect sliding mode control of a three-phase
active power filter. In: Proceedings of the 29th annual IEEE Power Electronics Specialists
Conference – PESC 1998. Kyushu Island, Japan, pp 1408–1414
Hung JY, Gao W, Hung JC (1993) Variable structure control: a survey. IEEE Trans Ind Electron
40(1):2–22
Itkis U (1976) Control systems of variable structure. Wiley, New York
Levant A (2007) Principles of 2-sliding mode design. Automatica 43(4):576–586
Levant A (2010) Chattering analysis. IEEE Trans Autom Control 55(6):1380–1389
Malesani L, Rossetto L, Spiazzi G, Tenti P (1995) Performance optimization of Cuk  ́
 converters by
sliding-mode control. IEEE Trans Power Electron 10(3):302–309
Malesani L, Rossetto L, Spiazzi G, Zuccato A (1996) An AC power supply with sliding mode
control. IEEE Ind Appl Mag 2(5):32–38
Martinez-Salamero L, Calvente J, Giral R, Poveda A, Fossas E (1998) Analysis of a bidirectional
coupled-inductor Cuk  ́
 converter operating in sliding mode. IEEE Trans Circuit Syst I Fundam
Theor Appl 45(4):355–363
Mattavelli P, Rossetto L, Spiazzi G (1997) Small-signal analysis of DC–DC converters with
sliding mode control. IEEE Trans Power Electron 12(1):96–102
ˇ
Sabanovic A (2011) Variable structure systems with sliding modes in motion control—a survey.
IEEE Trans Ind Inform 7(2):212–223
Sabanovic ˇ
 A, Fridman L, Spurgeon S (2004) Variable structure systems: from principles to
implementation, IEE Control Engineering Series. The Institution of Engineering and Technol-
ogy, London

Sira-Ramırez  ́  H (1987) Sliding motions in bilinear switched networks. IEEE Trans Circuit Syst 34
(8):919–933
Sira-Ramırez  ́
 H (1988) Sliding mode control on slow manifolds of DC to DC power converters. Int
J Control 47(5):1323–1340
Sira-Ramırez  ́
 H (1993) On the dynamical sliding mode control of nonlinear systems. Int J Control
57(5):1039–1061
Sira-Ramırez  ́
 H (2003) On the generalized PI sliding mode control of DC-to-DC power converters:
a tutorial. Int J Control 76(9/10):1018–1033
Sira-Ramırez  ́
 H, Silva-Ortigoza R (2006) Control design techniques in power electronics devices.
Springer, London
Slotine JJE, Sastry SS (1983) Tracking control of non-linear systems using sliding surface, with
application to robot manipulators. Int J Control 38(2):465–492
Spiazzi G, Mattavelli P, Rossetto L, Malesani L (1995) Application of sliding mode control to
switch-mode power supplies. J Circuit Syst Comput 5(3):337–354
Tan S-C, Lai YM, Cheung KHM, Tse C-K (2005) On the practical design of a sliding mode
voltage controlled buck converter. IEEE Trans Power Electron 20(2):425–437
Tan S-C, Lai Y-M, Tse C-K (2011) Sliding mode control of switching power converters:
techniques and implementation. CRC Press, Taylor & Francis Group, Boca Raton
Utkin VA (1972) Equations of sliding mode in discontinuous systems. Autom Remote Control 2
(2):211–219
Utkin VA (1977) Variable structure systems with sliding mode. IEEE Trans Autom Control 22
(2):212–222
Utkin V (1993) Sliding mode control design principles and applications to electric drives. IEEE
Trans Ind Electron 40(1):23–36
Venkataramanan R, Sabanovic ˇ
 A, Cuk  ́
 S (1985) Sliding mode control of DC-to-DC converters. In:
Proceedings of IEEE Industrial Electronics Conference – IECON 1985. San Francisco,
California, USA, pp 251–258
Young KD, Utkin VI, Ozguner U (1999) A control engineer’s guide to sliding mode control. IEEE
Trans Control Syst Technol 7(3):328–342

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Other References
Buhler H (1986) Sliding mode control (in French: Reglage  ́
 par mode de glissement). Presses
Polytechniques Romandes, Lausanne
Carpita M, Marchesoni M (1996) Experimental study of a power conditioning system using sliding
mode control. IEEE Trans Power Electron 11(5):731–742
Carrasco JM, Quero JM, Ridao FP, Perales MA, Franquelo LG (1997) Sliding mode control of a
DC/DC PWM converter with PFC implemented by neural networks. IEEE Trans Circuit Syst I
Fundam Theor Appl 44(8):743–749
DeBattista H, Mantz RJ, Christiansen CF (2000) Dynamical sliding mode power control of wind
driven induction generators. IEEE Trans Energy Convers 15(4):728–734
DeCarlo RA, Zak  ̇
 SH, Drakunov SV (2011) Variable structure, sliding mode controller design. In:
Levine WS (ed) The control handbook—control system advanced methods. CRC Press, Taylor
& Francis Group, Boca Raton, pp 50-1–50-22
Emelyanov SV (1967) Variable structure control systems. Nauka, Moscow (in Russian)
Filippov AF (1960) Differential equations with discontinuous right hand side. Am Math Soc
Transl 62:199–231
Guffon S (2000) Modelling and variable structure control for active power filters (in French:
“Modelisation  ́
 et commandes `
 a structure variable de filtres actifs de puissance”). Ph.D. thesis,
Grenoble Institute of Technology, France
Guffon S, Toledo AS, Bacha S, Bornard G (1998) Indirect sliding mode control of a three-phase
active power filter. In: Proceedings of the 29th annual IEEE Power Electronics Specialists
Conference – PESC 1998. Kyushu Island, Japan, pp 1408–1414
Hung JY, Gao W, Hung JC (1993) Variable structure control: a survey. IEEE Trans Ind Electron
40(1):2–22
Itkis U (1976) Control systems of variable structure. Wiley, New York
Levant A (2007) Principles of 2-sliding mode design. Automatica 43(4):576–586
Levant A (2010) Chattering analysis. IEEE Trans Autom Control 55(6):1380–1389
Malesani L, Rossetto L, Spiazzi G, Tenti P (1995) Performance optimization of Cuk  ́
 converters by
sliding-mode control. IEEE Trans Power Electron 10(3):302–309
Malesani L, Rossetto L, Spiazzi G, Zuccato A (1996) An AC power supply with sliding mode
control. IEEE Ind Appl Mag 2(5):32–38
Martinez-Salamero L, Calvente J, Giral R, Poveda A, Fossas E (1998) Analysis of a bidirectional
coupled-inductor Cuk  ́
 converter operating in sliding mode. IEEE Trans Circuit Syst I Fundam
Theor Appl 45(4):355–363
Mattavelli P, Rossetto L, Spiazzi G (1997) Small-signal analysis of DC–DC converters with
sliding mode control. IEEE Trans Power Electron 12(1):96–102
ˇ
Sabanovic A (2011) Variable structure systems with sliding modes in motion control—a survey.
IEEE Trans Ind Inform 7(2):212–223
Sabanovic ˇ
 A, Fridman L, Spurgeon S (2004) Variable structure systems: from principles to
implementation, IEE Control Engineering Series. The Institution of Engineering and Technol-
ogy, London

References:
 Sira-Ramırez  ́
 H (1987) Sliding motions in bilinear switched networks. IEEE Trans Circuit Syst 34
(8):919–933
Sira-Ramırez  ́
 H (1988) Sliding mode control on slow manifolds of DC to DC power converters. Int
J Control 47(5):1323–1340
Sira-Ramırez  ́
 H (1993) On the dynamical sliding mode control of nonlinear systems. Int J Control
57(5):1039–1061
Sira-Ramırez  ́
 H (2003) On the generalized PI sliding mode control of DC-to-DC power converters:
a tutorial. Int J Control 76(9/10):1018–1033
Sira-Ramırez  ́
 H, Silva-Ortigoza R (2006) Control design techniques in power electronics devices.
Springer, London
Slotine JJE, Sastry SS (1983) Tracking control of non-linear systems using sliding surface, with
application to robot manipulators. Int J Control 38(2):465–492
Spiazzi G, Mattavelli P, Rossetto L, Malesani L (1995) Application of sliding mode control to
switch-mode power supplies. J Circuit Syst Comput 5(3):337–354
Tan S-C, Lai YM, Cheung KHM, Tse C-K (2005) On the practical design of a sliding mode
voltage controlled buck converter. IEEE Trans Power Electron 20(2):425–437
Tan S-C, Lai Y-M, Tse C-K (2011) Sliding mode control of switching power converters:
techniques and implementation. CRC Press, Taylor & Francis Group, Boca Raton
Utkin VA (1972) Equations of sliding mode in discontinuous systems. Autom Remote Control 2
(2):211–219
Utkin VA (1977) Variable structure systems with sliding mode. IEEE Trans Autom Control 22
(2):212–222
Utkin V (1993) Sliding mode control design principles and applications to electric drives. IEEE
Trans Ind Electron 40(1):23–36
Venkataramanan R, Sabanovic ˇ
 A, Cuk  ́
 S (1985) Sliding mode control of DC-to-DC converters. In:
Proceedings of IEEE Industrial Electronics Conference – IECON 1985. San Francisco,
California, USA, pp 251–258
Young KD, Utkin VI, Ozguner U (1999) A control engineer’s guide to sliding mode control. IEEE
Trans Control Syst Technol 7(3):328–342

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69. Ackermann, W., and Hirschmann, W., “Switching Power Supplies 2, (Components and Their Selection
and Application Criteria),” Siemens Application Note.
70. Schaller, R., “Switching Power Supplies 3, (Radio Interference Suppression),” Siemens Application Note.
71. Macek, O., “Switching Power Supplies 4, (Basic Dimensioning), “Siemens Application Note.
72. Bulletin SFB, Buss Small Dimension Fuses, Bussmann Division, McGraw-Edison Co., Missouri.
73. Catalog #20, Littlefuse Circuit Protection Components, Littlefuse Tracor, Des Plaines, III.
74. Bulletin-B200, Brush HRC Current Limiting Fuses, Hawker Siddeley Electric Motors, Canada.
75. Bulletins PC-104E and PC109C, MPP and Iron Powder Cores, The Arnold Engineering Co., Marengo,
Illinois.
76. Publication TP-25-575, HCR Alloy, Telcon Metals Ltd., Sussex, England.
77. Catalog 4, Iron Powder Toridal Cores for EMI and Power Filters, Micrometals, Anaheim, Calif.
78. Bulletin 59–107, Soft Ferrites, Stackpole, St. Marys, Pa.
79. SOAR—The Basis for Reliable Power Circuit Design, Philips Product Information #68.
80. Bennett, Wilfred P., and Kurnbatovic, Robert A., “Power and Energy Limitations of Bipolar Transistors
Imposed by Thermal-Mode and Current-Mode Second-Breakdown Mechanisms,” IEEE Transactions
on Electron Devices, vol. ED28, no. 10, October 1981.
81. Roark, D. “Base Drive Considerations in High Power Switching Transistors,” TRW Applications Note
#120, 1975.
82. Gates, T. W., and Ballard, M. F., “Safe Operating Area for Power Transistors,” Mullard Technical Com-
munications, vol. 13, no. 122, April 1974.
83. Williams, P. E., “Mathematical Theory of Rectifier Circuits with Capacitor-Input Filters,” Power Con-
version International, October 1982.
84. “Guide for Surge Voltages in Low-Voltage AC Power Circuits,” IEC Publication 664, 1980.
85. Kit Sum, K., PCIM, February 1998.
86. Spangler, J., Proc. Sixth Annual Applied Power Electronics Conf., Dallas, March 10–15, 1991.
87. Neufeld, H., “Control IC for Near Unity Power Factor in SMPS,” Cherry Semiconductor Corp., October 1989.
88. Micro Linear application notes 16 and 33.
89. Micro Linear application note 34.
90. Micrometals’ “Power Conversion & Line Filter Applications” data book.
91. Pressman, Abraham I., Billings, Keith, Morey, Taylor, Switching Power Supply Design, McGraw-Hill,
2009. ISBN 978-0-07-148272-1.
92. Texas Instruments/Unitrode Data Sheet UCC3895 SLUS 157B & application notes U136A & U154.
93. Stanley, William D., Operational Amplifiers with Linear Integrated Circuits, 2d Ed., Merrill, Columbus,
Ohio, 1989. ISBN 067520660-X.
94. “LM13700 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers,”
National Semiconductor Corporation, 2004. http://www.national.com/ds/LM/LM13700.pdf.

Further References:
1. G. Aboud, Cathode Ray Tubes, 1997, 2nd ed., San Jose, CA, Stanford Resources, 1997.
2. G. Aboud, Cathode Ray Tubes, 1997, Internet excerpts, available http://www.stanfordresources.com/
sr/crt/crt.html, Stanford Resources, February 1998.
3. G. Shires, Ferdinand Braun and the Cathode Ray Tube, Sci. Am., 230 (3): 92–101, March 1974.
4. N. H. Lehrer, The challenge of the cathode-ray tube, in L. E. Tannas, Jr., Ed., Flat Panel Displays
and CRTs, New York: Van Nostrand Reinhold, 1985.
5. P. Keller, The Cathode-Ray Tube, Technology, History, and Applications, New York: Palisades Press,
1991.
6. D. C. Ketchum, CRT’s: the continuing evolution, Society for Information Display International
Symposium, Conference Seminar M-3, 1996.
7. L. R. Falce, CRT dispenser cathodes using molybdenum rhenium emitter surfaces, Society for
Information Display International Symposium Digest of Technical Papers, 23: 331–333, 1992.
8. J. H. Lee, J. I. Jang, B. D. Ko, G. Y. Jung, W. H. Kim, K. Takechi, and H. Nakanishi, Dispenser
cathodes for HDTV, Society for Information Display International Symposium Digest of Technical
Papers, 27: 445–448, 1996.
9. T. Nakadaira, T. Kodama, Y. Hara, and M. Santoku, Temperature and cutoff stabilization of
impregnated cathodes, Society for Information Display International Symposium Digest of Technical
Papers, 27: 811–814, 1996.
10. W. Kohl, Materials Technology for Electron Tubes, New York, Reinhold Publishing, 1951.
11. S. Sugawara, J. Kimiya, E. Kamohara, and K. Fukuda, A new dynamic-focus electron gun for color
CRTs with tri-quadrupole electron lens, Society for Information Display International Symposium
Digest of Technical Papers, 26: 103–106, 1995.
12. J. Kimiya, S. Sugawara, T. Hasegawa, and H. Mori, A 22.5 mm neck color CRT electron gun with
simplified dynamically activated quadrupole lens, Society for Information Display International
Symposium Digest of Technical Papers, 27: 795–798, 1996.
13. D. Imabayashi, M. Santoku, and J. Karasawa, New pre-focus system structure for the trinitron gun,
Society for Information Display International Symposium Digest of Technical Papers, 27: 807–810,
1996.
14. K. Kato, T. Sase, K. Sasaki, and M. Chiba, A high-resolution CRT monitor using built-in ultrasonic
motors for focus adjustment, Society for Information Display International Symposium Digest of
Technical Papers, 27: 63–66, 1996.
15. S. Sherr, Electronic Displays, 2nd ed., New York: John Wiley, 1993.
16. N. Azzi and O. Masson, Design of an NIS pin/coma-free 108° self-converging yoke for CRTs with
super-flat faceplates, Society for Information Display International Symposium Digest of Technical
Papers, 26: 183–186, 1995.
17. J. F. Fisher and R. G. Clapp, Waveforms and spectra of composite video signals, in K. Benson and
J. Whitaker, Television Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill
Reinhold, 1992.
18. D. Pritchard, Standards and recommended practices, in K. Benson and J. Whitaker, Television
Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill Reinhold, 1992.
19. A. Vecht, Phosphors for color emissive displays, Society for Information Display International Sym-
posium Conference Seminar Notes F-2, 1995.
20. Optical Characteristics of Cathode Ray Tube Screens, EIA publication TEP116-C, Feb., 1993.
21. G. Wyszecki and W. S. Stiles, Color Science: Concepts and Methods, Quantitative Data and Formulae,
2nd ed., New York: John Wiley & Sons, 1982.
© 1999 by CRC Press LLC
22. A. Robertson and J. Fisher, Color vision, representation, and reproduction, in K. Benson and J.
Whitaker, Television Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill
Reinhold, 1992.
23. M. Maeda, Trinitron technology: current status and future trends, Society for Information Display
International Symposium Digest of Technical Papers, 27: 867–870, 1996.
24. C. Sherman, Field sequential color takes another step, Inf. Display, 11 (3): 12–15, March, 1995.
25. L. Ozawa, Helmet mounted 0.5 in. crt for SVGA images, Society for Information Display Interna-
tional Symposium Digest of Technical Papers, 26: 95–98, 1995.
26. C. Infante, CRT display measurements and quality, Society for Information Display International
Symposium Conference Seminar Notes M-3, 1995.
27. J. Whitaker, Electronic Displays, Technology, Design, and Applications, New York: McGraw-Hill, 1994.
28. P. Keller, Electronic Display Measurement, Concepts, Techniques, and Instrumentation, New York:
John Wiley & Sons, 1997.
Further Information
L. Ozawa, Cathodoluminescence: Theory and Applications, New York: Kodansha, 1990.
V. K. Zworykin and G. A. Morton, Television: The Electronics of Image Transmission in Color and Mono-
chrome, New York: John Wiley & Sons, 1954.
B. Wandell, The foundations of color measurement and color perception, Society for Information Display
International Symposium, Conference Seminar M-1, 1993. A nice brief introduction to color science
(31 pages).
Electronic Industries Association (EIA), 2500 Wilson Blvd., Arlington, VA 22201 (Internet: www.eia.org).
The Electronic Industries Association maintains a collection of over 1000 current engineering publi-
cations and standards. The EIA is an excellent source for information on CRT engineering, standards,
phosphors, safety, market information, and electronics in general.
The Society for Information Display (SID), 1526 Brookhollow Dr., Suite 82, Santa Ana, CA 92705-5421
(Internet: www.display.org). The Society for Information Display is a good source of engineering
research and development information on CRTs and information display technology in general.

Internet Resources:
The following is a brief list of places to begin looking on the World Wide Web for information on CRTs
and displays, standards, metrics, and current research. Also many of the manufacturers listed in Table
91.3 maintain Web sites with useful information.
The Society for Information Display
The Society of Motion Picture and Television Engineers
The Institute of Electrical and Electronics Engineers
The Electronic Industries Association
National Information Display Laboratory
The International Society for Optical Engineering
The Optical Society of America
Electronics & Electrical Engineering Laboratory
National Institute of Standards and Technology (NIST)
The Federal Communications Commission

www.display.org
www.smpte.org
www.ieee.org
www.eia.org
www.nta.org
www.spie.org
www.osa.org
www.eeel.nist.gov
www.nist.gov
www.fcc.gov